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* Revert "In visitSTORE, always use FindBetterChain, rather than only when ↵Nirav Dave2017-02-025-379/+380
| | | | | | | | | UseAA is enabled." This reverts commit r293893 which is miscompiling lua on ARM and bootstrapping for x86-windows. llvm-svn: 293915
* Revert "[ThinLTO] Add an auto-hide feature"Mehdi Amini2017-02-026-73/+41
| | | | | | This reverts r293912, bots are broken. llvm-svn: 293914
* [ThinLTO] Add an auto-hide featureMehdi Amini2017-02-026-41/+73
| | | | | | | | | | | | When a symbol is not exported outside of the DSO, it is can be hidden. Usually we try to internalize as much as possible, but it is not always possible, for instance a symbol can be referenced outside of the LTO unit, or there can be cross-module reference in ThinLTO. Differential Revision: https://reviews.llvm.org/D28978 llvm-svn: 293912
* [mips] Expansion of BEQL and BNEL with immediate operandsSimon Dardis2017-02-022-5/+30
| | | | | | | | | | | | Adds support for BEQL and BNEL macros with immediate operands. Patch by: Srdjan Obucina Reviewers: dsanders, zoran.jovanovic, vkalintiris, sdardis, obucina, seanbruno Differential Revision: https://reviews.llvm.org/D17040 llvm-svn: 293905
* Use N0 instead of N->getOperand(0) in DagCombiner::visitAdd. NFCAmaury Sechet2017-02-021-1/+1
| | | | llvm-svn: 293903
* [SystemZ] Add comment for ISD::FP_TO_UINT expansion.Jonas Paulsson2017-02-021-0/+3
| | | | | | | (Copied from the fp-conv-10.ll test to SystemZISelLowering.cpp) Review: Ulrich Weigand llvm-svn: 293900
* [Hexagon] Emitting individual instructions without copying themKrzysztof Parzyszek2017-02-022-97/+82
| | | | | | Patch by Colin LeMahieu. llvm-svn: 293899
* [JumpThread] Enhance finding partial redundant loads by continuing scanning ↵Jun Bum Lim2017-02-022-5/+24
| | | | | | | | | | | | | | | | single predecessor Summary: While scanning predecessors to find an available loaded value, if the predecessor has a single predecessor, we can continue scanning through the single predecessor. Reviewers: mcrosier, rengolin, reames, davidxl, haicheng Reviewed By: rengolin Subscribers: zzheng, llvm-commits Differential Revision: https://reviews.llvm.org/D29200 llvm-svn: 293896
* [Hexagon] Rename TypeCOMPOUND to TypeCJKrzysztof Parzyszek2017-02-028-16/+15
| | | | llvm-svn: 293894
* In visitSTORE, always use FindBetterChain, rather than only when UseAA is ↵Nirav Dave2017-02-025-380/+379
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enabled. Recommiting after fixing X86 inc/dec chain bug. * Simplify Consecutive Merge Store Candidate Search Now that address aliasing is much less conservative, push through simplified store merging search and chain alias analysis which only checks for parallel stores through the chain subgraph. This is cleaner as the separation of non-interfering loads/stores from the store-merging logic. When merging stores search up the chain through a single load, and finds all possible stores by looking down from through a load and a TokenFactor to all stores visited. This improves the quality of the output SelectionDAG and the output Codegen (save perhaps for some ARM cases where we correctly constructs wider loads, but then promotes them to float operations which appear but requires more expensive constant generation). Some minor peephole optimizations to deal with improved SubDAG shapes (listed below) Additional Minor Changes: 1. Finishes removing unused AliasLoad code 2. Unifies the chain aggregation in the merged stores across code paths 3. Re-add the Store node to the worklist after calling SimplifyDemandedBits. 4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is arbitrary, but seems sufficient to not cause regressions in tests. 5. Remove Chain dependencies of Memory operations on CopyfromReg nodes as these are captured by data dependence 6. Forward loads-store values through tokenfactors containing {CopyToReg,CopyFromReg} Values. 7. Peephole to convert buildvector of extract_vector_elt to extract_subvector if possible (see CodeGen/AArch64/store-merge.ll) 8. Store merging for the ARM target is restricted to 32-bit as some in some contexts invalid 64-bit operations are being generated. This can be removed once appropriate checks are added. This finishes the change Matt Arsenault started in r246307 and jyknight's original patch. Many tests required some changes as memory operations are now reorderable, improving load-store forwarding. One test in particular is worth noting: CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store forwarding converts a load-store pair into a parallel store and a memory-realized bitcast of the same value. However, because we lose the sharing of the explicit and implicit store values we must create another local store. A similar transformation happens before SelectionDAG as well. Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle llvm-svn: 293893
* [X86,ISEL] Fix X86 increment chain dependence calculationNirav Dave2017-02-021-0/+2
| | | | | | | | Merging Load-add-store pattern into a increment op previously dropped the load's chain from the instructions dependence if the store is chained to a TokenFactor. llvm-svn: 293892
* [ARM] GlobalISel: Lower pointer args and returnsDiana Picus2017-02-022-6/+35
| | | | | | | | | It is important to change the ArgInfo's type from pointer to integer, otherwise the CC assign function won't know what to do. Instead of hacking it up, we use ComputeValueVTs and introduce some of the helpers that we will need later on for lowering more complex types. llvm-svn: 293889
* [ARM] GlobalISel: Error out instead of assertingDiana Picus2017-02-021-1/+1
| | | | | | | | Allow unknown types in TLI.getValueType, otherwise we get asserts for certain types that we do not support yet (instead of returning that we don't support them and falling through the normal error path). llvm-svn: 293888
* [LICM] Hoist loads that are dominated by invariant.start intrinsic, and are ↵Anna Thomas2017-02-021-0/+62
| | | | | | | | | | | | | | | | | | invariant in the loop. Summary: We can hoist out loads that are dominated by invariant.start, to the preheader. We conservatively assume the load is variant, if we see a corresponding use of invariant.start (it could be an invariant.end or an escaping call). Reviewers: mkuper, sanjoy, reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29331 llvm-svn: 293887
* [ARM] GlobalISel: Legalize loading pointersDiana Picus2017-02-021-1/+1
| | | | | | | Make it legal to load pointer values. Also check that pointers are assigned to the GPR reg bank by default. llvm-svn: 293886
* [X86][SSE] Use MOVMSK for all_of/any_of reduction patternsSimon Pilgrim2017-02-021-0/+83
| | | | | | | | | | This is a first attempt at using the MOVMSK instructions to replace all_of/any_of reduction patterns (i.e. an and/or + shuffle chain). So far this only matches patterns where we are reducing an all/none bits source vector (i.e. a comparison result) but we should be able to expand on this in conjunction with improvements to 'bool vector' handling both in the x86 backend as well as the vectorizers etc. Differential Revision: https://reviews.llvm.org/D28810 llvm-svn: 293880
* [X86] Remove some unused DAGCombinerInfo parameters. NFCCraig Topper2017-02-021-7/+4
| | | | llvm-svn: 293873
* [X86] Move some INSERT_SUBVECTOR optimizations from legalize to DAG combine.Craig Topper2017-02-021-53/+74
| | | | | | | | This moves creation of SUBV_BROADCAST and merging of adjacent loads that are being inserted together. This is a step towards removing legalizing of INSERT_SUBVECTOR except for vXi1 cases. llvm-svn: 293872
* [LV] Also port failure remarks to new OptimizationRemarkEmitter APIAdam Nemet2017-02-023-19/+20
| | | | llvm-svn: 293866
* LTO: Link non-prevailing weak_odr or linkonce_odr globals into the combined ↵Peter Collingbourne2017-02-021-4/+17
| | | | | | | | | | | | module with available_externally linkage. These linkages mean that the ultimately prevailing symbol will have the same semantics as any non-prevailing copy of the symbol, so we are free to ignore the linker's resolution. Differential Revision: https://reviews.llvm.org/D29367 llvm-svn: 293865
* Linker: Move special casing for available_externally in IRMover to clients. ↵Peter Collingbourne2017-02-023-17/+24
| | | | | | | | | | NFCI. The goal is to simplify the semantic model for clients of IRMover. Differential Revision: https://reviews.llvm.org/D29435 llvm-svn: 293864
* [AVX-512] Fix the implicit defs for VZEROALL/VZEROUPPER to include YMM16-YMM31.Craig Topper2017-02-021-1/+3
| | | | llvm-svn: 293862
* InferAddressSpaces: Handle more cases with constant select operandsMatt Arsenault2017-02-021-11/+63
| | | | llvm-svn: 293859
* AMDGPU: Use source modifiers with f16->f32 conversionsMatt Arsenault2017-02-028-8/+84
| | | | | | | | | | | The operand types were defined to fit the fp16_to_fp node, which has the half as an integer type. v_cvt_f32_f16 does support source modifiers, so change this to have an FP type and modifiers. For targets without legal f16, this requires recognizing the bit operations and trying to produce them. llvm-svn: 293857
* RegisterCoalescer: Cleanup joinReservedPhysReg(); NFCMatthias Braun2017-02-021-9/+24
| | | | | | | | - Factor out a common subexpression - Add some helpful comments - Fix printing of a register in a debug message llvm-svn: 293856
* AArch64RegisterInfo: Simplify getReservedReg(); NFCMatthias Braun2017-02-021-12/+4
| | | | | | | After marking a 32bit register and all its super registers the 64bit register does not need to be marked again. llvm-svn: 293855
* NVPTX: Fix not preserving volatile when expanding memsetMatt Arsenault2017-02-021-3/+4
| | | | llvm-svn: 293851
* Fix LLDB Android AArch64 GCC debug info buildOmair Javaid2017-02-022-2/+2
| | | | | | | | | Committing after fixing suggested changes and tested release/debug builds on x86_64-linux and arm/aarch64 builds. Differential revision: https://reviews.llvm.org/D29042 llvm-svn: 293850
* Re-submit r293820: Return Error instead of bool from mergeTypeStreams().Rui Ueyama2017-02-021-17/+21
| | | | llvm-svn: 293847
* [IPSCCP] Restore the old behaviour (pre r293799).Davide Italiano2017-02-021-6/+1
| | | | | | | It's not clear the change I made a good idea, and it definitely needs further discussion. Thanks to Eli for pointing out. llvm-svn: 293846
* X86: Produce @ABS8 symbol modifiers for absolute symbols in range [0,128).Peter Collingbourne2017-02-023-3/+19
| | | | | | Differential Revision: https://reviews.llvm.org/D28689 llvm-svn: 293844
* InferAddressSpaces: clang-format some thingsMatt Arsenault2017-02-021-35/+35
| | | | llvm-svn: 293843
* Remove an assertion that doesn't hold when mixing -g and -gmlt throughPaul Robinson2017-02-011-3/+1
| | | | | | | | | | LTO. Replace it with a related assertion, ensuring that abstract variables appear only in abstract scopes. Part of PR31437. Differential Revision: http://reviews.llvm.org/D29430 llvm-svn: 293841
* [AMDGPU] Account workgroup size in LDS occupancy limitsStanislav Mekhanoshin2017-02-014-58/+25
| | | | | | | | | | | | | | | | | | Functions matching LDS use to occupancy return results for a workgroup of 64 workitems. The numbers has to be adjusted for bigger workgroups. For example a workgroup of size 256 already occupies 4 waves just by itself. Given that all numbers of LDS use in the compiler are per workgroup, occupancy shall be multiplied by 4 in this case. Each 64 workitems still limited by the same number, but 4 subrgoups 64 workitems each can afford 4 times more LDS to get the same occupancy. In addition change initializes LDS size in the subtarget to a real value for SI+ targets. This is required since LDS size is a variable in these calculations. Differential Revision: https://reviews.llvm.org/D29423 llvm-svn: 293837
* [AArch64] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-02-013-34/+59
| | | | | | other minor fixes (NFC). llvm-svn: 293836
* Change debug-info-for-profiling from a TargetOption to a function attribute.Dehao Chen2017-02-0110-18/+19
| | | | | | | | | | | | | | Summary: LTO requires the debug-info-for-profiling to be a function attribute. Reviewers: echristo, mehdi_amini, dblaikie, probinson, aprantl Reviewed By: mehdi_amini, dblaikie, aprantl Subscribers: aprantl, probinson, ahatanak, llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D29203 llvm-svn: 293833
* [libFuzzer] Disable afl tests on non-posix systems.Marcos Pividori2017-02-012-0/+4
| | | | | | | | AflDriver is not supported on non posix systems. Differential Revision: https://reviews.llvm.org/D29422 llvm-svn: 293830
* [libFuzzer] Disable equivalence tests on non posix systems.Marcos Pividori2017-02-011-0/+2
| | | | | | | | We can not run this test until we implement shared memory on Windows. Differential Revision: https://reviews.llvm.org/D29421 llvm-svn: 293829
* [libFuzzer] Isolate merge tests that require posix.Marcos Pividori2017-02-012-8/+23
| | | | | | Differential Revision: https://reviews.llvm.org/D29420 llvm-svn: 293828
* [libFuzzer] Add features `windows` and `posix` for lit tests.Marcos Pividori2017-02-013-0/+11
| | | | | | | | | | | | Add 2 features: posix and windows. Sometimes we want some specific tests only for posix and we use: REQUIRES: posix Sometimes we want some specific tests only for windows and we use: REQUIRES: windows Differential Revision: https://reviews.llvm.org/D29418 llvm-svn: 293827
* [libFuzzer] Accept different extensions.Marcos Pividori2017-02-011-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D29417 llvm-svn: 293826
* [libFuzzer] Fix test because cmd prompt does not expand wildcard.Marcos Pividori2017-02-011-1/+1
| | | | | | | | | | Commands should expand the wildcards on Windows, the cmd prompt doesn't. Because of that sancov was not finding the needed file. To deal with this, we use ls and xargs from gnu win utils. Differential Revision: https://reviews.llvm.org/D29374 llvm-svn: 293825
* Revert r293820: Return Error instead of bool from mergeTypeStreams().Rui Ueyama2017-02-011-21/+17
| | | | | | It broke buildbots. llvm-svn: 293824
* [ValueTracking] remove a FIXME for something we don't want to do; NFCSanjay Patel2017-02-011-4/+0
| | | | | | | | The comment was added with: https://reviews.llvm.org/rL293773 ...but there would be a cost to implement this and possibly no payoff. llvm-svn: 293823
* Return Error instead of bool from mergeTypeStreams().Rui Ueyama2017-02-011-17/+21
| | | | | | | | | | Previously, mergeTypeStreams returns only true or false, so it was impossible to know the reason if it failed. This patch changes the function signature so that it returns an Error object. Differential Revision: https://reviews.llvm.org/D29362 llvm-svn: 293820
* Remove an assertion that doesn't hold when mixing -g and -gmlt throughPaul Robinson2017-02-011-1/+0
| | | | | | | | LTO. Part of PR31437. Differential Revision: http://reviews.llvm.org/D29310 llvm-svn: 293818
* [InstCombine] move folds for shift-shift pairs; NFCISanjay Patel2017-02-011-48/+34
| | | | | | | | | | | Although this is 'no-functional-change-intended', I'm adding tests for shl-shl and lshr-lshr pairs because there is no existing test coverage for those folds. It seems like we should be able to remove some code from foldShiftedShift() at this point because we're handling those patterns on the general path. llvm-svn: 293814
* Shut up another GCC warning about operator precedence. NFC.Michael Kuperstein2017-02-011-1/+1
| | | | llvm-svn: 293812
* AMDGPU: Allow clustering flat memory operationsMatt Arsenault2017-02-011-1/+2
| | | | llvm-svn: 293809
* [JumpThread] No need to erase BB from LoopHeaders. NFC.Jun Bum Lim2017-02-011-14/+1
| | | | | | | | | | | | | | Summary: No need to try to ease BB from LoopHeaders as we already know that BB is not in LoopHeaders. Reviewers: hsung, majnemer, mcrosier, haicheng, rengolin Reviewed By: rengolin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29232 llvm-svn: 293802
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