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* Improve merging of stores from static constructors in GlobalOptAnthony Pesch2015-07-221-77/+249
| | | | | | | | | | | | | | | | | | | Summary: While working on a project I wound up generating a fairly large lookup table (10k entries) of callbacks inside of a static constructor. Clang was taking upwards of ~10 minutes to compile the lookup table. I generated a smaller test case (http://www.inolen.com/static_initializer_test.ll) that, after running with -ftime-report, pointed fingers at GlobalOpt and MemCpyOptimizer. Running globalopt took around ~9 minutes. The slowdown came from how GlobalOpt merged stores from static constructors individually into the global initializer in EvaluateStaticConstructor. For each store it discovered and wanted to commit, it would copy the existing global initializer and then merge in the individual store. I changed this so that stores are now grouped by global, and sorted from most significant to least significant by their GEP indexes (e.g. a store to GEP 0, 0 comes before GEP 0, 0, 1). With this representation, the existing initializer can be copied and all new stores merged into it in a single pass. With this patch and http://reviews.llvm.org/D11198, the lookup table that was taking ~10 minutes to compile now compiles in around 5 seconds. I've ran 'make check' and the test-suite, which all passed. I'm not really sure who to tag as a reviewer, Lang mentioned that Chandler may be appropriate. Reviewers: chandlerc, nlewycky Subscribers: nlewycky, llvm-commits Differential Revision: http://reviews.llvm.org/D11200 llvm-svn: 242935
* MIR Parser: Extract the MDNode parsing code into a separate method. NFC.Alex Lorenz2015-07-221-2/+11
| | | | | | | This change would allow the machine instruction parser to reuse this method when parsing the metadata node for the machine instruction's debug location property. llvm-svn: 242934
* Fix -Wextra-semi warnings.Hans Wennborg2015-07-226-6/+6
| | | | | | | | Patch by Eugene Zelenko! Differential Revision: http://reviews.llvm.org/D11400 llvm-svn: 242930
* Fix fetching the symbol table of a thin archive.Rafael Espindola2015-07-221-6/+11
| | | | | | We were trying to read it as an external file. llvm-svn: 242926
* De-duplicate Unix & Windows CallBacksToRunYaron Keren2015-07-223-20/+17
| | | | | | | | | Move CallBacksToRun into the common Signals.cpp, create RunCallBacksToRun() and use these in both Unix/Signals.inc and Windows/Signals.inc. Lots of potential code to be merged here. llvm-svn: 242925
* Test commit, added blank lineAnthony Pesch2015-07-221-0/+1
| | | | llvm-svn: 242923
* Simplify switch as all cases other than default return true. NFC.Chad Rosier2015-07-221-10/+0
| | | | llvm-svn: 242922
* Identify thin archives as archives.Rafael Espindola2015-07-221-1/+2
| | | | llvm-svn: 242921
* Remove C++98 workaround in llvm::sys::DontRemoveFileOnSignal()Yaron Keren2015-07-221-7/+0
| | | | llvm-svn: 242920
* MIR Serialization: Serialize the metadata machine operands.Alex Lorenz2015-07-224-0/+26
| | | | llvm-svn: 242916
* [ARM] Make the frame lowering code ready for shrink-wrapping.Quentin Colombet2015-07-223-119/+173
| | | | | | | | Shrink-wrapping can now be tested on ARM with -enable-shrink-wrap. Related to <rdar://problem/20821730> llvm-svn: 242908
* [X86][AVX512] add reduce/range/scalef/rndScaleAsaf Badouh2015-07-225-90/+203
| | | | | | | | include encoding and intrinsics Differential Revision: http://reviews.llvm.org/D11222 llvm-svn: 242896
* [GMR] Add a flag to enable GlobalsModRef in the normal compilationChandler Carruth2015-07-221-0/+11
| | | | | | | | | | | | | | | pipeline. Even before I started improving its runtime, it was already crazy fast once the call graph exists, and if we can get it to be conservatively correct, will still likely catch a lot of interesting and useful cases. So it may well be useful to enable by default. But more importantly for me, this should make it easier for me to test that changes aren't breaking it in fundamental ways by enabling it for normal builds. llvm-svn: 242895
* [GMR] Switch from std::set to SmallPtrSet. NFC.Chandler Carruth2015-07-221-3/+3
| | | | | | | | | This almost certainly doesn't matter in some deep sense, but std::set is essentially always going to be slower here. Now the alias query should be essentially constant time instead of having to chase the set tree each time. llvm-svn: 242893
* [GMR] Only look in the associated allocs map for an underlying value ifChandler Carruth2015-07-221-4/+4
| | | | | | | | it wasn't one of the indirect globals (which clearly cannot be an allocation function call). Also only do a single lookup into this map instead of two. NFC. llvm-svn: 242892
* [GMR] Switch to a DenseMap and clean up the iteration loop. NFC.Chandler Carruth2015-07-221-11/+6
| | | | | | | | | | | | | Since we have to iterate this map not that infrequently, we should use a map that is efficient for iteration. It is also almost certainly much faster for lookups as well. There is more to do in terms of reducing the wasted overhead of GMR's runtime though. Not sure how much is worthwhile though. The loop improvements should hopefully address the code review that Duncan gave when he saw this code as I moved it around. llvm-svn: 242891
* Fix a -Winconsistent-missing-override failure in the .intel_syntaxChandler Carruth2015-07-221-1/+1
| | | | | | patch. llvm-svn: 242890
* [PM/AA] Try to fix libc++ build bots which require the type used inChandler Carruth2015-07-221-40/+39
| | | | | | | std::list to be complete by hoisting the entire definition into the class. Ugly, but hopefully works. llvm-svn: 242888
* [X86] Add .intel_syntax noprefix directive to intel-syntax x86 asm outputMichael Kuperstein2015-07-223-0/+14
| | | | | | | Patch by: michael.zuckerman@intel.com Differential Revision: http://reviews.llvm.org/D11223 llvm-svn: 242886
* Fix mem2reg to correctly handle allocas only used in a single blockMichael Kuperstein2015-07-221-15/+23
| | | | | | | | | | | | | | | Currently, a load from an alloca that is used in as single block and is not preceded by a store is replaced by undef. This is not always correct if the single block is inside a loop. Fix the logic so that: 1) If there are no stores in the block, replace the load with an undef, as before. 2) If there is a store (regardless of where it is in the block w.r.t the load), bail out, and let the rest of mem2reg handle this alloca. Patch by: gil.rapaport@intel.com Differential Revision: http://reviews.llvm.org/D11355 llvm-svn: 242884
* [asan] Improve moving of non-instrumented allocasKuba Brecka2015-07-221-6/+12
| | | | | | | | In r242510, non-instrumented allocas are now moved into the first basic block. This patch limits that to only move allocas that are present *after* the first instrumented one (i.e. only move allocas up). A testcase was updated to show behavior in these two cases. Without the patch, an alloca could be moved down, and could cause an invalid IR. Differential Revision: http://reviews.llvm.org/D11339 llvm-svn: 242883
* [PM/AA] Remove all of the dead AliasAnalysis pointers being threadedChandler Carruth2015-07-2211-65/+51
| | | | | | | | | | through APIs that are no longer necessary now that the update API has been removed. This will make changes to the AA interfaces significantly less disruptive (I hope). Either way, it seems like a really nice cleanup. llvm-svn: 242882
* [PM/AA] Remove the last of the legacy update API from AliasAnalysis asChandler Carruth2015-07-229-49/+2
| | | | | | | | | | | | | part of simplifying its interface and usage in preparation for porting to work with the new pass manager. Note that this will likely expose that we have dead arguments, members, and maybe even pass requirements for AA. I'll be cleaning those up in seperate patches. This just zaps the actual update API. Differential Revision: http://reviews.llvm.org/D11325 llvm-svn: 242881
* [PM/AA] Switch to an early-exit. NFC. This was split out of anotherChandler Carruth2015-07-221-36/+35
| | | | | | | | | change because the diff is *useless*. I assure you, I just switched to early-return in this function. Cleanup in preparation for my next commit, as requested in code review! llvm-svn: 242880
* [PM/AA] Put the 'final' keyword in the correct place. And actuallyChandler Carruth2015-07-221-1/+1
| | | | | | succeed at compiling my change before committing it too! llvm-svn: 242879
* [PM/AA] Replace the only use of the AliasAnalysis::deleteValue API (inChandler Carruth2015-07-221-35/+58
| | | | | | | | | | | | | | | | | | | | | | GlobalsModRef) with CallbackVHs that trigger the same behavior. This is technically more expensive, but in benchmarking some LTO runs, it seems unlikely to even be above the noise floor. The only way I was able to measure the performance of GMR at all was to run nothing else but this one analysis on a linked clang bitcode file. The call graph analysis still took 5x more time than GMR, and this change at most made GMR 2% slower (this is well within the noise, so its hard for me to be sure that this is an actual change). However, in a real LTO run over the same bitcode, the GMR run takes so little time that the pass timers don't measure it. With this, I can remove the last update API from the AliasAnalysis interface, but I'll actually remove the interface hook point in a follow-up commit. Differential Revision: http://reviews.llvm.org/D11324 llvm-svn: 242878
* AVX-512: Added intrinsics for VCVT* instructions.Elena Demikhovsky2015-07-222-7/+181
| | | | | | | | All SKX forms. All VCVT instructions for float/double/int/long types. Differential Revision: http://reviews.llvm.org/D11343 llvm-svn: 242877
* [LoopUnswitch] Code refactoring to separate trivial loop unswitch and ↵Chen Li2015-07-221-96/+112
| | | | | | | | | | | | | | non-trivial loop unswitch in processCurrentLoop() Summary: The current code in LoopUnswtich::processCurrentLoop() mixes trivial loop unswitch and non-trivial loop unswitch together. It goes over all basic blocks in the loop and checks if a condition is trivial or non-trivial unswitch condition. However, trivial unswitch condition can only occur in the loop header basic block (where it controls whether or not the loop does something at all). This refactoring separate trivial loop unswitch and non-trivial loop unswitch. Before going over all basic blocks in the loop, it checks if the loop header contains a trivial unswitch condition. If so, unswitch it. Otherwise, go over all blocks like before but don't check trivial condition any more since they are not possible to be in the other blocks. This code has no functionality change. Reviewers: meheff, reames, broune Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11276 llvm-svn: 242873
* [BranchFolding] do not iterate the aliases of virtual registersJingyue Wu2015-07-222-16/+28
| | | | | | | | | | | | | | | | | Summary: MCRegAliasIterator only works for physical registers. So, do not run it on virtual registers. With this issue fixed, we can resurrect the BranchFolding pass in NVPTX backend. Reviewers: jholewinski, bkramer Subscribers: henryhu, meheff, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11174 llvm-svn: 242871
* [SROA] Fix a nasty pile of bugs to do with big-endian, different allocaChandler Carruth2015-07-221-11/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | types and loads, loads or stores widened past the size of an alloca, etc. This started off with a bug report about big-endian behavior with bitfields and loads and stores to a { i32, i24 } struct. An initial attempt to fix this was sent for review in D10357, but that didn't really get to the root of the problem. The core issue was that canConvertValue and convertValue in SROA were handling different bitwidth integers by doing a zext of the integer. It wouldn't do a trunc though, only a zext! This would in turn lead SROA to form an i24 load from an i24 alloca, zext it to i32, and then use it. This would at least produce the wrong value for big-endian systems. One of my many false starts here was to correct the computation for big-endian systems by shifting. But this doesn't actually work because the original code has a 64-bit store to the entire 8 bytes, and a 32-bit load of the last 4 bytes, and because the alloc size is 8 bytes, we can't lose that last (least significant if bigendian) byte! The real problem here is that we're forming an i24 load in SROA which is actually not sufficiently wide to load all of the necessary bits here. The source has an i32 load, and SROA needs to form that as well. The straightforward way to do this is to disable the zext logic in canConvertValue and convertValue, forcing us to actually load all 32-bits. This seems like a really good change, but it in turn breaks several other parts of SROA. First in the chain of knock-on failures, we had places where we were doing integer-widening promotion even though some of the integer loads or stores extended *past the end* of the alloca's memory! There was even a comment about preventing this, but it only prevented the case where the type had a different bit size from its store size. So I added checks to handle the cases where we actually have a widened load or store and to avoid trying to special integer widening promotion in those cases. Second, we actually rely on the ability to promote in the face of loads past the end of an alloca! This is important so that we can (for example) speculate loads around PHI nodes to do more promotion. The bits loaded are garbage, but as long as they aren't used and the alignment is suitable high (which it wasn't in the test case!) this is "fine". And we can't stop promoting here, lots of things stop working well if we do. So we need to add specific logic to handle the extension (and truncation) case, but *only* where that extension or truncation are over bytes that *are outside the alloca's allocated storage* and thus totally bogus to load or store. And of course, once we add back this correct handling of extension or truncation, we need to correctly handle bigendian systems to avoid re-introducing the exact bug that started us off on this chain of misery in the first place, but this time even more subtle as it only happens along speculated loads atop a PHI node. I've ported an existing test for PHI speculation to the big-endian test file and checked that we get that part correct, and I've added several more interesting big-endian test cases that should help check that we're getting this correct. Fun times. llvm-svn: 242869
* [Fuzzer] Rely on $PATH expansion instead of hardcoding paths in tests. NFC.Alexey Samsonov2015-07-213-14/+15
| | | | llvm-svn: 242851
* [Fuzzer] Clearly separate regular and DFSan tests. NFC.Alexey Samsonov2015-07-215-7/+10
| | | | llvm-svn: 242850
* MIR Serialization: Start serializing the CFI operands with .cfi_def_cfa_offset.Alex Lorenz2015-07-214-1/+56
| | | | | | | | This commit begins serialization of the CFI index machine operands by serializing one kind of CFI instruction - the .cfi_def_cfa_offset instruction. Reviewers: Duncan P. N. Exon Smith llvm-svn: 242845
* Fix a performance problem in memcpyopt by removing a linear scan over ranges ↵Nick Lewycky2015-07-211-16/+9
| | | | | | when inserting a new range. No functionality change intended. Patch by Anthony Pesch! llvm-svn: 242843
* [MDA] change BlockScanLimit into a command line option.Jingyue Wu2015-07-211-1/+5
| | | | | | | | | | | | | | | | | | | | Summary: In the benchmark (https://github.com/vetter/shoc) we are researching, the duplicated load is not eliminated because MemoryDependenceAnalysis hit the BlockScanLimit. This patch change it into a command line option instead of a hardcoded value. Patched by Xuetian Weng. Test Plan: test/Analysis/MemoryDependenceAnalysis/memdep-block-scan-limit.ll Reviewers: jingyue, reames Subscribers: reames, llvm-commits Differential Revision: http://reviews.llvm.org/D11366 llvm-svn: 242842
* [AsmPrinter] Check for valid constants in handleIndirectSymViaGOTPCRelBruno Cardoso Lopes2015-07-211-1/+1
| | | | | | | | | Check whether BaseCst is valid before extracting a GlobalValue. This fixes PR24163. Patch by David Majnemer. llvm-svn: 242840
* [PPC64LE] More vector swap optimization TLCBill Schmidt2015-07-211-21/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes one substantive change and a few stylistic changes to the VSX swap optimization pass. The substantive change is to permit LXSDX and LXSSPX instructions to participate in swap optimization computations. The previous change to insert a swap following a SUBREG_TO_REG widening operation makes this almost trivial. I experimented with also permitting STXSDX and STXSSPX instructions. This can be done using similar techniques: we could insert a swap prior to a narrowing COPY operation, and then permit these stores to participate. I prototyped this, but discovered that the pattern of a narrowing COPY followed by an STXSDX does not occur in any of our test-suite code. So instead, I added commentary indicating that this could be done. Other TLC: - I changed SH_COPYSCALAR to SH_COPYWIDEN to more clearly indicate the direction of the copy. - I factored the insertion of swap instructions into a separate function. Finally, I added a new test case to check that the scalar-to-vector loads are working properly with swap optimization. llvm-svn: 242838
* MIR Parser: Reuse the function 'lexName' when lexing global value tokens. NFC.Alex Lorenz2015-07-211-31/+19
| | | | | | | This commit refactors the function 'maybeLexGlobalValue' so that now it reuses the function 'lexName' when lexing a named global value token. llvm-svn: 242837
* [SCEV][NFC] Fix a typo in a comment.Sanjoy Das2015-07-211-6/+6
| | | | llvm-svn: 242834
* [RewriteStatepointsForGC] minor style cleanupPhilip Reames2015-07-211-26/+25
| | | | | | Use a named lambda for readability, common some code, remove a stale comments, and use llvm style variable names. llvm-svn: 242827
* Follow up to r242810. NFC.Chad Rosier2015-07-211-1/+1
| | | | llvm-svn: 242812
* [AArch64] Simplify the passing of arguments. NFC.Chad Rosier2015-07-211-23/+37
| | | | | | This is setup for future work planned for the AArch64 Load/Store Opt pass. llvm-svn: 242810
* Re-land 242726 to use RAII to do cleanupReid Kleckner2015-07-211-0/+50
| | | | | | | The LooksLikeCodeInBug11395() codepath was returning without clearing the ProcessedAllocas cache. llvm-svn: 242809
* [RewriteStatepointsForGC] Hoist some code out of a loopPhilip Reames2015-07-211-12/+13
| | | | llvm-svn: 242808
* MergeFunc: Transfer the callee's attributes when replacing a direct callerArnold Schwaighofer2015-07-211-0/+19
| | | | | | | | | | We insert a bitcast which obfuscates the getCalledFunction for the utility function which looks up attributes from the called function. Loosing ABI changing parameter attributes is a bad thing. rdar://21516488 llvm-svn: 242807
* MIR Serialization: Serialize the external symbol machine operands.Alex Lorenz2015-07-215-1/+65
| | | | | Reviewers: Duncan P. N. Exon Smith llvm-svn: 242806
* [RewriteStatepointsForGC] Delete trivial codePhilip Reames2015-07-211-13/+5
| | | | | | A bit more code cleanup: delete some a trivial true assertion and supporting code, remove a redundant cast, and use count in assertions where feasible. llvm-svn: 242805
* IR: Extract a function 'printLLVMNameWithoutPrefix' from 'PrintLLVMName'. NFC.Alex Lorenz2015-07-211-14/+26
| | | | | | | | | | | | | This commit extracts the code that prints out a name of an LLVM value without a prefix from a function 'PrintLLVMName' into a publicly accessible function named 'printLLVMNameWithoutPrefix'. This change would be useful for MIR serialization, as it would allow the MIR printer to reuse this function to print out the names of the external symbol machine operands. Reviewers: Duncan P. N. Exon Smith llvm-svn: 242803
* fix formatting; NFCSanjay Patel2015-07-211-2/+2
| | | | llvm-svn: 242796
* Revert 242726, it broke ASan on OS X.Nico Weber2015-07-211-40/+0
| | | | llvm-svn: 242792
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