summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* [InstSimplify] Missed optimization in math expression: squashing exp(log), ↵Dmitry Venikov2018-01-031-6/+33
| | | | | | | | | | | | | | | | log(exp) Summary: This patch enables folding following expressions under -ffast-math flag: exp(log(x)) -> x, exp2(log2(x)) -> x, log(exp(x)) -> x, log2(exp2(x)) -> x Reviewers: spatel, hfinkel, davide Reviewed By: spatel, hfinkel, davide Subscribers: scanon, llvm-commits Differential Revision: https://reviews.llvm.org/D41381 llvm-svn: 321710
* [ARM][NFC] Avoid recreating MCSubtargetInfo in ARMAsmBackendAlex Bradbury2018-01-036-36/+31
| | | | | | | | | | | | | After D41349, we can now directly access MCSubtargetInfo from createARM*AsmBackend. This patch makes use of this, avoiding the need to create a fresh MCSubtargetInfo (which was previously always done with a blank CPU and feature string). Given the total size of the change remains pretty tiny and we're removing the old explicit destructor, I changed the STI field to a reference rather than a pointer. Differential Revision: https://reviews.llvm.org/D41693 llvm-svn: 321707
* [AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors.Sander de Smalen2018-01-033-11/+52
| | | | | | | | | | | | | | | | | Summary: Add a register class for SVE predicate operands that can only be p0-p7 (as opposed to p0-p15) Patch [1/3] in a series to add predicated ADD/SUB instructions for SVE. Reviewers: rengolin, mcrosier, evandro, fhahn, echristo, olista01, SjoerdMeijer, javed.absar Reviewed By: fhahn Subscribers: aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D41441 llvm-svn: 321699
* Fix build of WebAssembly and AVR backends after r321692Alex Bradbury2018-01-033-7/+8
| | | | | | | As experimental backends, I didn't have them configured to build in my local build config. llvm-svn: 321696
* Thread MCSubtargetInfo through Target::createMCAsmBackendAlex Bradbury2018-01-0325-72/+89
| | | | | | | | | | | | | | | | | | | | | Currently it's not possible to access MCSubtargetInfo from a TgtMCAsmBackend. D20830 threaded an MCSubtargetInfo reference through MCAsmBackend::relaxInstruction, but this isn't the only function that would benefit from access. This patch removes the Triple and CPUString arguments from createMCAsmBackend and replaces them with MCSubtargetInfo. This patch just changes the interface without making any intentional functional changes. Once in, several cleanups are possible: * Get rid of the awkward MCSubtargetInfo handling in ARMAsmBackend * Support 16-bit instructions when valid in MipsAsmBackend::writeNopData * Get rid of the CPU string parsing in X86AsmBackend and just use a SubtargetFeature for HasNopl * Emit 16-bit nops in RISCVAsmBackend::writeNopData if the compressed instruction set extension is enabled (see D41221) This change initially exposed PR35686, which has since been resolved in r321026. Differential Revision: https://reviews.llvm.org/D41349 llvm-svn: 321692
* [GlobalISel][Legalizer] Fix legalization of llvm.smul.with.overflowAmara Emerson2018-01-031-1/+15
| | | | | | | | | Previously the code for handling G_SMULO didn't properly check for the signed multiply overflow, instead treating it the same as the unsigned G_UMULO. Fixes PR35800. llvm-svn: 321690
* Handle the case of live 16-bit subregisters in X86FixupBWInstsAndrew Kaylor2018-01-021-82/+71
| | | | | | | Differential Revision: https://reviews.llvm.org/D40524 Change-Id: Ie3a405b28503ceae999f5f3ba07a68fa733a2400 llvm-svn: 321674
* [ValueTracking] recognize min/max of min/max patternsSanjay Patel2018-01-021-0/+79
| | | | | | | | | | | | | | | | | | | | | | This is part of solving PR35717: https://bugs.llvm.org/show_bug.cgi?id=35717 The larger IR optimization is proposed in D41603, but we can show the improvement in ValueTracking using codegen tests because SelectionDAG creates min/max nodes based on ValueTracking. Any target with min/max ops should show wins here. I chose AArch64 vector ops because they're clean and uniform. Some Alive proofs for the tests (can't put more than 2 tests in 1 page currently because the web app says it's too long): https://rise4fun.com/Alive/WRN https://rise4fun.com/Alive/iPm https://rise4fun.com/Alive/HmY https://rise4fun.com/Alive/CNm https://rise4fun.com/Alive/LYf llvm-svn: 321672
* [AArch64][GlobalISel] Fix assert fail with unknown intrinsic.Amara Emerson2018-01-021-5/+8
| | | | | | | | A call may have an intrinsic name but not have a valid intrinsic ID, for example with llvm.invariant.group.barrier. If so, treat it as a normal call like FastISel does. llvm-svn: 321662
* [x86] allow pairs of PCMPEQ for vector-sized integer equality comparisons ↵Sanjay Patel2018-01-021-7/+31
| | | | | | | | | | | | | | | | | | (PR33325) This is an extension of D31156 with the goal that we'll allow memcmp() == 0 expansion for x86 to use 2 pairs of loads per block. The memcmp expansion pass (formerly part of CGP) will generate this kind of pattern with oversized integer compares, so we want to transform these into x86-specific vector nodes before legalization splits things into scalar chunks. See PR33325 for more details: https://bugs.llvm.org/show_bug.cgi?id=33325 Differential Revision: https://reviews.llvm.org/D41618 llvm-svn: 321656
* [AArch64][GlobalISel] Enable GlobalISel at -O0 by defaultAmara Emerson2018-01-022-3/+11
| | | | | | | | | | | Tests updated to explicitly use fast-isel at -O0 instead of implicitly. This change also allows an explicit -fast-isel option to override an implicitly enabled global-isel. Otherwise -fast-isel would have no effect at -O0. Differential Revision: https://reviews.llvm.org/D41362 llvm-svn: 321655
* [BasicBlockUtils] Check for unreachable preds before updating LI in ↵Anna Thomas2018-01-021-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | UpdateAnalysisInformation Summary: We are incorrectly updating the LI when loop-simplify generates dedicated exit blocks for a loop. The issue is that there's an implicit assumption that the Preds passed into UpdateAnalysisInformation are reachable. However, this is not true and breaks LI by incorrectly updating the header of a loop. One such case is when we generate dedicated exits when the exit block is a landing pad (through SplitLandingPadPredecessors). There maybe other cases as well, since we do not guarantee that Preds passed in are reachable basic blocks. The added test case shows how loop-simplify breaks LI for the outer loop (and DT in turn) after we try to generate the LoopSimplifyForm. Reviewers: davide, chandlerc, sanjoy Reviewed By: davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41519 llvm-svn: 321653
* [Hexagon] Fix generation of vector sign extensionsKrzysztof Parzyszek2018-01-021-17/+27
| | | | llvm-svn: 321650
* Revert r321089: "[DAG] Elide overlapping store" (and subsequent fix in r321204)Daniel Jasper2018-01-021-21/+21
| | | | | | | Our internal testing has revealed has discovered bugs in PPC builds. I have forward reproduction instructions to the original author (Nirav). llvm-svn: 321649
* [AArch64][AsmParser] Add isScalarReg() and repurpose isReg()Sander de Smalen2018-01-021-10/+14
| | | | | | | | | | | | | | | | | Summary: isReg() in AArch64AsmParser.cpp is a bit of a misnomer, and would be better named 'isScalarReg()' instead. Patch [1/3] in a series to add operand constraint checks for SVE's predicated ADD/SUB. Reviewers: rengolin, mcrosier, evandro, fhahn, echristo Reviewed By: fhahn Subscribers: aemerson, javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D41445 llvm-svn: 321646
* Strip trailing whitespace. NFCISimon Pilgrim2018-01-021-2/+2
| | | | llvm-svn: 321644
* [RISCV] Add Defs Uses information for c.jal and c.addi4spnAlex Bradbury2018-01-021-2/+2
| | | | | | | Differential Revision: https://reviews.llvm.org/D41339 Patch by Shiva Chen. llvm-svn: 321643
* [RISCV][NFC] Resolve unused variable warning in RISCVISelLoweringAlex Bradbury2018-01-021-2/+1
| | | | | | XLenVT in LowerFormalArguments is used only in an assert. llvm-svn: 321642
* [DAGCombine] Fix for PR35765Sam Parker2018-01-021-1/+0
| | | | | | | | | | | Remove the acceptance of ANY_EXTEND nodes while trying to move and nodes back to loads. Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=35765 Differential Revision: https://reviews.llvm.org/D41625 llvm-svn: 321641
* [SelectionDAG] Teach WidenVecOp_Convert to widen the operation if a widened ↵Craig Topper2018-01-021-4/+13
| | | | | | result type would still be legal. llvm-svn: 321638
* [InstCombine] Missed optimization in math expression: squashing sqrt functionsDmitry Venikov2018-01-021-0/+17
| | | | | | | | | | | | | | Summary: This patch enables folding under -ffast-math flag sqrt(a) * sqrt(b) -> sqrt(a*b) Reviewers: hfinkel, spatel, davide Reviewed By: spatel, davide Subscribers: davide, llvm-commits Differential Revision: https://reviews.llvm.org/D41322 llvm-svn: 321637
* Test commitDmitry Venikov2018-01-021-1/+1
| | | | | | | | | | Reviewers: Quolyk Reviewed By: Quolyk Differential Revision: https://reviews.llvm.org/D41561 llvm-svn: 321636
* [SelectionDAG] Remove ifs on getTypeAction being TypeWidenVector from some ↵Craig Topper2018-01-021-9/+11
| | | | | | | | of the WideVecOp handlers. We should only be in the handler if the tyep action is TypeWidenVector. There's no reason to try to do anything else. llvm-svn: 321635
* [ValueTracking] Don't assume shift values are in rangeSimon Pilgrim2018-01-011-4/+4
| | | | | | Reduced (as best I could...) from oss-fuzz #4857 test case llvm-svn: 321634
* [X86] Promote vXi1 fp_to_uint/fp_to_sint to vXi32 to avoid scalarization.Craig Topper2018-01-011-1/+32
| | | | llvm-svn: 321632
* [X86] Replace custom lowering of vXi1 SINT_TO_FP/UINT_TO_FP with promotion.Craig Topper2018-01-011-32/+20
| | | | | | The custom lowering was just doing the same thing promotion would do. llvm-svn: 321630
* [SelectionDAG][X86][AArch64] Require targets to specify the promotion type ↵Craig Topper2018-01-013-51/+35
| | | | | | | | | | | | | | | | when using setOperationAction Promote for INT_TO_FP and FP_TO_INT Currently the promotion for these ignores the normal getTypeToPromoteTo and instead just tries to double the element width. This is because the default behavior of getTypeToPromote to just adds 1 to the SimpleVT, which has the affect of increasing the element count while keeping the scalar size the same. If multiple steps are required to get to a legal operation type, int_to_fp will be promoted multiple times. And fp_to_int will keep trying wider types in a loop until it finds one that works. getTypeToPromoteTo does have the ability to query a promotion map to get the type and not do the increasing behavior. It seems better to just let the target specify the promotion type in the map explicitly instead of letting the legalizer iterate via widening. FWIW, it's worth I think for any other vector operations that need to be promoted, we have to specify the type explicitly because the default behavior of getTypeToPromote isn't useful for vectors. The other types of promotion already require either the element count is constant or the total vector width is constant, but neither happens by incrementing the SimpleVT enum. Differential Revision: https://reviews.llvm.org/D40664 llvm-svn: 321629
* [X86] In LowerTruncateVecI1, don't add SHL if the input is known to be all ↵Craig Topper2018-01-011-10/+16
| | | | | | | | sign bits. If the input is all sign bits then the LSB through MSB are all the same so we don't need to be move the LSB to the MSB. llvm-svn: 321617
* [X86] Add missing NoVLX predicate around some patterns that use zmm ↵Craig Topper2018-01-011-1/+1
| | | | | | registers to implement 128/256-bit operations without VLX. llvm-svn: 321613
* [X86] Add patterns for using zmm registers for v8i32/v8f32 vselect with the ↵Craig Topper2018-01-011-19/+24
| | | | | | | | false input being zero. We can use zmm move with zero masking for this. We already had patterns for using a masked move, but we didn't check for the zero masking case separately. llvm-svn: 321612
* [X86] Use CONCAT_VECTORS instead of INSERT_SUBVECTOR for padding v4i1/v2i1 ↵Craig Topper2017-12-311-3/+4
| | | | | | | | | | vector to v8i1 pre-legalize. The CONCAT_VECTORS will be lowered to INSERT_SUBVECTOR later. In the modified cases this seems to be enough to trick a later DAG combine into running in a different order than allows the ANDs to be removed. I'll admit this is a bit of a hack that happens to work, but using CONCAT_VECTORS is more consistent with other legalization code anyway. llvm-svn: 321611
* [X86][AVX2] Combine extract(broadcast(scalar_value)) --> scalar_valueSimon Pilgrim2017-12-311-0/+5
| | | | | | As it has a scalar source we don't treat it as a target shuffle so needs special handling. llvm-svn: 321610
* [X86][SSE] Don't vectorize splat buildvector of binops (PR30780)Simon Pilgrim2017-12-311-0/+4
| | | | | | Don't combine buildvector(binop(),binop(),binop(),binop()) -> binop(buildvector(), buildvector()) if its a splat - keep the binop scalar and just splat the result to avoid large vector constants. llvm-svn: 321607
* [SimplifyCFG] Return to the pass manager the correct value.Davide Italiano2017-12-311-1/+1
| | | | | | | I wanted to commit this with r321603, but I failed to squash the two commits. llvm-svn: 321606
* [Utils/Local] Use `auto` when the type is obvious. NFCI.Davide Italiano2017-12-311-6/+6
| | | | llvm-svn: 321605
* [Utils] Remove commented debug message. NFCI.Davide Italiano2017-12-311-4/+0
| | | | llvm-svn: 321604
* [SimplifyCFG] Stop hoisting musttail calls incorrectly.Davide Italiano2017-12-311-0/+11
| | | | | | PR35774. llvm-svn: 321603
* [X86] Add a DAG combine to widen (i4 (bitcast (v4i1))) before type ↵Craig Topper2017-12-311-0/+12
| | | | | | | | legalization sees the i4 and changes to load/store. Same for v2i1 and i2. llvm-svn: 321602
* [X86] Add a DAG combine to fix (v4i1 (bitcast (i4))) before type ↵Craig Topper2017-12-311-1/+14
| | | | | | | | legalization sees the i4 and changes to load/store. Same for i2 and v2i1. llvm-svn: 321601
* [MC] - Stop ignoring invalid meta data symbols.George Rimar2017-12-311-1/+1
| | | | | | | | | | | Previously llvm-mc would silently accept code from testcase, that contains invalid metadata symbol in section declaration. Patch fixes the issue. Differential revision: https://reviews.llvm.org/D41641 llvm-svn: 321599
* [X86] Prevent combining (v8i1 (bitconvert (i8 load)))->(v8i1 load) if we ↵Craig Topper2017-12-313-0/+12
| | | | | | | | don't have DQI. We end up using an i8 load via an isel pattern from v8i1 anyway. This just makes it more explicit. This seems to improve codgen in some cases and I'd like to kill off some of the load patterns. llvm-svn: 321598
* [X86] Remove patterns for load/store of vXi with bitcasts to/from integer.Craig Topper2017-12-311-19/+0
| | | | | | This is better handled by a DAG combine if its not already being done. No lit tests fail from the removal of these patterns. llvm-svn: 321597
* [X86] Remove AND32ri8 from pattern for v1i1 load.Craig Topper2017-12-311-1/+1
| | | | | | I don't think anything would actually expect the other bits to be zero. llvm-svn: 321596
* [X86] Fix a crash when returning a <1 x i1> value>Craig Topper2017-12-311-0/+4
| | | | llvm-svn: 321595
* [X86] Cleanup store splitting in LowerTruncatingStoreCraig Topper2017-12-311-4/+5
| | | | | | Use getMemBasePlusOffset and calculate proper pointer info and alignment for the second store. llvm-svn: 321594
* Added support for reading configuration filesSerge Pavlov2017-12-301-0/+48
| | | | | | | | | | | | | Configuration file is read as a response file in which file names in the nested constructs `@file` are resolved relative to the directory where the including file resides. Lines in which the first non-whitespace character is '#' are considered as comments and are skipped. Trailing backslashes are used to concatenate lines in the same way as they are used in shell scripts. Differential Revision: https://reviews.llvm.org/D24926 llvm-svn: 321586
* Use phi ranges to simplify code. No functionality change intended.Benjamin Kramer2017-12-3031-476/+289
| | | | llvm-svn: 321585
* Reverted 321580: Added support for reading configuration filesSerge Pavlov2017-12-301-47/+0
| | | | | | It caused buildbot fails. llvm-svn: 321582
* Added support for reading configuration filesSerge Pavlov2017-12-301-0/+47
| | | | | | | | | | | | | Configuration file is read as a response file in which file names in the nested constructs `@file` are resolved relative to the directory where the including file resides. Lines in which the first non-whitespace character is '#' are considered as comments and are skipped. Trailing backslashes are used to concatenate lines in the same way as they are used in shell scripts. Differential Revision: https://reviews.llvm.org/D24926 llvm-svn: 321580
* [PowerPC] fix a bug in TCO eligibility checkHiroshi Inoue2017-12-301-6/+29
| | | | | | | | | | If the callee and caller use different calling convensions, we cannot apply TCO if the callee requires arguments on stack; e.g. C calling convention and Fast CC use the same registers for parameter passing, but the stack offset is not necessarily same. This patch also recommit r319218 "[PowerPC] Allow tail calls of fastcc functions from C CallingConv functions." by @sfertile since the problem reported in r320106 should be fixed. Differential Revision: https://reviews.llvm.org/D40893 llvm-svn: 321579
OpenPOWER on IntegriCloud