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* [mips] Fold FeatureSwap into FeatureMips32r2 and FeatureMips64r2Daniel Sanders2014-05-127-23/+14
| | | | | | | | | | | | | | | | | Summary: dsbh and dshd are not available on Mips32r2. No codegen test changes required since expansion of i64 prevented the use of these instructions anyway. Depends on D3690 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3692 llvm-svn: 208542
* [mips] Replace FeatureFPIdx with FeatureMips4_32r2Daniel Sanders2014-05-126-31/+40
| | | | | | | | | | | | | | | | | Summary: No functional change. The minor change to the MIPS16 code is in preparation for a patch that will handle 32-bit FPIdx instructions separately to 64-bit (because they were added in different revisions) Depends on D3677 Reviewers: rkotler, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3690 llvm-svn: 208541
* [ARM64] Add proper bounds checking/diagnostics to logical shiftsBradley Smith2014-05-123-22/+43
| | | | llvm-svn: 208540
* ARM: Implement big endian bit-conversion for NEON typeChristian Pirker2014-05-123-56/+142
| | | | llvm-svn: 208538
* X86ISelLowering.cpp:LowerINTRINSIC_W_CHAIN(): Prune impossible "default:" ↵NAKAMURA Takumi2014-05-121-3/+0
| | | | | | [-Wcovered-switch-default] llvm-svn: 208533
* Fix type of shuffle obtained from reordering with binary operationSerge Pavlov2014-05-121-1/+1
| | | | | | | | In transformation: BinOp(shuffle(v1,undef), shuffle(v2,undef)) -> shuffle(BinOp(v1, v2),undef) type of the undef argument must be same as type of BinOp. llvm-svn: 208531
* [ARM64] Add diagnostics for bitfield extract/insert instructionsBradley Smith2014-05-121-19/+54
| | | | | | | | Unfortunately, since ARM64 models all these instructions as aliases, the checks need to be done at the time the alias is seen rather than during instruction validation as AArch64 does it. llvm-svn: 208529
* [ARM64] Correct more bounds checks/diagnostics for arithmetic shift operandsBradley Smith2014-05-122-10/+18
| | | | llvm-svn: 208528
* [ARM64] Move register/register MOV handling into tablegen and improve ↵Bradley Smith2014-05-124-54/+26
| | | | | | diagnostics llvm-svn: 208527
* Fixed compilation issueElena Demikhovsky2014-05-121-0/+1
| | | | llvm-svn: 208524
* AVX-512: changes in intrinsicsElena Demikhovsky2014-05-124-192/+231
| | | | | | | | | 1) Changed gather and scatter intrinsics. Now they are aligned with GCC built-ins. There is no more non-masked form. Masked intrinsic receives -1 if all lanes are executed. 2) I changed the function that works with intrinsics inside X86ISelLowering.cpp. I put all intrinsics in one table. I did it for INTRINSICS_W_CHAIN and plan to put all intrinsics from WO_CHAIN set to the same table in order to avoid the long-long "switch". (I wanted to use static map initialization that allowed by C++11 but I wasn't able to compile it on VS2012). 3) I added gather/scatter prefetch intrinsics. 4) I fixed MRMm encoding for masked instructions. llvm-svn: 208522
* CodeGen: add parenthesis around complex expressionSaleem Abdulrasool2014-05-121-5/+5
| | | | | | Add missing parenthesis suggested by GCC. NFC. llvm-svn: 208519
* Fix reordering of shuffles and binary operationsSerge Pavlov2014-05-121-0/+1
| | | | | | | | | | | | Do not apply transformation: BinOp(shuffle(v1), shuffle(v2)) -> shuffle(BinOp(v1, v2)) if operands v1 and v2 are of different size. This change fixes PR19717, which was caused by r208488. llvm-svn: 208518
* Fix return before elseMatt Arsenault2014-05-111-18/+18
| | | | llvm-svn: 208510
* [PowerPC] Add global named register supportHal Finkel2014-05-112-0/+27
| | | | | | | Support for the intrinsics that read from and write to global named registers is added for r1, r2 and r13 (depending on the subtarget). llvm-svn: 208509
* Pass the value type to TLI::getRegisterByNameHal Finkel2014-05-119-10/+14
| | | | | | | | | | | | | We must validate the value type in TLI::getRegisterByName, because if we don't and the wrong type was used with the IR intrinsic, then we'll assert (because we won't be able to find a valid register class with which to construct the requested copy operation). For PPC64, additionally, the type information is necessary to decide between the 64-bit register and the 32-bit subregister. No functionality change. llvm-svn: 208508
* Add 'override' to getRegisterByName in *ISelLowering.hHal Finkel2014-05-114-4/+4
| | | | | | No functionality change intended. llvm-svn: 208507
* DebugInfo: Include lexical scopes in inlined subroutines.David Blaikie2014-05-112-17/+35
| | | | llvm-svn: 208506
* DwarfUnit: Make explicit a limitation/bug in enumeration constant emission.David Blaikie2014-05-111-4/+9
| | | | | | | | Filed as PR19712, LLVM fails to detect the right type of an enum constant when a frontend does not provide an underlying type for the enumeration type. llvm-svn: 208502
* [PowerPC] On PPC32, 128-bit shifts might be runtime callsHal Finkel2014-05-111-0/+8
| | | | | | | | | | | The counter-loops formation pass needs to know what operations might be function calls (because they can't appear in counter-based loops). On PPC32, 128-bit shifts might be runtime calls (even though you can't use __int128 on PPC32, it seems that SROA might form them). Fixes PR19709. llvm-svn: 208501
* DwarfUnit: Pick a winner between isTypeSigned and isUnsignedDIType.David Blaikie2014-05-112-24/+17
| | | | | | | | | And the winner by a nose is isUnsignedDIType, for no particular reason. These two functions were just complements of each other and used in very related code, so refactor callers to just use one of them. llvm-svn: 208500
* DwarfUnit: Factor out calling isUnsignedDIType into a utility function so ↵David Blaikie2014-05-112-9/+12
| | | | | | each caller of emitConstantValue doesn't have to call it separately. llvm-svn: 208496
* DwarfUnit: Share common constant value emission between APInts of small (<= ↵David Blaikie2014-05-112-40/+17
| | | | | | | | | | | | 64 bit) and MCOperand immediates. Doesn't seem a good reason to duplicate this code (it was more literally duplicated prior to r208494, and while the dataN code /does/ actually fire in this case, it doesn't seem necessary (and the DWARF standard recommends using udata/sdata pervasively instead of dataN, so as to indicate signedness of the values)) llvm-svn: 208495
* DebugInfo: Simplify constant value emission.David Blaikie2014-05-111-41/+11
| | | | | | | | | | | | | This code looks to have become dead at some time in the past. I tried to reproduce cases where LLVM would emit constants with dataN, but could not. Upon inspection it seems the code doesn't do that anymore - the only time a size is provided by isTypeSigned is when the type is signed, and in those cases we use sdata. dataN is only used for unsigned types and isTypeSigned doesn't provide a value for sizeInBits in that case. Remove the dead cases/size plumbing. llvm-svn: 208494
* SLPVectorizer: Instead of just performing CSE on dead blocks ignore them ↵Benjamin Kramer2014-05-111-8/+13
| | | | | | | | | | | | | completely. Turns out that there is a very cheap way of testing whether a block is dead, just look it up in the DomTree. We have to do this anyways so just ignore unreachable blocks before sorting by domination. This restores a proper ordering for std::stable_sort when dead code is present. Covered by existing tests & buildbots running in STL debug mode (MSVC). llvm-svn: 208492
* Reorder shuffle and binary operation.Serge Pavlov2014-05-117-10/+175
| | | | | | | | | | | | | This patch enables transformations: BinOp(shuffle(v1), shuffle(v2)) -> shuffle(BinOp(v1, v2)) BinOp(shuffle(v1), const1) -> shuffle(BinOp, const2) They allow to eliminate extra shuffles in some cases. Differential Revision: http://reviews.llvm.org/D3525 llvm-svn: 208488
* Fixed a bug when lowering build_vector (PR19694)Filipe Cabecinhas2014-05-111-3/+8
| | | | | | | | When lowering build_vector to an insertps, we would still lower it, even if the source vectors weren't v4x32. This would break on avx if the source was a v8x32. We now check the type of the source vectors. llvm-svn: 208487
* R600/SI: Fold fabs/fneg into src input modifierVincent Lejeune2014-05-101-2/+31
| | | | llvm-svn: 208480
* R600/SI: Prettier display of input modifiersVincent Lejeune2014-05-107-38/+77
| | | | llvm-svn: 208479
* R600/SI: Use pseudo instruction for fabs/clamp/fnegVincent Lejeune2014-05-102-4/+74
| | | | llvm-svn: 208478
* SCEV: Use range-based for loop and fold variable into assert.Benjamin Kramer2014-05-101-6/+4
| | | | llvm-svn: 208476
* ARM64: fix SELECT_CC lowering in absence of NaNs.Tim Northover2014-05-101-8/+9
| | | | | | | | | | We were swapping the true & false results while testing for FMAX/FMIN, but not putting them back to the original state if the later checks failed. Should fix PR19700. llvm-svn: 208469
* SLPVectorizer: When sorting by domination for CSE don't assert on ↵Benjamin Kramer2014-05-091-1/+2
| | | | | | | | | | | | unreachable code. There is no total ordering if the CFG is disconnected. We don't care if we catch all CSE opportunities in dead code either so just exclude ignore them in the assert. PR19646 llvm-svn: 208461
* Revert "[ms-cxxabi] Add a new calling convention that swaps 'this' and 'sret'"Reid Kleckner2014-05-096-42/+1
| | | | | | | | | | | | | | This reverts commit r200561. This calling convention was an attempt to match the MSVC C++ ABI for methods that return structures by value. This solution didn't scale, because it would have required splitting every CC available on Windows into two: one for methods and one for free functions. Now that we can put sret on the second arg (r208453), and Clang does that (r208458), revert this hack. llvm-svn: 208459
* move findArrayDimensions to ScalarEvolutionSebastian Pop2014-05-092-10/+10
| | | | | | | we do not use the information from SCEVAddRecExpr to compute the shape of the array, so a better place for this function is in ScalarEvolution. llvm-svn: 208456
* fix typo in debug messageSebastian Pop2014-05-091-2/+2
| | | | llvm-svn: 208455
* Allow sret on the second parameter as well as the firstReid Kleckner2014-05-095-36/+45
| | | | | | | | | | | | | | | | | | | | | | | | | MSVC always places the implicit sret parameter after the implicit this parameter of instance methods. We used to handle this for x86_thiscallcc by allocating the sret parameter on the stack and leaving the this pointer in ecx, but that doesn't handle alternative calling conventions like cdecl, stdcall, fastcall, or the win64 convention. Instead, change the verifier to allow sret on the second parameter. This also requires changing the Mips and X86 backends to return the argument with the sret parameter, instead of assuming that the sret parameter comes first. The Sparc backend also returns sret parameters in a register, but I wasn't able to update it to handle secondary sret parameters. It currently calls report_fatal_error if you feed it an sret in the second parameter. Reviewers: rafael.espindola, majnemer Differential Revision: http://reviews.llvm.org/D3617 llvm-svn: 208453
* Don't crash on redefinitions.Rafael Espindola2014-05-091-5/+7
| | | | | | | | One error we were not deleting the alias or putting it in the Module. The end result is that there was an use left of the aliasee when the module was deleted. llvm-svn: 208447
* Fix broken buildJonathan Roelofs2014-05-091-1/+1
| | | | | | ARM64 backend was missing a required_library entry. llvm-svn: 208437
* Add custom lowering for add/sub with overflow intrinsics to ARMLouis Gerbarg2014-05-092-0/+97
| | | | | | | | | | | | | This patch adds support to ARM for custom lowering of the llvm.{u|s}add.with.overflow.i32 intrinsics for i32/i64. This is particularly useful for handling idiomatic saturating math functions as generated by InstCombineCompare. Test cases included. rdar://14853450 llvm-svn: 208435
* Add ExtractValue instruction to SimplifyCFG's ComputeSpeculationCostLouis Gerbarg2014-05-091-0/+1
| | | | | | | | | | | | | Since ExtractValue is not included in ComputeSpeculationCost CFGs containing ExtractValueInsts cannot be simplified. In particular this interacts with InstCombineCompare's tendency to insert add.with.overflow intrinsics for certain idiomatic math operations, preventing optimization. This patch adds ExtractValue to the ComputeSpeculationCost. Test case included rdar://14853450 llvm-svn: 208434
* R600/SI: Teach SIInstrInfo::moveToVALU() how to move S_LOAD_*_IMM instructionsTom Stellard2014-05-091-4/+35
| | | | llvm-svn: 208432
* R600/SI: Fix SMRD pattern for offsets > 32 bitsTom Stellard2014-05-092-7/+6
| | | | | | We were dropping the high bits of 64-bit immediate offsets. llvm-svn: 208431
* R600: Expand i64 SELECT_CCTom Stellard2014-05-091-0/+2
| | | | llvm-svn: 208430
* R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine()Tom Stellard2014-05-094-23/+19
| | | | llvm-svn: 208429
* Use auto and clang-format this snippet.Rafael Espindola2014-05-091-3/+5
| | | | llvm-svn: 208421
* Run clang-format in small sections of code to make a patch easier to read.Rafael Espindola2014-05-092-22/+18
| | | | llvm-svn: 208419
* Delete trailing whitespace.Rafael Espindola2014-05-091-98/+98
| | | | llvm-svn: 208416
* Delete trailing white space.Rafael Espindola2014-05-091-4/+4
| | | | llvm-svn: 208415
* [mips] Marked up instructions added in MIPS-IV and tested that IAS for ↵Daniel Sanders2014-05-095-24/+41
| | | | | | | | | | | | | | | | | | | | | -mcpu=mips[123] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-IV that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. Depends on D3676 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3677 llvm-svn: 208414
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