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* [InstCombine] rearrange code for foldSelectBinOpIdentity; NFCISanjay Patel2018-08-101-21/+25
| | | | | | | This should make it easier to folow and to add the planned enhancements such as D50190. llvm-svn: 339439
* [MS Demangler] Properly demangle conversion operators.Zachary Turner2018-08-101-20/+44
| | | | | | | These were completely broken before. We need to handle the 'B' operator tag. llvm-svn: 339436
* [MS Demangler] Fix several issues related to templates.Zachary Turner2018-08-101-34/+90
| | | | | | | | | | | | These were uncovered when porting the mangling tests in ms-templates.cpp from clang/CodeGenCXX over to demangling tests. The main issues fixed here are surrounding integer literal signed and unsignedness, empty array dimensions, and pointer and reference non-type template parameters. Differential Revision: https://reviews.llvm.org/D50512 llvm-svn: 339434
* [ARM] Disallow zexts in ARMCodeGenPrepareSam Parker2018-08-101-165/+109
| | | | | | | | | | | | | | | | | | | Enabling ARMCodeGenPrepare by default caused a whole load of failures. This is due to zexts and truncs not being handled properly. ZExts are messy so it's just easier to disable for now and truncs are allowed only as 'sinks'. I still need to figure out why allowing them as 'sources' causes so many failures. The other main changes are that we are explicit in the types that we converting to, it's now always 'TypeSize'. Type support is also now performed while checking for valid opcodes as it unnecessarily complicated having the checks are different stages. I've moved the tests around too, so we have the zext and truncs in their own file as well as the overflowing opcode tests. Differential Revision: https://reviews.llvm.org/D50518 llvm-svn: 339432
* [X86][SSE] Pull out repeated shift getOpcode() calls. NFCI.Simon Pilgrim2018-08-101-23/+23
| | | | llvm-svn: 339425
* Fix -Wimplicit-fallthrough warning introduced in rL339397.Simon Pilgrim2018-08-101-0/+1
| | | | llvm-svn: 339422
* Rename the cfguard module flag to cfguardtableHans Wennborg2018-08-101-1/+1
| | | | | | | | | | The previous name sounds like it inserts cfguard implementation, but it really just emits the table of address-taken functions. Change the name to better reflect that. Clang will be updated in the next commit. llvm-svn: 339419
* [MSan] Shrink the register save area for non-SSE buildsAlexander Potapenko2018-08-101-2/+16
| | | | | | | | If code is compiled for X86 without SSE support, the register save area doesn't contain FPU registers, so `AMD64FpEndOffset` should be equal to `AMD64GpEndOffset`. llvm-svn: 339414
* [MemorySSA] "Fix" lifetime intrinsic handlingGeorge Burgess IV2018-08-101-2/+7
| | | | | | | | | | | | | | | | | | | MemorySSA currently creates MemoryAccesses for lifetime intrinsics, and sometimes treats them as clobbers. This may/may not be the best way forward, but while we're doing it, we should consider MayAlias/PartialAlias to be clobbers. The ideal fix here is probably to remove all of this reasoning about lifetimes from MemorySSA + put it into the passes that need to care. But that's a wayyy broader fix that needs some consensus, and we have miscompiles + a release branch today, and this should solve the miscompiles just as well. differential revision is D43269. Landing without an explicit LGTM (and without using the special please-autoclose-this syntax) so we can still use that revision as a place to decide what the right fix here is. llvm-svn: 339411
* [InstCombine] Transform str(n)cmp to memcmpDavid Bolvansky2018-08-101-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Motivation examples: int strcmp_memcmp() { char buf[12]; return strcmp(buf, "key") == 0; } int strcmp_memcmp2() { char buf[12]; return strcmp(buf, "key") != 0; } int strncmp_memcmp() { char buf[12]; return strncmp(buf, "key", 3) == 0; } can be turned to memcmp. See test file for more cases. Reviewers: efriedma Reviewed By: efriedma Subscribers: spatel, llvm-commits Differential Revision: https://reviews.llvm.org/D50233 llvm-svn: 339410
* [WebAssembly] Gate i64x2 and f64x2 on -wasm-enable-unimplementedHeejin Ahn2018-08-091-2/+10
| | | | | | | | | | | | | | | | | | Summary: i64x2 and f64x2 operations are not implemented in V8, so we normally do not want to emit them. However, they are in the SIMD spec proposal, so we still want to be able to test them in the toolchain. This patch adds a flag to enable their emission. Reviewers: aheejin, dschuff Subscribers: sunfish, jgravelle-google, sbc100, llvm-commits Differential Revision: https://reviews.llvm.org/D50423 Patch by Thomas Lively (tlively) llvm-svn: 339407
* [X86] Qualify one of the heuristics in combineMul to only apply to positive ↵Craig Topper2018-08-091-2/+4
| | | | | | | | multiply amounts. This seems to slightly help the performance of one of our internal benchmarks. We probably need better heuristics here. llvm-svn: 339406
* ValueTracking: Start enhancing isKnownNeverNaNMatt Arsenault2018-08-093-14/+34
| | | | llvm-svn: 339399
* [WebAssembly] Fix wasm backend compilation on gcc 5.4: variable name cannot ↵Heejin Ahn2018-08-091-5/+5
| | | | | | | | | | | | | | | | | | | | | | | match class Summary: gcc does not like const Region *Region; It wants a different name for the variable. Is there a better convention for what name to use in such a case? Reviewers: sbc100, aheejin Subscribers: aheejin, jgravelle-google, dschuff, llvm-commits Differential Revision: https://reviews.llvm.org/D50472 Patch by Alon Zakai (kripken) llvm-svn: 339398
* [MC] Move EH DWARF encodings from MC to CodeGen, NFCReid Kleckner2018-08-093-157/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The TType encoding, LSDA encoding, and personality encoding are all passed explicitly by CodeGen to the assembler through .cfi_* directives, so only the AsmPrinter needs to know about them. The FDE CFI encoding however, controls the encoding of the label implicitly created by the .cfi_startproc directive. That directive seems to be special in that it doesn't take an encoding, so the assembler just has to know how to encode one DSO-local label reference from .eh_frame to .text. As a result, it looks like MC will continue to have to know when the large code model is in use. Perhaps we could invent a '.cfi_startproc [large]' flag so that this knowledge doesn't need to pollute the assembler. Reviewers: davide, lliu0, JDevlieghere Subscribers: hiraditya, fedor.sergeev, llvm-commits Differential Revision: https://reviews.llvm.org/D50533 llvm-svn: 339397
* [InstSimplify] move minnum/maxnum with Inf folds from instcombineSanjay Patel2018-08-092-36/+16
| | | | llvm-svn: 339396
* [NFC] ConstantMerge: factor out some functionsJF Bastien2018-08-091-25/+42
| | | | | | This makes the code easier to read and will make an upcoming patch I have easier to review because that patch needed this refactoring to reuse some of the functions. llvm-svn: 339391
* ConstantMerge: update MadeChange when change is madeJF Bastien2018-08-091-0/+1
| | | | | | It was always false, which is obviously wrong. llvm-svn: 339390
* [LICM] Suppress a compiler warning noticed by one of the botsPhilip Reames2018-08-091-0/+1
| | | | llvm-svn: 339388
* [RISC-V] Fixed alias for addi x2, x2, 0Ana Pazos2018-08-091-1/+1
| | | | | | | | A missing check for non-zero immediate in MCOperandPredicate caused c.addi16sp sp, 0 to be selected which is not a valid instruction. llvm-svn: 339381
* [LICM] hoist fences out of loops w/o memory operationsPhilip Reames2018-08-091-0/+15
| | | | | | | | | | The motivating case is an otherwise dead loop with a fence in it. At the moment, this goes all the way through the optimizer and we end up emitting an entirely pointless loop on x86. This case may seem a bit contrived, but we've seen it in real code as the result of otherwise reasonable lowering strategies combined w/thread local memory optimizations (such as escape analysis). To handle this simple case, we can teach LICM to hoist must execute fences when there is no other memory operation within the loop. Differential Revision: https://reviews.llvm.org/D50489 llvm-svn: 339378
* [InstCombine] allow fsub+fmul FMF folds for vectorsSanjay Patel2018-08-091-0/+11
| | | | llvm-svn: 339368
* [NFC] Remove magic bool param in RAUWJF Bastien2018-08-091-4/+4
| | | | | | Use an enum class instead. llvm-svn: 339366
* [Hexagon] Map ISD::TRAP to J2_trap0(#0)Krzysztof Parzyszek2018-08-093-15/+20
| | | | llvm-svn: 339365
* SCEV should forget all loops containing a deleted block.Alina Sbirlea2018-08-091-1/+2
| | | | | | | | | | | | | | Summary: LoopSimplifyCFG should update ScEv for all loops after a block is deleted. If the deleted block "Succ" is part of L, then it is part of all parent loops, so forget topmost loop. Reviewers: greened, mkazantsev, sanjoy Subscribers: jlebar, javed.absar, uabelho, llvm-commits Differential Revision: https://reviews.llvm.org/D50422 llvm-svn: 339363
* [GlobalOpt] Don't apply fastcc if it would break inalloca invariantsReid Kleckner2018-08-091-0/+7
| | | | | | | | | | | | | | The inalloca parameter has to be the only parameter passed in memory. Changing the convention to fastcc can break that. At some point we should teach global opt how to optimize ABI attributes like inalloca and maybe byval. These attributes are mainly used to match C ABIs. They are harder for LLVM to optimize and they don't always generate the best code. Fixes PR38487 llvm-svn: 339360
* [SelectionDAG] try harder to convert funnel shift to rotateSanjay Patel2018-08-091-3/+10
| | | | | | | | | | | | Similar to rL337966 - if the DAGCombiner's rotate matching was working as expected, I don't think we'd see any test diffs here. AArch only goes right, and PPC only goes left. x86 has both, so no diffs there. Differential Revision: https://reviews.llvm.org/D50091 llvm-svn: 339359
* extend folding fsub/fadd to fneg for FMFMichael Berg2018-08-091-8/+10
| | | | | | | | | | | | | | Summary: This change provides a common optimization path for both Unsafe and FMF driven optimization for this fsub fold adding reassociation, as it the flag that most closely represents the translation Reviewers: spatel, wristow, arsenm Reviewed By: spatel Subscribers: wdng Differential Revision: https://reviews.llvm.org/D50195 llvm-svn: 339357
* [ARM] Adjust the feature set for ExynosEvandro Menezes2018-08-091-0/+36
| | | | | | | | | Enable `FeatureZCZeroing`, `FeatureHasSlowFPVMLx`, `FeatureExpandMLx`, `FeatureProfUnpredicate`, `FeatureSlowVDUP32`, `FeatureSlowVGETLNi32`, `FeatureSplatVFPToNeon`, `FeatureHasRetAddrStack`, `FeatureSlowFPBrcc` for all Exynos processors. llvm-svn: 339356
* [ARM] Replace processor check with featureEvandro Menezes2018-08-093-1/+15
| | | | | | | Add new feature, `FeatureUseWideStrideVFP`, that replaces the need for a processor check. Otherwise, NFC. llvm-svn: 339354
* [MC][PredicateExpander] Extend the grammar to support simple switch and ↵Andrea Di Biagio2018-08-091-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | return statements. This patch introduces tablegen class MCStatement. Currently, an MCStatement can be either a return statement, or a switch statement. ``` MCStatement: MCReturnStatement MCOpcodeSwitchStatement ``` A MCReturnStatement expands to a return statement, and the boolean expression associated with the return statement is described by a MCInstPredicate. An MCOpcodeSwitchStatement is a switch statement where the condition is a check on the machine opcode. It allows the definition of multiple checks, as well as a default case. More details on the grammar implemented by these two new constructs can be found in the diff for TargetInstrPredicates.td. This patch makes it easier to read the body of auto-generated TargetInstrInfo predicates. In future, I plan to reuse/extend the MCStatement grammar to describe more complex target hooks. For now, this is just a first step (mostly a minor cosmetic change to polish the new predicates framework). Differential Revision: https://reviews.llvm.org/D50457 llvm-svn: 339352
* [MC] Remove PhysRegSize from MCRegisterClassBjorn Pettersson2018-08-091-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: The interface to get size and spill size of a register was moved from MCRegisterInfo to TargetRegisterInfo over a year ago. Afaik the old interface has bee around to give out-of-tree targets a chance to adapt to the new interface. One problem with the old MCRegisterClass::PhysRegSize was that it represented the size of a register as "size in bits" / 8. So a register had to be a multiple of eight bits wide for the size to be correct (and the byte size for the target needed to be eight bits). Reviewers: kparzysz, qcolombet Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47199 llvm-svn: 339350
* [InstCombine] reduce code duplication; NFCSanjay Patel2018-08-091-9/+7
| | | | llvm-svn: 339349
* [TargetLowering] Add BuildSDIVPattern helper to BuildExactSDIV (NFCI).Simon Pilgrim2018-08-091-14/+23
| | | | | | As requested in D50392, pull the magic constant calculations out into a helper function. llvm-svn: 339346
* [ARM] FP16: codegen support for VTRNSjoerd Meijer2018-08-091-0/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D50454 llvm-svn: 339340
* [X86][SSE] Remove PMULDQ/PMULUDQ by zeroSimon Pilgrim2018-08-091-0/+9
| | | | | | | | Exposed by D50328 Differential Revision: https://reviews.llvm.org/D50328 llvm-svn: 339337
* [X86][SSE] Combine (some) target shuffles with multiple usesSimon Pilgrim2018-08-091-20/+29
| | | | | | | | | | | | | | As discussed on D41794, we have many cases where we fail to combine shuffles as the input operands have other uses. This patch permits these shuffles to be combined as long as they don't introduce additional variable shuffle masks, which should reduce instruction dependencies and allow the total number of shuffles to still drop without increasing the constant pool. However, this may mean that some memory folds may no longer occur, and on pre-AVX require the occasional extra register move. This also exposes some poor PMULDQ/PMULUDQ codegen which was doing unnecessary upper/lower calculations which will in fact fold to zero/undef - the fix will be added in a followup commit. Differential Revision: https://reviews.llvm.org/D50328 llvm-svn: 339335
* [X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions.Andrew V. Tischenko2018-08-0911-57/+14
| | | | | | Differential Revision: https://reviews.llvm.org/D49861 llvm-svn: 339321
* [NVPTX] Select atomic loads and storesJonas Hahnfeld2018-08-091-34/+82
| | | | | | | | | | | | | | | | | | | According to PTX ISA .volatile has the same memory synchronization semantics as .relaxed.sys, so it can be used to implement monotonic atomic loads and stores. This is important for OpenMP's atomic construct where - 'read's and 'write's are lowered to atomic loads and stores, and - an update of float or double types are lowered into a cmpxchg loop. (Note that PTX could do better because it has atom.add.f{32,64} but LLVM's atomicrmw instruction only allows integer types.) Higher levels of atomicity (like acquire and release) need additional synchronization properties which were added with PTX ISA 6.0 / sm_70. So using these instructions still results in an error. Differential Revision: https://reviews.llvm.org/D50391 llvm-svn: 339316
* [RISCV] Add "lla" pseudo-instruction to assemblerRoger Ferrer Ibanez2018-08-092-3/+69
| | | | | | | | | | | | | | | | | | | | | | | | This pseudo-instruction is similar to la but uses PC-relative addressing unconditionally. This is, la is only different to lla when using -fPIC. This pseudo-instruction seems often forgotten in several specs but it is definitely mentioned in binutils opcodes/riscv-opc.c. The semantics are defined both in page 37 of the "RISC-V Reader" book but also in function macro found in gas/config/tc-riscv.c. This is a very first step towards adding PIC support for Linux in the RISC-V backend. The lla pseudo-instruction expands to a sequence of auipc + addi with a couple of pc-rel relocations where the second points to the first one. This is described in https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses For now, this patch only introduces support of that pseudo instruction at the assembler parser. Differential Revision: https://reviews.llvm.org/D49661 llvm-svn: 339314
* [NFC] ConstantMerge: don't insert when find should be usedJF Bastien2018-08-091-2/+5
| | | | | | | | | | Summary: DenseMap's operator[] performs an insertion if the entry isn't found. The second phase of ConstantMerge isn't trying to insert anything: it's just looking to see if the first phased performed an insertion. Use find instead, avoiding insertion of every single global initializer in the map of constants. This has the side-effect of making all entries in CMap non-null (because only global declarations would have null initializers, and that would be a bug). Subscribers: dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D50476 llvm-svn: 339309
* [LICM] Add an assert to ensure all instruction types needing aliasing are ↵Philip Reames2018-08-091-0/+2
| | | | | | handled [NFC] llvm-svn: 339308
* [DWARF] Verifier now handles .debug_types sections.Paul Robinson2018-08-081-23/+35
| | | | | | Differential Revision: https://reviews.llvm.org/D50466 llvm-svn: 339302
* [DAGCombiner] loosen constraints for fsub+fadd foldSanjay Patel2018-08-081-14/+7
| | | | | | | | | isNegatibleForFree() should not matter here (as the test diffs show) because it's always a win to replace an fsub+fadd with fneg. The problem in D50195 persists because either (1) we are doing these folds in the wrong order or (2) we're missing another fold for fadd. llvm-svn: 339299
* [DAGCombiner] move fadd simplification ahead of other foldsSanjay Patel2018-08-081-9/+6
| | | | | | | | | I don't know if it's possible to expose this diff in a test, but we should always try simplifications (no new nodes created) before more complicated transforms for efficiency (similar to what we do in IR). llvm-svn: 339298
* [ADT] Normalize empty triple componentsPetr Hosek2018-08-081-0/+6
| | | | | | | | | | | | | | | | | LLVM triple normalization is handling "unknown" and empty components differently; for example given "x86_64-unknown-linux-gnu" and "x86_64-linux-gnu" which should be equivalent, triple normalization returns "x86_64-unknown-linux-gnu" and "x86_64--linux-gnu". autoconf's config.sub returns "x86_64-unknown-linux-gnu" for both "x86_64-linux-gnu" and "x86_64-unknown-linux-gnu". This changes the triple normalization to behave the same way, replacing empty triple components with "unknown". This addresses PR37129. Differential Revision: https://reviews.llvm.org/D50219 llvm-svn: 339294
* [DWARF] Unclamp line table version on Darwin for v5 and later.Jonas Devlieghere2018-08-081-3/+6
| | | | | | | | | On Darwin we pin the DWARF line tables to version 2. Stop doing so for DWARF v5 and later. Differential revision: https://reviews.llvm.org/D49381 llvm-svn: 339288
* [ARM] Avoid spilling lr with Thumb1 tail calls.Eli Friedman2018-08-081-2/+7
| | | | | | | | | | | | | | | Normally, if any registers are spilled, we prefer to spill lr on Thumb1 so we can fold the "bx lr" into the "pop". However, if there are tail calls involved, restoring lr is expensive, so skip the optimization in that case. The spill of r7 in the new test also isn't necessary, but that's mostly orthogonal to this patch. (It's the same code in ARMFrameLowering, but it's not related to tail calls.) Differential Revision: https://reviews.llvm.org/D49459 llvm-svn: 339283
* [MS Demangler] Create a new backref context for template instantiations.Zachary Turner2018-08-081-29/+39
| | | | | | | | Template manglings use a fresh back-referencing context, so we need to do the same. This fixes several existing tests which are marked as FIXME, so those are now actually run. llvm-svn: 339275
* revert '[CodeGen] emit inline asm clobber list warnings for reserved'Ties Stuij2018-08-081-78/+32
| | | | llvm-svn: 339274
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