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* Use branches instead of jumps + variable cleanup. Testcase coming next. ↵Bruno Cardoso Lopes2011-12-063-41/+39
| | | | | | Patch by Jack Carter llvm-svn: 145912
* Explicit symbols for gnu mimicing relocations. Patch by Jack CarterBruno Cardoso Lopes2011-12-062-0/+20
| | | | llvm-svn: 145911
* Add register HWR29 numbering. Patch by Jack CarterBruno Cardoso Lopes2011-12-062-0/+2
| | | | llvm-svn: 145910
* LSR: prune undesirable formulae early.Andrew Trick2011-12-061-46/+85
| | | | | | | | | It's always good to prune early, but formulae that are unsatisfactory in their own right need to be removed before running any other pruning heuristics. We easily avoid generating such formulae, but we need them as an intermediate basis for forming other good formulae. llvm-svn: 145906
* Mix some minor misuse of MachineBasicBlock iterator.Evan Cheng2011-12-061-3/+3
| | | | llvm-svn: 145903
* Removed isWinToJoinCrossClass from the register coalescer.Pete Cooper2011-12-061-66/+0
| | | | | | | | The new register allocator is much more able to split back up ranges too constrained by register classes. Fixes <rdar://problem/10466609> llvm-svn: 145899
* Kill off the LoopSplitter. It's not being used or maintained.Lang Hames2011-12-065-941/+0
| | | | llvm-svn: 145897
* Add a comment.Bill Wendling2011-12-061-0/+3
| | | | llvm-svn: 145896
* Tidy up value checking.Jim Grosbach2011-12-061-1/+2
| | | | llvm-svn: 145895
* MipsAsmBackend.cpp, PPCAsmBackend.cpp: Fix -Asserts build to appease msvc.NAKAMURA Takumi2011-12-062-0/+2
| | | | llvm-svn: 145894
* Update PBQP's analysis usage to reflect the requirements of the inline spiller.Lang Hames2011-12-061-0/+7
| | | | llvm-svn: 145893
* [arm-fast-isel] Doublewords only require word-alignment.Chad Rosier2011-12-061-3/+4
| | | | | | rdar://10528060 llvm-svn: 145891
* Align ARM constant pool islands via their basic block.Jakob Stoklund Olesen2011-12-062-2/+7
| | | | | | | | | | | Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired alignment of 4 bytes emitted by ARMAsmPrinter. Now the same alignment is set on the basic block. This is in preparation of supporting ARM constant pool islands with different alignments. llvm-svn: 145890
* Use logarithmic units for basic block alignment.Jakob Stoklund Olesen2011-12-062-3/+3
| | | | | | | | | | | | | | | | | This was actually a bit of a mess. TLI.setPrefLoopAlignment was clearly documented as taking log2(bytes) units, but the x86 target would still set a preferred loop alignment of '16'. CodePlacementOpt passed this number on to the basic block, and AsmPrinter interpreted it as bytes. Now both MachineFunction and MachineBasicBlock use logarithmic alignments. Obviously, MachineConstantPool still measures alignments in bytes, so we can emulate the thrill of using as. llvm-svn: 145889
* The compact encoding of the registers are 3-bits each. Make sure we shift theBill Wendling2011-12-061-2/+4
| | | | | | value over that much. llvm-svn: 145888
* Fix ARM handling of tBcc branch relaxation.Jim Grosbach2011-12-061-3/+5
| | | | | | rdar://10069056 llvm-svn: 145885
* Use an existing function.Jakob Stoklund Olesen2011-12-061-10/+1
| | | | llvm-svn: 145883
* Move target-specific logic out of generic MCAssembler.Jim Grosbach2011-12-066-5/+67
| | | | | | | | Whether a fixup needs relaxation for the associated instruction is a target-specific function, as the FIXME indicated. Create a hook for that and use it. llvm-svn: 145881
* Expose a switch for the new gcov format.Nick Lewycky2011-12-061-2/+3
| | | | llvm-svn: 145880
* Probably not a good idea to convert a single vector load into a memcpy. WeChad Rosier2011-12-061-0/+2
| | | | | | | | don't do this now, but add a test case to prevent this from happening in the future. Additional test for rdar://9892684 llvm-svn: 145879
* Tidy up. Hard tabs.Jim Grosbach2011-12-063-3/+3
| | | | llvm-svn: 145878
* Switch MCAssembler to method names starting w/ lower-case.Jim Grosbach2011-12-064-34/+34
| | | | | | per http://llvm.org/docs/CodingStandards.html#ll_naming llvm-svn: 145873
* Simple branch relaxation for Thumb2 Bcc instructions.Jim Grosbach2011-12-051-3/+24
| | | | | | | Not right yet, as the rules for when to relax in the MCAssembler aren't (yet) correct for ARM. This is a step in the proper direction, though. llvm-svn: 145871
* Silence tsan false-positives (tsan can't track things which are only safe due toNick Lewycky2011-12-051-0/+3
| | | | | | | memory fences) in statistics registration, which works the same way that ManagedStatic registration does. llvm-svn: 145869
* Update comment.Chad Rosier2011-12-051-1/+1
| | | | llvm-svn: 145866
* Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerioChad Rosier2011-12-051-1/+1
| | | | | | | | where this would be bad as the backend shouldn't have a problem inlining small memcpys. rdar://10510150 llvm-svn: 145865
* Tweak ADDrr fix. Bad check for explicit .wJim Grosbach2011-12-051-2/+2
| | | | llvm-svn: 145863
* Thumb2 prefer ADD register encoding T2 to T3 when possible.Jim Grosbach2011-12-051-0/+20
| | | | | | rdar://10529664 llvm-svn: 145860
* Add definitions of 64-bit extract and insert instrucions and makeAkira Hatanaka2011-12-052-12/+17
| | | | | | | PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
* Split ExtIns into two base classes and have instructions EXT and INS derive fromAkira Hatanaka2011-12-051-17/+21
| | | | | | them. llvm-svn: 145852
* Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.Jim Grosbach2011-12-051-0/+18
| | | | | | rdar://10529348 llvm-svn: 145851
* Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 andAkira Hatanaka2011-12-051-20/+16
| | | | | | O32 with relocation-model=pic too. llvm-svn: 145850
* ARM assembly parsing for the rest of the VMUL data type aliases.Jim Grosbach2011-12-052-10/+74
| | | | | | Finish up rdar://10522016. llvm-svn: 145846
* Fix previous commit. Oops.Jim Grosbach2011-12-051-3/+3
| | | | llvm-svn: 145844
* Tidy up. No functional change.Jim Grosbach2011-12-051-9/+6
| | | | llvm-svn: 145843
* ARM assmebler parsing for two-operand VMUL instructions.Jim Grosbach2011-12-052-0/+11
| | | | | | | | | Combined destination and first source operand for f32 variant of the VMUL (by scalar) instruction. rdar://10522016 llvm-svn: 145842
* enable PPC register scavenging by default (update tests and remove some FIXMEs)Hal Finkel2011-12-053-17/+13
| | | | llvm-svn: 145819
* don't include CR bit subregs in callee-saved listHal Finkel2011-12-051-16/+0
| | | | llvm-svn: 145818
* add register pressure for CR regsHal Finkel2011-12-051-0/+2
| | | | llvm-svn: 145816
* Add a little heuristic to Value::isUsedInBasicBlock to speed it up for small ↵Benjamin Kramer2011-12-052-8/+14
| | | | | | | | | | basic blocks. - Calling getUser in a loop is much more expensive than iterating over a few instructions. - Use it instead of the open-coded loop in AddrModeMatcher. - 5% speedup on ARMDisassembler.cpp Release builds. llvm-svn: 145810
* Remove some leftover remnants that once tried to create 64-bit MMX PALIGNR ↵Craig Topper2011-12-051-2/+2
| | | | | | instructions. llvm-svn: 145804
* Clean up and optimizations to the X86 shuffle lowering code. No functional ↵Craig Topper2011-12-051-52/+36
| | | | | | change. llvm-svn: 145803
* Add support for vectors of pointers.Nadav Rotem2011-12-0513-39/+168
| | | | llvm-svn: 145801
* Add inline subprogram names to the name lookup table since they mayEric Christopher2011-12-041-0/+4
| | | | | | not get there any other way. llvm-svn: 145789
* Fix 80-column issues.Bob Wilson2011-12-041-4/+8
| | | | llvm-svn: 145783
* Emit the ctors in the proper order on ARM/EABI.Anton Korobeynikov2011-12-035-3/+8
| | | | | | | | Maybe some targets should use this as well. Patch by Evgeniy Stepanov! llvm-svn: 145781
* Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() sinceVenkatraman Govindaraju2011-12-031-1/+1
| | | | | | AnalyzeBranch doesn't change the successor, just the order. llvm-svn: 145779
* Simplify code. No functionality change.Benjamin Kramer2011-12-031-2/+1
| | | | | | -3% on ARMDissasembler.cpp. llvm-svn: 145773
* Clear the new cache.Benjamin Kramer2011-12-031-0/+1
| | | | llvm-svn: 145771
* Add a "seen blocks" cache to LVI to avoid a linear scan over the whole cache ↵Benjamin Kramer2011-12-031-1/+13
| | | | | | | | | just to remove no blocks from the maps. -15% on ARMDisassembler.cpp (Release build). It's not that great to add another layer of caching to the caching-heavy LVI but I don't see a better way. llvm-svn: 145770
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