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* indvars: cleanup the IV visitor. It does more than gather sext/zext info.Andrew Trick2014-01-021-25/+33
| | | | llvm-svn: 198353
* Fix up a couple of review comments:Eric Christopher2014-01-022-9/+9
| | | | | | | | Use an if statement instead of a pair of ternary operators checking the same condition. Use a cheap method call rather than returning the local symbol. llvm-svn: 198351
* Simplify conditional.Eric Christopher2014-01-021-1/+1
| | | | llvm-svn: 198350
* Allow addrspacecast in global aliasesMatt Arsenault2014-01-022-2/+5
| | | | llvm-svn: 198349
* [TableGen] Correctly generate implicit anonymous prototype defs in multiclassesHal Finkel2014-01-021-5/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | Even within a multiclass, we had been generating concrete implicit anonymous defs when parsing values (generally in value lists). This behavior was incorrect, and led to errors when multiclass parameters were used in the parameter list of the implicit anonymous def. If we had some multiclass: multiclass mc<string n> { ... : SomeClass<SomeOtherClass<n> > The capture of the multiclass parameter 'n' would not work correctly, and depending on how the implicit SomeOtherClass was used, either TableGen would ignore something it shouldn't, or would crash. To fix this problem, when inside a multiclass, we generate prototype anonymous defs for implicit anonymous defs (just as we do for explicit anonymous defs). Within the multiclass, the current record prototype is populated with a node that is essentially: !cast<SomeOtherClass>(!strconcat(NAME, anon_value_name)). This is then resolved to the correct concrete anonymous def, in the usual way, when NAME is resolved during multiclass instantiation. llvm-svn: 198348
* Delete unread globals through addrspacecastMatt Arsenault2014-01-021-2/+3
| | | | llvm-svn: 198346
* Fix addrspacecast with metadata globalsMatt Arsenault2014-01-021-3/+5
| | | | llvm-svn: 198345
* Remove redundant fold call introduced in r195944. Thanks very much to JuergenLang Hames2014-01-021-2/+1
| | | | | | | for pointing this out. llvm-svn: 198341
* [TableGen] Use the same anonymous name as the prefix on all multiclass defsHal Finkel2014-01-022-2/+2
| | | | | | | | | | | | | | | | TableGen had been generating a different name for an anonymous multiclass's NAME for every def in the multiclass. This had an unfortunate side effect: it was impossible to reference one def within the multiclass from another (in the parameter list, for example). By making sure we only generate an anonymous name once per multiclass (which, as it turns out, requires only changing the name parameter to reference type), we can now concatenate NAME within the multiclass with a def name in order to generate a reference to that def. This does not matter so much, in and of itself, but is necessary for a follow-up commit that will fix variable capturing in implicit anonymous multiclass defs (and that is important). llvm-svn: 198340
* indvars: insert truncate at loop boundary to avoid redundant IVs.Andrew Trick2014-01-021-5/+12
| | | | | | | | | When widening an IV to remove s/zext, we generally try to eliminate the original narrow IV. However, LCSSA phi nodes outside the loop were still using the original IV. Clean this up more aggressively to avoid redundancy in generated code. llvm-svn: 198338
* Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr.Craig Topper2014-01-021-1/+2
| | | | llvm-svn: 198336
* Make llvm::Regex non-copyable but movable.David Blaikie2014-01-021-2/+4
| | | | | | Based on a patch by Maciej Piechotka. llvm-svn: 198334
* Revert "Debug info: Add enumerators to the __apple_names accelerator table."Adrian Prantl2014-01-021-3/+0
| | | | | | | This reverts r197927 until the discussion on llvm-commits comes to a conclusion. llvm-svn: 198333
* Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack ↵Craig Topper2014-01-021-4/+4
| | | | | | from the disassembler table builder. llvm-svn: 198327
* Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler ↵Craig Topper2014-01-023-145/+196
| | | | | | table builder doesn't need to string match them to exclude them. llvm-svn: 198323
* [arm] Add softvfp to supported FPU names.Logan Chien2014-01-022-0/+4
| | | | llvm-svn: 198313
* Make the ARM ABI selectable via SubtargetFeature.Rafael Espindola2014-01-023-14/+33
| | | | | | | This patch makes it possible to select the ABI with -mattr. It will be used to forward clang's -target-abi option to llvm's CodeGen. llvm-svn: 198304
* BasicAA: Fix value equality and phi cyclesArnold Schwaighofer2014-01-021-37/+112
| | | | | | | | | | | | | | | | | | | | | | | | | When there are cycles in the value graph we have to be careful interpreting "Value*" identity as "value" equivalence. We interpret the value of a phi node as the value of its operands. When we check for value equivalence now we make sure that the "Value*" dominates all cycles (phis). %0 = phi [%noaliasval, %addr2] %l = load %ptr %addr1 = gep @a, 0, %l %addr2 = gep @a, 0, (%l + 1) store %ptr ... Before this patch we would return NoAlias for (%0, %addr1) which is wrong because the value of the load is from different iterations of the loop. Tested on x86_64 -mavx at O3 and O3 -flto with no performance or compile time regressions. PR18068 radar://15653794 llvm-svn: 198290
* Remove the 's' DataLayout specificationRafael Espindola2014-01-017-18/+16
| | | | | | | | | | | | | | | | | | | | | | | During the years there have been some attempts at figuring out how to align byval arguments. A look at the commit log suggests that they were * Use the ABI alignment. * When that was not sufficient for x86-64, I added the 's' specification to DataLayout. * When that was not sufficient Evan added the virtual getByValTypeAlignment. * When even that was not sufficient, we just got the FE to add the alignment to the byval. This patch is just a simple cleanup that removes my first attempt at fixing the problem. I also added an AArch64 implementation of getByValTypeAlignment to make sure this patch is a nop. I also left the 's' parsing for backward compatibility. I will send a short email to llvmdev about the change for anyone maintaining an out of tree target. llvm-svn: 198287
* [Sparc] Handle atomic loads/stores in sparc backend.Venkatraman Govindaraju2014-01-013-3/+101
| | | | llvm-svn: 198286
* Remove modifierType/Base from X86 disassembler tables as they are no longer ↵Craig Topper2014-01-011-3/+0
| | | | | | used. Removes ~11.5K from static tables. llvm-svn: 198284
* [SparcV9]: Custom lower UMULO/SMULO so that the arguments are send to ↵Venkatraman Govindaraju2014-01-011-0/+52
| | | | | | __multi3() in correct order. llvm-svn: 198281
* [SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL ↵Venkatraman Govindaraju2014-01-011-2/+2
| | | | | | does not clear top 32 bit, only SRL does. llvm-svn: 198280
* X86Disassembler.cpp: Prune stray @return on translateFPRegister(). ↵NAKAMURA Takumi2014-01-011-1/+0
| | | | | | [-Wdocumentation] llvm-svn: 198279
* Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are ↵Craig Topper2014-01-014-52/+10
| | | | | | really more like OrRegFrm so we don't need a difference since we can just mask bits. llvm-svn: 198278
* AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmpElena Demikhovsky2014-01-018-63/+273
| | | | | | | Printing rounding control. Enncoding for EVEX_RC (rounding control). llvm-svn: 198277
* Second attempt at Removing special form of AddRegFrm used by FP ↵Craig Topper2014-01-014-83/+68
| | | | | | instructions. These instructions can be handled by MRMXr instead. llvm-svn: 198276
* Fold vector selects with undef elements in the condition. Fixes PR18319.Nick Lewycky2013-12-311-6/+15
| | | | | | Patch by Ilia Filippov! llvm-svn: 198267
* Revert r198238 and add FP disassembler tests. It didn't work and I didn't ↵Craig Topper2013-12-313-63/+76
| | | | | | realized we had no FP disassembler test cases. llvm-svn: 198265
* Remove old comment referring to an argument that no longer exists.Craig Topper2013-12-311-2/+0
| | | | llvm-svn: 198263
* Fix misaligned indentation in "if" block in MipsMCCodeEmitter.cppMark Seaborn2013-12-311-92/+92
| | | | llvm-svn: 198262
* Add missing MRM_XX forms to the old JIT emitter for consistency.Craig Topper2013-12-311-26/+39
| | | | llvm-svn: 198258
* Remove MRMInitReg form now that it's last use is gone.Craig Topper2013-12-314-36/+0
| | | | llvm-svn: 198257
* Silence g++ 4.9 build issueAlp Toker2013-12-311-2/+3
| | | | | | | | | lib/Support/ThreadLocal.cpp:53:15: error: typedef 'SIZE_TOO_BIG' locally defined but not used [-Werror=unused-local-typedefs] typedef int SIZE_TOO_BIG[sizeof(pthread_key_t) <= sizeof(data) ? 1 : -1]; Done the C++11 way, switching on and using LLVM_STATIC_ASSERT() instead of LLVM_ATTRIBUTE_UNUSED. llvm-svn: 198255
* Handle MOV32r0 in expandPostRAPseudo instead of MCInst lowering. No ↵Craig Topper2013-12-313-10/+4
| | | | | | functional change intended. llvm-svn: 198254
* Merge case statements to remove redundant code.Craig Topper2013-12-301-18/+12
| | | | llvm-svn: 198241
* Remove special form of AddRegFrm used by FP instructions. These instructions ↵Craig Topper2013-12-303-76/+63
| | | | | | can be handled by MRMXr instead. llvm-svn: 198238
* ARM IAS: account for predicated pre-UAL mnemonicsSaleem Abdulrasool2013-12-301-7/+26
| | | | | | | | Checking the trailing letter of the mnemonic is insufficient. Be more thorough in the scanning of the instruction to ensure that we correctly work with the predicated mnemonics. llvm-svn: 198235
* Refactor and reduce code duplication for non-split dwarf strings.Eric Christopher2013-12-301-18/+9
| | | | llvm-svn: 198233
* Revert r198208 and reapply:Eric Christopher2013-12-304-34/+52
| | | | | | | | | | r198196: Use a pointer to keep track of the skeleton unit for each normal unit and construct it up front. r198199: Reapply r198196 with a fix to zero initialize the skeleton pointer. r198202: Fix aranges and split dwarf by ensuring that the symbol and relocation back to the compile unit from the aranges section is to the skeleton unit and not the one in the dwo. with a fix to use integer 0 for DW_AT_low_pc since the relocation to the text section symbol was causing issues with COFF. Accordingly remove addLocalLabelAddress and machinery since we're not currently using it. llvm-svn: 198222
* Revert r198199 (and r198202). It broke 3 DebugInfo tests for targeting ↵NAKAMURA Takumi2013-12-304-75/+34
| | | | | | | | | | | | | | i686-cygming. r198196: Use a pointer to keep track of the skeleton unit for each normal unit and construct it up front. r198199: Reapply r198196 with a fix to zero initialize the skeleton pointer. r198202: Fix aranges and split dwarf by ensuring that the symbol and relocation back to the compile unit from the aranges section is to the skeleton unit and not the one in the dwo. They could be reproducible with explicit target. llvm/lib/MC/WinCOFFObjectWriter.cpp:224: bool {anonymous}::COFFSymbol::should_keep() const: Assertion `Section->Number != -1 && "Sections with relocations must be real!"' failed. llvm-svn: 198208
* Fix aranges and split dwarf by ensuring that the symbol and relocationEric Christopher2013-12-303-7/+23
| | | | | | | | | | | back to the compile unit from the aranges section is to the skeleton unit and not the one in the dwo. Do this by adding a method to grab a forwarded on local sym and local section by querying the skeleton if one exists and using that. Add a few tests to verify the relocations are back to the correct section. llvm-svn: 198202
* Keep comment with 'Subtarget' ivar.Bill Wendling2013-12-301-1/+1
| | | | llvm-svn: 198201
* Reapply r198196 with a fix to zero initialize the skeleton pointer.Eric Christopher2013-12-303-27/+52
| | | | llvm-svn: 198199
* Temporarily revert "Use a pointer to keep track of the skeleton unit forEric Christopher2013-12-303-51/+26
| | | | | | each normal unit" as it seems to be causing problems in the asan tests. llvm-svn: 198197
* Use a pointer to keep track of the skeleton unit for each normal unitEric Christopher2013-12-303-26/+51
| | | | | | | | | | | and construct it up front. Add address ranges at the end and a helper routine so that we're not needlessly using an indirction in the case of split dwarf. Update testcases according to the new ordering of attributes on the compile unit. llvm-svn: 198196
* For AArch64 Neon, simplify scalar dup by lane0 for fp.Jiangning Liu2013-12-301-17/+22
| | | | llvm-svn: 198194
* [AArch64]Add code to spill/fill Q register tuples such as QPair/QTriple/QQuad.Hao Liu2013-12-302-16/+69
| | | | llvm-svn: 198193
* [AArch64]Can't select shift left 0 of type v1i64Hao Liu2013-12-301-4/+10
| | | | llvm-svn: 198192
* Fix a bug in DAGcombiner about zero-extend after setcc.Kevin Qin2013-12-301-1/+2
| | | | | | | | | | For AArch64 backend, if DAGCombiner see "sext(setcc)", it will combine them together to a single setcc with extended value type. Then if it see "zext(setcc)", it assumes setcc is Vxi1, and try to create "(and (vsetcc), (1, 1, ...)". While setcc isn't Vxi1, DAGcombiner will create wrong node and get wrong code emitted. llvm-svn: 198190
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