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* Add -lowertypetests-bitsets-level to control bitsets generation.Ivan Krasin2016-08-031-2/+9
| | | | | | | | | | | | | | | Summary: Sometimes, bitsets could get really large (>300k entries) and we might want to drop a check, as it would have a too much cost. Adding a flag to control how much penalty are we willing to pay for bitsets. Reviewers: kcc Differential Revision: https://reviews.llvm.org/D23088 llvm-svn: 277556
* Support for lifetime begin/end markers in the MemorySSA use optimizerDaniel Berlin2016-08-031-1/+38
| | | | | | | | | | | | Summary: Depends on D23072 Reviewers: george.burgess.iv Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23076 llvm-svn: 277553
* [WebAssembly] Remove unnecessary subtarget checks in peephole passDerek Schuff2016-08-021-22/+13
| | | | | | | Leftover from D22686; the passes can handle all the instructions unconditionally; only isel needs to care whether to generate them. llvm-svn: 277549
* [safestack] Layout large allocas first to reduce fragmentation.Evgeniy Stepanov2016-08-021-0/+8
| | | | llvm-svn: 277544
* [WebAssembly] Initial SIMD128 support.Derek Schuff2016-08-0216-14/+243
| | | | | | | | | | | | | | Kicks off the implementation of wasm SIMD128 support (spec: https://github.com/stoklund/portable-simd/blob/master/portable-simd.md), adding support for add, sub, mul for i8x16, i16x8, i32x4, and f32x4. The spec is WIP, and might change in the near future. Patch by João Porto Differential Revision: https://reviews.llvm.org/D22686 llvm-svn: 277543
* ARM: only form SMMLS when SUBE flags unused.Tim Northover2016-08-021-1/+2
| | | | | | | | In this particular example we wouldn't want the smmls anyway (the value is actually unused), but in general smmls does not provide the required flags register so if that SUBE result is used we can't replace it. llvm-svn: 277541
* More fixes to get good error messages for bad archives.Kevin Enderby2016-08-022-16/+66
| | | | | | | Fixed the last incorrect uses of llvm_unreachable() in the code which were actually just cases of errors in the input Archives. llvm-svn: 277540
* [InstCombine] replace dyn_casts with matches; NFCISanjay Patel2016-08-022-15/+15
| | | | | | Clean-up before changing this to allow folds for vectors. llvm-svn: 277538
* AMDGPU: fdiv -1, x -> rcp -xMatt Arsenault2016-08-021-16/+25
| | | | llvm-svn: 277535
* Imported statistics types changesPiotr Padlewski2016-08-021-23/+25
| | | | | | | | | | Reviewers: tejohnson, eraman Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22980 llvm-svn: 277534
* [CFLAA] Be more conservative with values we haven't seen.George Burgess IV2016-08-021-11/+16
| | | | | | | | | | | | | | There were issues with simply reporting AttrUnknown on previously-unknown values in CFLAnders. So, we now act *entirely* conservatively for values we haven't seen before. As in the prior patch (r277362), writing a lit test for this isn't exactly trivial. If someone wants a test badly, I'm willing to try to write one. Patch by Jia Chen. Differential Revision: https://reviews.llvm.org/D23077 llvm-svn: 277533
* Move to having a single real instructionClobbersQueryDaniel Berlin2016-08-021-88/+94
| | | | | | | | | | | | Summary: We really want to move towards MemoryLocOrCall (or fix AA) everywhere, but for now, this lets us have a single instructionClobbersQuery. Reviewers: george.burgess.iv Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23072 llvm-svn: 277530
* PDB: Mark extended file pages as free by default.Rui Ueyama2016-08-021-1/+1
| | | | | | | | | BitVector::extend initializes extended bits as true by default. That is not desirable because new pages should be initially free. Differential Revision: https://reviews.llvm.org/D23048 llvm-svn: 277529
* [Hexagon] Recognize vcombine in copy propagationKrzysztof Parzyszek2016-08-021-2/+8
| | | | llvm-svn: 277528
* [LoopUnroll] Switch the default value of -unroll-runtime-epilog back to its ↵Michael Zolotukhin2016-08-021-1/+1
| | | | | | | | | | original value. As agreed in post-commit review of r265388, I'm switching the flag to its original value until the 90% runtime performance regression on SingleSource/Benchmarks/Stanford/Bubblesort is addressed. llvm-svn: 277524
* [NVPTX] remove unnecessary named metadata update that happens to break debug ↵Artem Belevich2016-08-021-36/+0
| | | | | | | | | | info. Also added test case to verify IR changes done by NVPTXGenericToNVVM pass. Differential Revision: https://reviews.llvm.org/D22837 llvm-svn: 277520
* [LoopVectorize] Change comment for isOutOfScope in collectLoopUniforms, NFCWei Mi2016-08-021-3/+4
| | | | | | | | | Update comment for isOutOfScope and add a testcase for uniform value being used out of scope. Differential Revision: https://reviews.llvm.org/D23073 llvm-svn: 277515
* AArch64: properly calculate cmpxchg status in FastISel.Tim Northover2016-08-022-13/+28
| | | | | | | | | | | | We were relying on the misleadingly-names $status result to actually be the status. Actually it's just a scratch register that may or may not be valid (and is the inverse of the real ststus anyway). Success can be determined by comparing the value loaded against the one we wanted to see for "cmpxchg strong" loops like this. Should fix PR28819. llvm-svn: 277513
* Fixes for post-commit review comments on r277480Daniel Berlin2016-08-021-12/+10
| | | | llvm-svn: 277510
* [IRCE] Rename variable; NFCSanjoy Das2016-08-021-6/+6
| | | | | | There is nothing "Original" about "OriginalLoopInfo". llvm-svn: 277506
* [IRCE] Preserve DomTree and LCSSASanjoy Das2016-08-021-5/+11
| | | | | | | This changes IRCE to "preserve" LCSSA and DomTree by recomputing them. It still does not preserve LoopSimplify. llvm-svn: 277505
* AMDGPU: Stay in WQM for non-intrinsic storesNicolai Haehnle2016-08-026-10/+33
| | | | | | | | | | | | | | | | | | | | | | | Summary: Two types of stores are possible in pixel shaders: stores to memory that are explicitly requested at the API level, and stores that are an implementation detail of register spilling or lowering of arrays. For the first kind of store, we must ensure that helper pixels have no effect and hence WQM must be disabled. The second kind of store must always be executed, because the written value may be loaded again in a way that is relevant for helper pixels as well -- and there are no externally visible effects anyway. This is a candidate for the 3.9 release branch. Reviewers: arsenm, tstellarAMD, mareko Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: https://reviews.llvm.org/D22675 llvm-svn: 277504
* [LoopUnroll] Ensure we create prolog loops in simplified form.Michael Zolotukhin2016-08-021-0/+12
| | | | llvm-svn: 277502
* Fix handling of end-of-line preprocessor comments Attempt 2Nirav Dave2016-08-021-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | Attempt 2: Retryign after Tsan.mman test fix. Attempt 1: Recommitting after fixing test. When parsing assembly where the line comment syntax is not hash, the lexer cannot distinguish between hash's that start a hash line comment and one that is part of an assembly statement and must be distinguished during parsing. Previously, this was incompletely handled by not checking for EndOfStatement at the end of statements and interpreting hash prefixed statements as comments. Change EndOfStatement Parsing to check for Hash comments and reintroduce Hash statement parsing to catch previously handled cases. Reviewers: rnk, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23017 llvm-svn: 277501
* AMDGPU: Track physical registers in SIWholeQuadModeNicolai Haehnle2016-08-021-26/+53
| | | | | | | | | | | | | | | | | | | | Summary: There are cases where uniform branch conditions are computed in VGPRs, and we didn't correctly mark those as WQM. The stray change in basic-branch.ll is because invoking the LiveIntervals analysis leads to the detection of a dead register that would otherwise not be seen at -O0. This is a candidate for the 3.9 branch, as it fixes a possible hang. Reviewers: arsenm, tstellarAMD, mareko Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: https://reviews.llvm.org/D22673 llvm-svn: 277500
* [Hexagon] Prefer _io over _rr for 64-bit store with constant offsetKrzysztof Parzyszek2016-08-021-0/+13
| | | | | | | | | Identify patterns where the address is aligned to an 8-byte boundary, but both the base address and the constant offset are both proper multiples of 4. In such cases, extract Base+4 into a separate instruc- tion, and use S2_storerd_io, instead of using S4_storerd_rr. llvm-svn: 277497
* [Hexagon] Remove unused optionKrzysztof Parzyszek2016-08-021-7/+0
| | | | llvm-svn: 277496
* [Hexagon] Improvements to address mode checks in TargetLoweringKrzysztof Parzyszek2016-08-022-2/+39
| | | | | | | - Implement getOptimalMemOpType. - Check BaseOffset in isLegalAddressingMode. llvm-svn: 277494
* [MC] Fix Intel Operand assembly parsing for .set idsNirav Dave2016-08-021-116/+80
| | | | | | | | | | | | | | | | | Recommitting after fixing overaggressive fastpath return in parsing. Fix intel syntax special case identifier operands that refer to a constant (e.g. .set <ID> n) to be interpreted as immediate not memory in parsing. Associated commit to fix clang test commited shortly. Reviewers: rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22585 llvm-svn: 277489
* MSVC 2013 does not implement C++11 unions properly, so remove the anoymous ↵Daniel Berlin2016-08-021-2/+2
| | | | | | | | union for now, and leave a FIXME. llvm-svn: 277485
* [GlobalISel] Set the Selected MF property.Ahmed Bougacha2016-08-021-14/+0
| | | | | | | None of GlobalISel requires the property, but this lets us use the verifier instead of rolling our own "all instructions selected" check. llvm-svn: 277484
* [GlobalISel] Verify Selected MF property.Ahmed Bougacha2016-08-021-1/+15
| | | | | | | | After instruction selection, there should be no pre-isel generic instructions remaining, nor should generic virtual registers be used. Verify that. llvm-svn: 277483
* [GlobalISel] Add Selected MachineFunction property.Ahmed Bougacha2016-08-023-0/+7
| | | | | | | | | | | | | | | | Selected: the InstructionSelect pass ran and all pre-isel generic instructions have been eliminated; i.e., all instructions are now target-specific or non-pre-isel generic instructions (e.g., COPY). Since only pre-isel generic instructions can have generic virtual register operands, this also means that all generic virtual registers have been constrained to virtual registers (assigned to register classes) and that all sizes attached to them have been eliminated. This lets us enforce certain invariants across passes. This property is GlobalISel-specific, but is always available. llvm-svn: 277482
* Rewrite the use optimizer to be less memory intensive and 50% faster.Daniel Berlin2016-08-021-31/+311
| | | | | | | | | | | | | | | | | | | | | | | | Fixes PR28670 Summary: Rewrite the use optimizer to be less memory intensive and 50% faster. Fixes PR28670 The new use optimizer works like a standard SSA renaming pass, storing all possible versions a MemorySSA use could get in a stack, and just tracking indexes into the stack. This uses much less memory than caching N^2 alias query results. It's also a lot faster. The current version defers phi node walking to the normal walker. Reviewers: george.burgess.iv Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23032 llvm-svn: 277480
* [LVI] NFC. Sink a condition type check from the caller down to ↵Artur Pilipenko2016-08-021-31/+33
| | | | | | | | getValueFromCondition This is a preparatory refactoring to support conditions other than ICmpInst. llvm-svn: 277479
* [GlobalISel] Verify RegBankSelected MF property.Ahmed Bougacha2016-08-021-1/+17
| | | | | | | RegBankSelected functions shouldn't have any generic virtual register not assigned to a bank. Verify that. llvm-svn: 277476
* [GlobalISel] Add RegBankSelected MachineFunction property.Ahmed Bougacha2016-08-023-0/+8
| | | | | | | | | | RegBankSelected: the RegBankSelect pass ran and all generic virtual registers have been assigned to a register bank. This lets us enforce certain invariants across passes. This property is GlobalISel-specific, but is always available. llvm-svn: 277475
* [LV] Generate both scalar and vector integer induction variablesMatthew Simpson2016-08-021-34/+66
| | | | | | | | | | | | | | | | This patch enables the vectorizer to generate both scalar and vector versions of an integer induction variable for a given loop. Previously, we only generated a scalar induction variable if we knew all its users were going to be scalar. Otherwise, we generated a vector induction variable. In the case of a loop with both scalar and vector users of the induction variable, we would generate the vector induction variable and extract scalar values from it for the scalar users. With this patch, we now generate both versions of the induction variable when there are both scalar and vector users and select which version to use based on whether the user is scalar or vector. Differential Revision: https://reviews.llvm.org/D22869 llvm-svn: 277474
* [GlobalISel] Set, require, and verify Legalized MF property.Ahmed Bougacha2016-08-022-0/+35
| | | | | | | | | | | | | RegBankSelect and InstructionSelect run after the legalizer and require a Legalized function: check that all instructions are legal. Note that this should be in the MachineVerifier, but it can't use the MachineLegalizer as it's currently in the separate GlobalISel library. Note that the RegBankSelect verifier checks have the same layering problem, but we only use inline methods so end up not needing to link against the GlobalISel library. llvm-svn: 277472
* [AArch64][GlobalISel] Mark basic binops/memops as legal.Ahmed Bougacha2016-08-021-1/+17
| | | | | | | | | | We currently use and test these, and select most of them. Mark them as legal even though we don't go through the full ir->asm flow yet. This doesn't currently have standalone tests, but the verifier will soon learn to check that the regbankselect/select tests are legal. llvm-svn: 277471
* [GlobalISel] Add Legalized MachineFunction property.Ahmed Bougacha2016-08-023-0/+10
| | | | | | | | | | | | | Legalized: The MachineLegalizer ran; all pre-isel generic instructions have been legalized, i.e., all instructions are now one of: - generic and always legal (e.g., COPY) - target-specific - legal pre-isel generic instructions. This lets us enforce certain invariants across passes. This property is GlobalISel-specific, but is always available. llvm-svn: 277470
* Revert "[MC] Fix handling of end-of-line preprocessor comments"Nirav Dave2016-08-021-34/+0
| | | | | | | | Causes TSan failure on PPC64 This reverts commit r277459. llvm-svn: 277468
* [WebAssembly] Remove a README.txt entry that is now implemented.Dan Gohman2016-08-021-6/+0
| | | | llvm-svn: 277467
* [LVI] NFC. Fix a typo getValueFromFromCondition -> getValueFromConditionArtur Pilipenko2016-08-021-11/+9
| | | | llvm-svn: 277466
* [CodeGen] Generalize MachineFunctionProperties::print comma handling.Ahmed Bougacha2016-08-021-2/+7
| | | | | | | | This is only used for debug prints, but the previous hardcoded ", " caused it to be printed unnecessarily when OnlySet, and is annoying when adding new properties. llvm-svn: 277465
* [LV] Untangle the concepts of uniform and scalarMatthew Simpson2016-08-021-63/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch refactors the logic in collectLoopUniforms and collectValuesToIgnore, untangling the concepts of "uniform" and "scalar". It adds isScalarAfterVectorization along side isUniformAfterVectorization to distinguish the two. Known scalar values include those that are uniform, getelementptr instructions that won't be vectorized, and induction variables and induction variable update instructions whose users are all known to be scalar. This patch includes the following functional changes: - In collectLoopUniforms, we mark uniform the pointer operands of interleaved accesses. Although non-consecutive, these pointers are treated like consecutive pointers during vectorization. - In collectValuesToIgnore, we insert a value into VecValuesToIgnore if it isScalarAfterVectorization rather than isUniformAfterVectorization. This differs from the previous functionaly in that we now add getelementptr instructions that will not be vectorized into VecValuesToIgnore. This patch also removes the ValuesNotWidened set used for induction variable scalarization since, after the above changes, it is now equivalent to isScalarAfterVectorization. Differential Revision: https://reviews.llvm.org/D22867 llvm-svn: 277460
* [MC] Fix handling of end-of-line preprocessor commentsNirav Dave2016-08-021-0/+34
| | | | | | | | | | | | | | | | | | | | | | Recommitting after fixing test. When parsing assembly where the line comment syntax is not hash, the lexer cannot distinguish between hash's that start a hash line comment and one that is part of an assembly statement and must be distinguished during parsing. Previously, this was incompletely handled by not checking for EndOfStatement at the end of statements and interpreting hash prefixed statements as comments. Change EndOfStatement Parsing to check for Hash comments and reintroduce Hash statement parsing to catch previously handled cases. Reviewers: rnk, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23017 llvm-svn: 277459
* [ARM] Improve smul* and smla* isel for Thumb2Sam Parker2016-08-023-25/+41
| | | | | | | | | | | | | | Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
* HexagonVectorPrint.cpp: Fix r277370. Don't use getInstrVecReg() in the ↵NAKAMURA Takumi2016-08-021-1/+2
| | | | | | expression of assert(). It has side effects. llvm-svn: 277448
* [GlobalISel] Don't RegBankSelect target-specific instructions.Ahmed Bougacha2016-08-021-1/+7
| | | | | | They don't have types and should be using register classes. llvm-svn: 277447
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