summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* Decompose GVN::processNonLocalLoad() (about 400 LOC) into smaller helper ↵Shuxin Yang2013-05-031-169/+194
| | | | | | | | | | | | | | functions. No function change. This function consists of following steps: 1. Collect dependent memory accesses. 2. Analyze availability. 3. Perform fully redundancy elimination, or 4. Perform PRE, depending on the availability Step 2, 3 and 4 are now moved to three helper routines. llvm-svn: 181047
* [mips] Split the DSP control register and define one register for each field ofAkira Hatanaka2013-05-035-191/+258
| | | | | | | | | | | its fields. This removes false dependencies between DSP instructions which access different fields of the the control register. Implicit register operands are added to instructions RDDSP and WRDSP after instruction selection, depending on the value of the mask operand. llvm-svn: 181041
* LoopVectorizer: Add support for if-conversion of PHINodes with 3+ incoming ↵Nadav Rotem2013-05-031-20/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | values. By supporting the vectorization of PHINodes with more than two incoming values we can increase the complexity of nested if statements. We can now vectorize this loop: int foo(int *A, int *B, int n) { for (int i=0; i < n; i++) { int x = 9; if (A[i] > B[i]) { if (A[i] > 19) { x = 3; } else if (B[i] < 4 ) { x = 4; } else { x = 5; } } A[i] = x; } } llvm-svn: 181037
* R600: Expand vector or, shl, srl, and xor nodesTom Stellard2013-05-031-0/+8
| | | | llvm-svn: 181035
* R600: BFI_INT is a vector-only instructionTom Stellard2013-05-031-1/+1
| | | | llvm-svn: 181034
* R600: Add pattern for SHA-256 Ma functionTom Stellard2013-05-033-0/+17
| | | | | | This can be optimized using the BFI_INT instruction. llvm-svn: 181033
* R600: Clean up comments in Processors.tdTom Stellard2013-05-031-5/+1
| | | | llvm-svn: 181032
* RegionInfo: Do not crash if unreachable block is foundTobias Grosser2013-05-031-1/+2
| | | | llvm-svn: 181025
* [SystemZ] Add MCJIT supportRichard Sandiford2013-05-034-0/+113
| | | | | | | | Another step towards reinstating the SystemZ backend. I'll commit the configure changes separately (TARGET_HAS_JIT etc.), then commit a patch to enable the MCJIT tests on SystemZ. llvm-svn: 181015
* [SystemZ] Support System Z as host architectureUlrich Weigand2013-05-031-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The llvm::sys::AddSignalHandler function (as well as related routines) in lib/Support/Unix/Signals.inc currently registers a signal handler routine via "sigaction". When this handler is called due to a SIGSEGV, SIGILL or similar signal, it will show a stack backtrace, deactivate the handler, and then simply return to the operating system. The intent is that the OS will now retry execution at the same location as before, which ought to again trigger the same error condition and cause the same signal to be delivered again. Since the hander is now deactivated, the OS will take its default action (usually, terminate the program and possibly create a core dump). However, this method doesn't work reliably on System Z: With certain signals (namely SIGILL, SIGFPE, and SIGTRAP), the program counter stored by the kernel on the signal stack frame (which is the location where execution will resume) is not the instruction that triggered the fault, but then instruction *after it*. When the LLVM signal handler simply returns to the kernel, execution will then resume at *that* address, which will not trigger the problem again, but simply go on and execute potentially unrelated code leading to random errors afterwards. To fix this, the patch simply goes and re-raises the signal in question directly from the handler instead of returning from it. This is done only on System Z and only for those signals that have this particular problem. llvm-svn: 181010
* Add support for reading ARM ELF build attributes.Amara Emerson2013-05-032-139/+8
| | | | | | | | | | | Build attribute sections can now be read if they exist via ELFObjectFile, and the llvm-readobj tool has been extended with an option to dump this information if requested. Regression tests are also included which exercise these features. Also update the docs with a fixed ARM ABI link and a new link to the Addenda which provides the build attributes specification. llvm-svn: 181009
* [SystemZ] Add llvm::Triple::systemzRichard Sandiford2013-05-031-0/+8
| | | | | | | First step towards reinstating the SystemZ backend. Tests will be included in the main backend patch. llvm-svn: 181007
* X86: Add target description for btver2; make autodetection logic aware of AVX.Benjamin Kramer2013-05-032-4/+14
| | | | llvm-svn: 181005
* Unbreaking the non-x86 build bots by protecting the AVX test code properly.Aaron Ballman2013-05-031-0/+4
| | | | llvm-svn: 180992
* Correctly testing for AVX support in x86 based off code from Hosts.cpp.Aaron Ballman2013-05-031-1/+18
| | | | llvm-svn: 180991
* Fix missing include in Hexagon code for Release+AssertsReid Kleckner2013-05-031-0/+1
| | | | llvm-svn: 180983
* In MC asm parsing, account for the possibility of whitespace withinJohn McCall2013-05-031-18/+22
| | | | | | | | | | | | | | the "identifier" parsed by the frontend callback by skipping forward until we've consumed a token that ends at the point dictated by the callback. In addition, inform the callback when it's parsing an unevaluated operand (e.g. mov eax, LENGTH A::x) as opposed to an evaluated one (e.g. mov eax, [A::x]). This commit depends on a clang commit. llvm-svn: 180978
* [mips] Handle reading, writing or copying of ccond field of DSP controlAkira Hatanaka2013-05-023-1/+60
| | | | | | | | | | | | register. - Define pseudo instructions which store or load ccond field of the DSP control register. - Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack. - Expand the pseudos before callee-scan save. - Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs. llvm-svn: 180969
* reverting r180953Jyotsna Verma2013-05-025-305/+404
| | | | llvm-svn: 180964
* R600: Signed literals are 64bits wideVincent Lejeune2013-05-021-3/+3
| | | | llvm-svn: 180960
* R600: If previous bundle is dot4, PV valid chan is always XVincent Lejeune2013-05-021-38/+51
| | | | llvm-svn: 180959
* R600: Improve asmPrint of ALU clauseVincent Lejeune2013-05-023-4/+20
| | | | llvm-svn: 180957
* R600: Prettier asmPrint of AluVincent Lejeune2013-05-024-13/+45
| | | | llvm-svn: 180956
* Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.Jyotsna Verma2013-05-025-404/+305
| | | | llvm-svn: 180953
* [GV] Remove dead code which is really difficult to decipher.Shuxin Yang2013-05-021-26/+2
| | | | | | | | | | | Actually it took me couple of hours trying to make sense of them and only to find they are dead code. I guess the original author used "allSingleSucc" to indicate if there are any critial edge emanating from some blocks, and tried to perform code motion (actually speculation) in the presence of these critical edges; but later on he/she changed mind and decided to perform edge-splitting first. llvm-svn: 180951
* Hexagon - Add peephole optimizations for zero extends.Pranav Bhandarkar2013-05-022-0/+40
| | | | | | | | | | | | * lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a sequence of a pair of i32->i64 extensions followed by a "bitwise or" into COMBINE_rr. * lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg. * test/CodeGen/Hexagon/union-1.ll: New test. * test/CodeGen/Hexagon/combine_ir.ll: Fix test. llvm-svn: 180946
* [mips] Fix the head Mips16RegisterInfo.cpp commentRichard Sandiford2013-05-021-2/+1
| | | | | | ...aka a test commit. llvm-svn: 180936
* Hexagon: Honor __builtin_expect by using branch probabilities.Jyotsna Verma2013-05-024-37/+122
| | | | | | | | | | | | | * lib/Target/Hexagon/HexagonInstrInfo.cpp (GetDotNewPredOp): Given a jump opcode return the right pred.new jump opcode with a taken vs not-taken hint based on branch probabilities provided by the target independent module. * lib/Target/Hexagon/HexagonVLIWPacketizer.cpp: Use the above function. * lib/Target/Hexagon/HexagonNewValueJump.cpp(getNewvalueJumpOpcode): Enhance existing function use branch probabilities like HexagonInstrInfo::GetDotNewPredOp but for New Value (GPR) Jumps. llvm-svn: 180923
* R600: Use new tablegen syntax for patternsTom Stellard2013-05-023-447/+381
| | | | | | | | All but two patterns have been converted to the new syntax. The remaining two patterns will require COPY_TO_REGCLASS instructions, which the VLIW DAG Scheduler cannot handle. llvm-svn: 180922
* R600/SI: remove nonsense select patternTom Stellard2013-05-021-8/+1
| | | | | | | | Fortunately this pattern never matched, otherwise we would have generated incorrect code. Signed-off-by: Christian K??nig <christian.koenig@amd.com> llvm-svn: 180921
* 80-col fixup.Michael Liao2013-05-021-2/+3
| | | | llvm-svn: 180915
* Avoid duplicating logic on frame register selecting when lowering eh_returnMichael Liao2013-05-021-9/+11
| | | | | | No functionality change llvm-svn: 180914
* Avoid duplicating logic on frame register selecting when lowering frameaddrMichael Liao2013-05-021-1/+3
| | | | | | No functionality change llvm-svn: 180912
* TiedTo flag can now be placed on implicit operands. isTwoAddrUse() should lookEvan Cheng2013-05-021-5/+3
| | | | | | | | | | | at all of the operands. Previously it was skipping over implicit operands which cause infinite looping when the two-address pass try to reschedule a two-address instruction below the kill of tied operand. I'm unable to come up with a reasonably sized test case. rdar://13747577 llvm-svn: 180906
* [mips] Rename class and functions. Simplify code.Akira Hatanaka2013-05-011-26/+29
| | | | | | No functionality changes. llvm-svn: 180897
* This exposes more MCJIT options via the C API:Filip Pizlo2013-05-013-32/+27
| | | | | | | | | | | | | | | | | | | | | CodeModel: It's now possible to create an MCJIT instance with any CodeModel you like. Previously it was only possible to create an MCJIT that used CodeModel::JITDefault. EnableFastISel: It's now possible to turn on the fast instruction selector. The CodeModel option required some trickery. The problem is that previously, we were ensuring future binary compatibility in the MCJITCompilerOptions by mandating that the user bzero's the options struct and passes the sizeof() that he saw; the bindings then bzero the remaining bits. This works great but assumes that the bitwise zero equivalent of any field is a sensible default value. But this is not the case for LLVMCodeModel, or its internal equivalent, llvm::CodeModel::Model. In both of those, the default for a JIT is CodeModel::JITDefault (or LLVMCodeModelJITDefault), which is not bitwise zero. Hence this change introduces LLVMInitializeMCJITCompilerOptions(), which will initialize the user's options struct with defaults. The user will use this in the same way that they would have previously used memset() or bzero(). MCJITCAPITest.cpp illustrates the change, as does the comment in ExecutionEngine.h. llvm-svn: 180893
* Revert r180737. The companion patch was reverted, and this is not relevant ↵Bill Wendling2013-05-011-15/+0
| | | | | | right now. llvm-svn: 180889
* Hexagon: Use multiclass for Jump instructions.Jyotsna Verma2013-05-0114-263/+336
| | | | llvm-svn: 180885
* Hexagon: Clear isKill flag on the predicate register inJyotsna Verma2013-05-011-1/+5
| | | | | | PredicateInstruction function. llvm-svn: 180884
* This patch breaks up Wrap.h so that it does not have to include all of Filip Pizlo2013-05-0119-19/+15
| | | | | | | | | | | | | | | | | | | | | | | | the things, and renames it to CBindingWrapping.h. I also moved CBindingWrapping.h into Support/. This new file just contains the macros for defining different wrap/unwrap methods. The calls to those macros, as well as any custom wrap/unwrap definitions (like for array of Values for example), are put into corresponding C++ headers. Doing this required some #include surgery, since some .cpp files relied on the fact that including Wrap.h implicitly caused the inclusion of a bunch of other things. This also now means that the C++ headers will include their corresponding C API headers; for example Value.h must include llvm-c/Core.h. I think this is harmless, since the C API headers contain just external function declarations and some C types, so I don't believe there should be any nasty dependency issues here. llvm-svn: 180881
* SROA: Generate selects instead of shuffles when blending values because this ↵Nadav Rotem2013-05-011-8/+6
| | | | | | | | is the cannonical form. Shuffles are more difficult to lower and we usually don't touch them, while we do optimize selects more often. llvm-svn: 180875
* [inline asm] Return an undef SDValue of the expected value type, rather thanChad Rosier2013-05-011-1/+1
| | | | | | | | | report a fatal error. This allows us to continue processing the translation unit. Test case to come on the clang side because we need an inline asm diagnostics handler in place. rdar://13446483 llvm-svn: 180873
* Optimize away nop CONCAT_VECTOR nodes.Nadav Rotem2013-05-011-0/+39
| | | | | | | | | Optimize CONCAT_VECTOR nodes that merge EXTRACT_SUBVECTOR values that extract from the same vector. rdar://13402653 PR15866 llvm-svn: 180871
* Now that the underlying issue is fixed, revert r180750 and r180722.Rafael Espindola2013-05-013-13/+24
| | | | | | | | | | | The cause of the windows failures was fixed by r180791. Revert to the state after Sabre's original revert. Original message: revert r179735, it has no testcases, and doesn't really make sense. llvm-svn: 180844
* Put VMOVPQIto64rr in the VRPDI class.Rafael Espindola2013-05-011-3/+3
| | | | | | Patch by Joshua Magee. llvm-svn: 180842
* Fixes a buffer overrun where the allocated buffer wasn't large enough to ↵Aaron Ballman2013-05-011-1/+8
| | | | | | accommodate the closing quote escape rules in some instances. llvm-svn: 180836
* Revert "InstCombine: Fold more shuffles of shuffles."Jim Grosbach2013-05-011-12/+5
| | | | | | | | | This reverts commit r180802 There's ongoing discussion about whether this is the right place to make this transformation. Reverting for now while we figure it out. llvm-svn: 180834
* [mips] Fix handling of instructions which copy to/from accumulator registers.Akira Hatanaka2013-04-307-37/+43
| | | | | | | | | Expand copy instructions between two accumulator registers before callee-saved scan is done. Handle copies between integer GPR and hi/lo registers in MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not needed. llvm-svn: 180827
* Only pass 'returned' to target-specific lowering code when the value of ↵Stephen Lin2013-04-302-28/+42
| | | | | | entire register is guaranteed to be preserved. llvm-svn: 180825
* Fix a use after free. RI is freed before the call to getDebugLoc(). ToRichard Trieu2013-04-301-4/+5
| | | | | | prevent this, capture the location before RI is freed. llvm-svn: 180824
OpenPOWER on IntegriCloud