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* [Remarks] Support parsing remark metadata in the YAML remark parserFrancis Visoiu Mistrih2019-07-263-0/+129
| | | | | | | | | | | This adds support to the yaml remark parser to be able to parse remarks directly from the metadata. This supports parsing separate metadata and following the external file with the associated metadata, and also a standalone file containing metadata + remarks all together. llvm-svn: 367148
* [InstCombine] canonicalize negated operand of fdivSanjay Patel2019-07-261-0/+10
| | | | | | | This is a transform that we use with fmul, so use it for fdiv too for consistency. llvm-svn: 367146
* Revert "[X86][SSE] Replace PMULDQ GetDemandedBits combine with ↵Vlad Tsyrklevich2019-07-261-12/+9
| | | | | | | | | SimplifyMultipleUseDemandedBits handler." This reverts r367100, it appears to be causing test failures after Nico's revert of r367091. llvm-svn: 367141
* [PowerPC][AIX]Add lowering of MCSymbol MachineOperand.Sean Fertile2019-07-262-0/+6
| | | | | | | | | | | Adds machine operand lowering for MCSymbolSDNodes to the PowerPC backend. This is needed to produce call instructions in assembly for AIX because the callee operand is a MCSymbolSDNode. The test is XFAIL'ed for asserts due to a (valid) assertion in PEI that the AIX ABI isn't supported yet. Differential Revision: https://reviews.llvm.org/D63738 llvm-svn: 367133
* [AMDGPU] Fix typo.Michael Liao2019-07-261-2/+2
| | | | llvm-svn: 367131
* [AArch64][SVE2] Rename bitperm feature to sve2-bitpermCullen Rhodes2019-07-264-5/+5
| | | | | | | | | | | | | | | | Summary: The bitperm feature flag is now prefixed with SVE2, as it is for all other SVE2 extensions Patch by Maciej Gabka. Reviewers: sdesmalen, rovka, chill, SjoerdMeijer, rengolin Reviewed By: SjoerdMeijer, rengolin Differential Revision: https://reviews.llvm.org/D65327 llvm-svn: 367124
* Revert r367091, it caused PR42777.Nico Weber2019-07-261-59/+2
| | | | llvm-svn: 367118
* [ARM][ParallelDSP] Combine structsSam Parker2019-07-261-19/+15
| | | | | | | Combine OpChain and BinOpChain structs as OpChain is a base class to BinOpChain that is never used. llvm-svn: 367114
* [PowerPC] Add getCRSaveOffset to improve readability. [NFC]Sean Fertile2019-07-262-6/+17
| | | | | | | | | | In preperation for AIX support in FrameLowering: replace a number of literal '8' that represent the stack offset of the condition register save area with a member in PPCFrameLowering. Patch by Chris Bowler. llvm-svn: 367111
* [MIPS GlobalISel] Fix check for void return during lowerCallPetar Avramovic2019-07-261-2/+2
| | | | | | | | | | | Void return used to have unsigned with value 0 for virtual register but with addition of Register class and changes to arguments to lowerCall this is no longer valid. Check for void return by inspecting the Ty field in OrigRet. Differential Revision: https://reviews.llvm.org/D65321 llvm-svn: 367107
* [AMDGPU] Move WQM/WWM intrinsic instruction selection to AMDGPUISelDAGToDAGCarl Ritson2019-07-262-10/+6
| | | | | | | | | | | | | | Reviewers: arsenm, nhaehnle Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65328 llvm-svn: 367105
* [MIPS GlobalISel] Select inttoptr and ptrtointPetar Avramovic2019-07-263-1/+11
| | | | | | | | Select G_INTTOPTR and G_PTRTOINT for MIPS32. Differential Revision: https://reviews.llvm.org/D65217 llvm-svn: 367104
* [InstCombine] remove flop from lerp patternsSanjay Patel2019-07-261-0/+20
| | | | | | | | | | | | | | | | | (Y * (1.0 - Z)) + (X * Z) --> Y - (Y * Z) + (X * Z) --> Y + Z * (X - Y) This is part of solving: https://bugs.llvm.org/show_bug.cgi?id=42716 Factoring eliminates an instruction, so that should be a good canonicalization. The potential conversion to FMA would be handled by the backend based on target capabilities. Differential Revision: https://reviews.llvm.org/D65305 llvm-svn: 367101
* [X86][SSE] Replace PMULDQ GetDemandedBits combine with ↵Simon Pilgrim2019-07-261-9/+12
| | | | | | | | SimplifyMultipleUseDemandedBits handler. This removes a GetDemandedBits user and allows us to benefit from the DemandedElts propagated through SimplifyDemandedBits. llvm-svn: 367100
* [NFC][ARM][ParallelDSP] Cleanup isNarrowSequenceSam Parker2019-07-261-26/+5
| | | | | | Remove unused logic. llvm-svn: 367099
* [SelectionDAG] GetDemandedBits - update SIGN_EXTEND_INREG op to just call ↵Simon Pilgrim2019-07-261-9/+1
| | | | | | SimplifyMultipleUseDemandedBits. llvm-svn: 367098
* [AMDGPU] Add llvm.amdgcn.softwqm intrinsicCarl Ritson2019-07-265-1/+38
| | | | | | | | | | | | | | | | | Add llvm.amdgcn.softwqm intrinsic which behaves like llvm.amdgcn.wqm only if there is other WQM computation in the shader. Reviewers: nhaehnle, tpr Reviewed By: nhaehnle Subscribers: arsenm, kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64935 llvm-svn: 367097
* [TargetLowering] SimplifyMultipleUseDemandedBits - add SIGN_EXTEND_INREG ↵Simon Pilgrim2019-07-261-0/+7
| | | | | | support. llvm-svn: 367096
* [AArch64] Define ETE and TRBE system registersMomchil Velikov2019-07-264-1/+45
| | | | | | | | | | | | | | | | | | | | Embedded Trace Extension and Trace Buffer Extension are optional future architecture extensions. (cf. https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools) Their system registers are documented here: https://developer.arm.com/docs/ddi0601/a ETE shares register names with ETM. One exception is the ETE TRCEXTINSELR0 register, which has the same encoding as the ETM TRCEXTINSELR register (but different semantics). This patch treats them as aliases: the assembler will accept both names, emitting identical encoding, and the disassembler will keep disassembling to TRCEXRINSELR. Differential Revision: https://reviews.llvm.org/D63707 llvm-svn: 367093
* [SelectionDAG] GetDemandedBits - update OR/XOR ops to just call ↵Simon Pilgrim2019-07-261-6/+2
| | | | | | | | SimplifyMultipleUseDemandedBits. Eventually all of these will be moved over, but we create nodes in GetDemandedBits recursion at the moment which causes regressions when we try to remove them all. llvm-svn: 367092
* [TargetLowering] SimplifyMultipleUseDemandedBits - add BITCAST pass through ↵Simon Pilgrim2019-07-261-2/+59
| | | | | | | | support. This allows us to peek through BITCASTs and attempt simplify the source operand, and then bitcast back. llvm-svn: 367091
* [ARM][LowOverheadLoops] Add CPSR defsSam Parker2019-07-261-2/+4
| | | | | | | | | | Both WhileLoopStart and LoopEnd may get turned into a cmp and br pair, so add an implicit def to these pseudo instructions in case that WLS and LE aren't generated. Differential Revision: https://reviews.llvm.org/D65275 llvm-svn: 367089
* [WinEH] Allocate space in funclets stack to save XMM CSRsPengfei Wang2019-07-263-23/+127
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This is an alternate approach to D57970. Currently funclets reuse the same stack slots that are used in the parent function for saving callee-saved xmm registers. If the parent function modifies a callee-saved xmm register before an excpetion is thrown, the catch handler will overwrite the original saved value. This patch allocates space in funclets stack for saving callee-saved xmm registers and uses RSP instead RBP to access memory. Reviewers: andrew.w.kaylor, LuoYuanke, annita.zhang, craig.topper, RKSimon Subscribers: rnk, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63396 Signed-off-by: pengfei <pengfei.wang@intel.com> llvm-svn: 367088
* [Loop Utils] Extend the scope of addStringMetadataToLoop.Serguei Katkov2019-07-261-2/+18
| | | | | | | | | | | | To avoid duplicates in loop metadata, if the string to add is already there, just update the value. Reviewers: reames, Ashutosh Reviewed By: reames Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D65265 llvm-svn: 367087
* [Loop Utils] Move utilty addStringMetadataToLoop to LoopUtils.cpp. NFC.Serguei Katkov2019-07-262-31/+31
| | | | | | | | | | | Just move the utility function to LoopUtils.cpp to re-use it in loop peeling. Reviewers: reames, Ashutosh Reviewed By: reames Subscribers: hiraditya, asbirlea, llvm-commits Differential Revision: https://reviews.llvm.org/D65264 llvm-svn: 367085
* Fix macOS build after r358716Yi Kong2019-07-261-1/+1
| | | | | | | | | COPYFILE_CLONE is only defined on newer macOS versions, using it without check breaks build on systems running legacy OS and toolchain. Differential Revision: https://reviews.llvm.org/D65317 llvm-svn: 367084
* Some case eror for: detected memory leaksKang Zhang2019-07-261-25/+0
| | | | llvm-svn: 367083
* AMDGPU/GlobalISel: Handle most function return typesMatt Arsenault2019-07-262-32/+141
| | | | | | | | | handleAssignments gives up pretty easily on structs, and i8 values for some reason. The other case that doesn't work is when an implicit sret needs to be inserted if the return size exceeds the number of return registers. llvm-svn: 367082
* [PowerPC] Do the Simple Early Return in block-placement pass to optimize the ↵Kang Zhang2019-07-261-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | blocks Summary: In `block-placement` pass, it will create some patterns for unconditional we can do the simple early retrun. But the `early-ret` pass is before `block-placement`, we don't want to run it again. This patch is to do the simple early return to optimize the blocks at the last of `block-placement`. Below is an example ``` BB: | BB: XOR 3, 3, 4 | XOR 3, 3, 4 B TBB | B ChainBB ... | ... ChainBB: | ChainBB: B TBB | ADD 3, 3, 4 ... | BLR TBB: | ADD 3, 3, 4 | BLR | ``` Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D63972 llvm-svn: 367080
* Reland: [Remarks] Add support for serializing metadata for every remark streamerFrancis Visoiu Mistrih2019-07-262-48/+78
| | | | | | | | | | | | This allows every serializer format to implement metaSerializer() and return the corresponding meta serializer. Original llvm-svn: 366946 Reverted llvm-svn: 367004 This fixes the unit tests on Windows bots. llvm-svn: 367078
* [AArch64][GlobalISel] Simplify zext/sext selection, use MachineIRBuilder. NFC.Amara Emerson2019-07-261-32/+28
| | | | llvm-svn: 367075
* [CodeGen] Don't resolve the stack protector frame accesses until PEIFrancis Visoiu Mistrih2019-07-251-0/+8
| | | | | | | | | | | | | | | | | | | | Currently, stack protector loads and stores are resolved during LocalStackSlotAllocation (if the pass needs to run). When this is the case, the base register assigned to the frame access is going to be one of the vregs created during LocalStackSlotAllocation. This means that we are keeping a pointer to the stack protector slot, and we're using this pointer to load and store to it. In case register pressure goes up, we may end up spilling this pointer to the stack, which can be a security concern. Instead, leave it to PEI to resolve the frame accesses. In order to do that, we make all stack protector accesses go through frame index operands, then PEI will resolve this using an offset from sp/fp/bp. Differential Revision: https://reviews.llvm.org/D64759 llvm-svn: 367068
* [BPF] fix typedef issue for offset relocationYonghong Song2019-07-252-9/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the CO-RE offset relocation does not work if any struct/union member or array element is a typedef. For example, typedef const int arr_t[7]; struct input { arr_t a; }; func(...) { struct input *in = ...; ... __builtin_preserve_access_index(&in->a[1]) ... } The BPF backend calculated default offset is 0 while 4 is the correct answer. Similar issues exist for struct/union typedef's. When getting struct/union member or array element type, we should trace down to the type by skipping typedef and qualifiers const/volatile as this is what clang did to generate getelementptr instructions. (const/volatile member type qualifiers are already ignored by clang.) This patch fixed this issue, for each access index, skipping typedef and const/volatile/restrict BTF types. Signed-off-by: Yonghong Song <yhs@fb.com> Differential Revision: https://reviews.llvm.org/D65259 llvm-svn: 367062
* [FileCollector] add support for recording empty directoriesAlex Lorenz2019-07-251-6/+19
| | | | | | | | | | | | | | | | The file collector class is useful for constructing reproducers by creating a snapshot of the files that are accessed. Sometimes it might also be important to construct directories that don't necessarily have files, but are still accessed by some tool that we want to make a reproducer for. This is useful for instance for modeling the behavior of Clang's header search, which scans through a number of directories it doesn't actually access when looking for framework headers. This commit extends the file collector to allow it to work with paths that are just directories, by constructing them as the files are copied over. Differential Revision: https://reviews.llvm.org/D65297 llvm-svn: 367061
* [AArch64][GlobalISel] Fix G_SELECT legalization fallback after r366943.Amara Emerson2019-07-251-1/+1
| | | | | | Changes the order of legalization of G_ICMP suggested by Petar in D65079. llvm-svn: 367060
* Reland the "[NewPM] Port Sancov" patch from rL365838. No functionalLeonard Chan2019-07-254-111/+262
| | | | | | | | | | | | | | | | | | | | | changes were made to the patch since then. -------- [NewPM] Port Sancov This patch contains a port of SanitizerCoverage to the new pass manager. This one's a bit hefty. Changes: - Split SanitizerCoverageModule into 2 SanitizerCoverage for passing over functions and ModuleSanitizerCoverage for passing over modules. - ModuleSanitizerCoverage exists for adding 2 module level calls to initialization functions but only if there's a function that was instrumented by sancov. - Added legacy and new PM wrapper classes that own instances of the 2 new classes. - Update llvm tests and add clang tests. llvm-svn: 367053
* [PredicateInfo] Replace pointer comparisons with deterministic compares.Florian Hahn2019-07-251-9/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently there are a few pointer comparisons in ValueDFS_Compare, which can cause non-deterministic ordering when materializing values. There are 2 cases this patch fixes: 1. Order defs before uses used to compare pointers, which guarantees defs before uses, but causes non-deterministic ordering between 2 uses or 2 defs, depending on the allocation order. By converting the pointers to booleans, we can circumvent that problem. 2. comparePHIRelated was comparing the basic block pointers of edges, which also results in a non-deterministic order and is also not really meaningful for ordering. By ordering by their destination DFS numbers we guarantee a deterministic order. For the example below, we can end up with 2 different uselist orderings, when running `opt -mem2reg -ipsccp` hundreds of times. Because the non-determinism is caused by allocation ordering, we cannot reproduce it with ipsccp alone. declare i32 @hoge() local_unnamed_addr #0 define dso_local i32 @ham(i8* %arg, i8* %arg1) #0 { bb: %tmp = alloca i32 %tmp2 = alloca i32, align 4 br label %bb19 bb4: ; preds = %bb20 br label %bb6 bb6: ; preds = %bb4 %tmp7 = call i32 @hoge() store i32 %tmp7, i32* %tmp %tmp8 = load i32, i32* %tmp %tmp9 = icmp eq i32 %tmp8, 912730082 %tmp10 = load i32, i32* %tmp br i1 %tmp9, label %bb11, label %bb16 bb11: ; preds = %bb6 unreachable bb13: ; preds = %bb20 br label %bb14 bb14: ; preds = %bb13 %tmp15 = load i32, i32* %tmp br label %bb16 bb16: ; preds = %bb14, %bb6 %tmp17 = phi i32 [ %tmp10, %bb6 ], [ 0, %bb14 ] br label %bb19 bb18: ; preds = %bb20 unreachable bb19: ; preds = %bb16, %bb br label %bb20 bb20: ; preds = %bb19 indirectbr i8* null, [label %bb4, label %bb13, label %bb18] } Reviewers: davide, efriedma Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D64866 llvm-svn: 367049
* [Loop Peeling] Fix idom detection algorithm.Serguei Katkov2019-07-251-1/+20
| | | | | | | | | | | | | | | | | | | | | | We'd like to determine the idom of exit block after peeling one iteration. Let Exit is exit block. Let ExitingSet - is a set of predecessors of Exit block. They are exiting blocks. Let Latch' and ExitingSet' are copies after a peeling. We'd like to find an idom'(Exit) - idom of Exit after peeling. It is an evident that idom'(Exit) will be the nearest common dominator of ExitingSet and ExitingSet'. idom(Exit) is a nearest common dominator of ExitingSet. idom(Exit)' is a nearest common dominator of ExitingSet'. Taking into account that we have a single Latch, Latch' will dominate Header and idom(Exit). So the idom'(Exit) is nearest common dominator of idom(Exit)' and Latch'. All these basic blocks are in the same loop, so what we find is (nearest common dominator of idom(Exit) and Latch)'. Reviewers: reames, fhahn Reviewed By: reames Subscribers: hiraditya, zzheng, llvm-commits Differential Revision: https://reviews.llvm.org/D65292 llvm-svn: 367044
* [SimplifyCFG] avoid crashing after simplifying a switch (PR42737)Sanjay Patel2019-07-251-8/+17
| | | | | | | | Later code in TryToSimplifyUncondBranchFromEmptyBlock() assumes that we have cleaned up unreachable blocks, but that was not happening with this switch transform. llvm-svn: 367037
* Make GCC happy about attribute locationJF Bastien2019-07-251-1/+2
| | | | | | It doesn't like function attributes on definitions, only declarations. llvm-svn: 367036
* Fix unused function from r367031JF Bastien2019-07-251-1/+1
| | | | llvm-svn: 367035
* [LOOPINFO] Introduce the loop guard API.Whitney Tsang2019-07-251-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is the first patch for the loop guard. We introduced getLoopGuardBranch() and isGuarded(). This currently only works on simplified loop, as it requires a preheader and a latch to identify the guard. It will work on loops of the form: /// GuardBB: /// br cond1, Preheader, ExitSucc <== GuardBranch /// Preheader: /// br Header /// Header: /// ... /// br Latch /// Latch: /// br cond2, Header, ExitBlock /// ExitBlock: /// br ExitSucc /// ExitSucc: Prior discussions leading upto the decision to introduce the loop guard API: http://lists.llvm.org/pipermail/llvm-dev/2019-May/132607.html Reviewer: reames, kbarton, hfinkel, jdoerfert, Meinersbur, dmgreen Reviewed By: reames Subscribers: wuzish, hiraditya, jsji, llvm-commits, bmahjour, etiotto Tag: LLVM Differential Revision: https://reviews.llvm.org/D63885 llvm-svn: 367033
* Allow prefetching from non-zero address spacesJF Bastien2019-07-252-2/+15
| | | | | | | | | | | | | | | Summary: This is useful for targets which have prefetch instructions for non-default address spaces. <rdar://problem/42662136> Subscribers: nemanjai, javed.absar, hiraditya, kbarton, jkorous, dexonsmith, cfe-commits, llvm-commits, RKSimon, hfinkel, t.p.northover, craig.topper, anemet Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D65254 llvm-svn: 367032
* CrashHandler: be careful about crashing while handlingJF Bastien2019-07-251-16/+47
| | | | | | | | | | | | | | | | | | | | | Summary: Looking at the current Apple-specific code for crash handling it does a few silly things that I think we should avoid while handling crashes: * Try real hard not to allocate. * Set the global crash reporter string early so that any crash while generating the stack trace will still report some info. * Prevent reordering of operations in the current thread. <rdar://problem/53503334> Subscribers: hiraditya, jkorous, dexonsmith, llvm-commits, beanz, Bigcheese, thakis, lattner, jordan_rose Tags: #llvm Differential Revision: https://reviews.llvm.org/D65235 llvm-svn: 367031
* [BPF] fix CO-RE incorrect index access stringYonghong Song2019-07-252-17/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, we expect the CO-RE offset relocation records a string encoding the original getelementptr access index, so kernel bpf loader can decode it correctly. For example, struct s { int a; int b; }; struct t { int c; int d; }; #define _(x) (__builtin_preserve_access_index(x)) int get_value(const void *addr1, const void *addr2); int test(struct s *arg1, struct t *arg2) { return get_value(_(&arg1->b), _(&arg2->d)); } We expect two offset relocations: reloc 1: type s, access index 0, 1 reloc 2: type t, access index 0, 1 Two globals are created to retain access indexes for the above two relocations with global variable names. The first global has a name "0:1:". Unfortunately, the second global has the name "0:1:.1" as the llvm internals automatically add suffix ".1" to a global with the same name. Later on, the BPF peels the last character and record "0:1" and "0:1:." in the relocation table. This is not desirable. BPF backend could use the global variable suffix knowledge to generate correct access str. This patch rather took an approach not relying on that knowledge. It generates "s:0:1:" and "t:0:1:" to avoid global variable suffixes and later on generate correct index access string "0:1" for both records. Signed-off-by: Yonghong Song <yhs@fb.com> Differential Revision: https://reviews.llvm.org/D65258 llvm-svn: 367030
* Revert "[InstCombine] try to narrow a truncated load"Vlad Tsyrklevich2019-07-251-39/+0
| | | | | | | | | This reverts commit bc4a63fd3c29c1a8ce22891bf34ee4dccfef578c, this is a speculative revert to fix a number of sanitizer bots (like sanitizer-x86_64-linux-bootstrap-ubsan) that have started to see stage2 compiler crashes, presumably due to a miscompile. llvm-svn: 367029
* [PredicateInfo] Use SmallVector instead of SmallPtrSet.Florian Hahn2019-07-251-13/+8
| | | | | | | | | | | | | | | | | | | | We do not need the SmallPtrSet to avoid adding duplicates to OpsToRename, because we already keep a ValueInfo mapping. If we see an op for the first time, Infos will be empty and we can also add it to OpsToRename. We process operands by visiting BBs depth-first and then iterate over all instructions & users, so the order should be deterministic. Therefore we can skip one round of sorting, which we purely needed for guaranteeing a deterministic order when iterating over the SmallPtrSet. Reviewers: efriedma, davide Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D64816 llvm-svn: 367028
* [AMDGPU] Run `unreachable-mbb-elimination` after isel to clean up PHIs.Michael Liao2019-07-251-0/+3
| | | | | | | | | | | | | | | | | | | | Summary: - As LCSSA is turned on just before isel, it may create PHI of the flow, which is consumed by pseudo structurized CFG instructions. When that PHIs are eliminated in O0, COPY may be placed wrongly as the these pseudo structurized CFG instructions are considering prologue of MBB. - Run extra `unreachable-mbb-elimination` at the end of isel to clean up PHIs. Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64353 llvm-svn: 367023
* [AArch64][SVE] Allow explicit size specifier for predicate operandMomchil Velikov2019-07-251-8/+15
| | | | | | | | | | | | | ... for the vector forms of `{SQ,UQ,}{INC,DEC}P` instructions. Also continue supporting the exsting behaviour of not requiring an explicit size specifier. The preferred disasembly is *with* the specifier. This is implemented by redefining intruction forms to require vector predicates with explicit size and adding aliases, which allow a predicate with no size. Differential Revision: https://reviews.llvm.org/D65145 llvm-svn: 367019
* AMDGPU: Don't assert on v4f16 arguments to shader calling conventionsMatt Arsenault2019-07-251-1/+2
| | | | llvm-svn: 367018
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