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* [InstCombine] allow non-splat folds of select cond (ext X), CSanjay Patel2016-09-302-40/+34
| | | | llvm-svn: 282906
* [Coroutines] Part15c: Fix coro-split to correctly handle definitions between ↵Gor Nishanov2016-09-301-22/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | coro.save and coro.suspend Summary: In the case below, %Result.i19 is defined between coro.save and coro.suspend and used after coro.suspend. We need to correctly place such a value into the coroutine frame. ``` %save = call token @llvm.coro.save(i8* null) %Result.i19 = getelementptr inbounds %"struct.lean_future<int>::Awaiter", %"struct.lean_future<int>::Awaiter"* %ref.tmp7, i64 0, i32 0 %suspend = call i8 @llvm.coro.suspend(token %save, i1 false) switch i8 %suspend, label %exit [ i8 0, label %await.ready i8 1, label %exit ] await.ready: %val = load i32, i32* %Result.i19 ``` Reviewers: majnemer Subscribers: llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D24418 llvm-svn: 282902
* [Coroutines] Part15b: Fix dbg information handling in coro-split.Gor Nishanov2016-09-302-6/+13
| | | | | | | | | | | | | | | Summary: Without the fix, if there was a function inlined into the coroutine with debug information, CloneFunctionInto(NewF, &F, VMap, /*ModuleLevelChanges=*/true, Returns); would duplicate all of the debug information including the DICompileUnit. We know use VMap to indicate that debug metadata for a File, Unit and FunctionType should not be duplicated when we creating clones that will become f.resume, f.destroy and f.cleanup. Reviewers: majnemer Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D24417 llvm-svn: 282899
* [Coroutines] Part 15a: Lower coro.subfn.addr in CoroCleanupGor Nishanov2016-09-302-3/+26
| | | | | | | | | | | | Summary: Not all coro.subfn.addr intrinsics can be eliminated in CoroElide through devirtualization. Those that remain need to be lowered in CoroCleanup. Reviewers: majnemer Subscribers: llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D24412 llvm-svn: 282897
* Update loop unroller cost model to make sure debug info does not affect ↵Dehao Chen2016-09-301-0/+3
| | | | | | | | | | | | | | optimization decisions. Summary: Debug info should *not* affect optimization decisions. This patch updates loop unroller cost model to make it not affected by debug info. Reviewers: davidxl, mzolotukhin Subscribers: haicheng, llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D25098 llvm-svn: 282894
* [libFuzzer] add a fuzzer test that finds CVE-2015-3193Kostya Serebryany2016-09-303-0/+184
| | | | llvm-svn: 282892
* [WebAssembly] Make register stackification more conservativeDerek Schuff2016-09-301-19/+15
| | | | | | | | | | | | Register stackification currently checks VNInfo for changes. Make that more accurate by testing each intervening instruction for any other defs to the same virtual register. Patch by Jacob Gravelle Differential Revision: https://reviews.llvm.org/D24942 llvm-svn: 282886
* [Object] Define Archive::isEmpty().Rui Ueyama2016-09-301-1/+4
| | | | llvm-svn: 282884
* [asan] Support dynamic shadow address instrumentationEtienne Bergeron2016-09-301-7/+50
| | | | | | | | | | | | | | | | | | | Summary: This patch is adding the support for a shadow memory with dynamically allocated address range. The compiler-rt needs to export a symbol containing the shadow memory range. This is required to support ASAN on windows 64-bits. Reviewers: kcc, rnk, vitalybuka Subscribers: zaks.anna, kubabrecka, dberris, llvm-commits, chrisha Differential Revision: https://reviews.llvm.org/D23354 llvm-svn: 282881
* [AMDGPU] Choose VMCNT, EXPCNT, LGKMCNT masks and shifts based on the isa versionKonstantin Zhuravlyov2016-09-305-16/+69
| | | | | | Differential Revision: https://reviews.llvm.org/D24973 llvm-svn: 282877
* [AMDGPU] Ask subtarget if waitcnt instruction is needed before barrier ↵Konstantin Zhuravlyov2016-09-302-2/+9
| | | | | | | | instruction Differential Revision: https://reviews.llvm.org/D24985 llvm-svn: 282875
* [AMDGPU] Do not run scalar optimization passes at "-O0"Konstantin Zhuravlyov2016-09-301-2/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D25055 llvm-svn: 282873
* CVP. Turn marking adds as no wrap on by default (was turned off by 279082)Artur Pilipenko2016-09-301-1/+1
| | | | | | With 282650 in tree extra no wrap on adds doesn't cause regressions anymore. Reenable the optimzation. llvm-svn: 282872
* [LV] Build all scalar steps for non-uniform induction variablesMatthew Simpson2016-09-301-14/+3
| | | | | | | | | | | | | | | | When building the steps for scalar induction variables, we previously attempted to determine if all the scalar users of the induction variable were uniform. If they were, we would only emit the step corresponding to vector lane zero. This optimization was too aggressive. We generally don't know the entire set of induction variable users that will be scalar. We have isScalarAfterVectorization, but this is only a conservative estimate of the instructions that will be scalarized. Thus, an induction variable may have scalar users that aren't already known to be scalar. To avoid emitting unused steps, we can only check that the induction variable is uniform. This should fix PR30542. Reference: https://llvm.org/bugs/show_bug.cgi?id=30542 llvm-svn: 282863
* [AVR] Add the ELF object file writerDylan McKay2016-09-302-0/+128
| | | | | | | | | | | | Summary: This adds the ELF32 writer for AVR. Reviewers: kparzysz Subscribers: beanz, mgorny Differential Revision: https://reviews.llvm.org/D25031 llvm-svn: 282856
* Revert "[RegAllocGreedy] Attempt to split unspillable live intervals"Dylan McKay2016-09-301-8/+6
| | | | | | It was accidentally committed. llvm-svn: 282855
* [AVR] Add the assembly instruction printerDylan McKay2016-09-306-2/+260
| | | | | | | | | | | | | | | | | Summary: This change adds the AVR assembly instruction printer. No tests are included in this patch. I have left them downstream so we can add them once `llc` successfully runs (there's very few components left to upstream until this). Reviewers: arsenm, kparzysz Subscribers: wdng, beanz, mgorny Differential Revision: https://reviews.llvm.org/D25028 llvm-svn: 282854
* [RegAllocGreedy] Attempt to split unspillable live intervalsDylan McKay2016-09-301-6/+8
| | | | | | | | | | | | | | | | | | | | | | | Summary: Previously, when allocating unspillable live ranges, we would never attempt to split. We would always bail out and try last ditch graph recoloring. This patch changes this by attempting to split all live intervals before performing recoloring. This fixes LLVM bug PR14879. I can't add test cases for any backends other than AVR because none of them have small enough register classes to trigger the bug. Reviewers: qcolombet Subscribers: MatzeB Differential Revision: https://reviews.llvm.org/D25070 llvm-svn: 282852
* [AVX-512] Store address operand should be an input operand for the special ↵Craig Topper2016-09-301-4/+4
| | | | | | stack spilling pseudos for XMM16-31 and YMM16-31 without VLX. llvm-svn: 282843
* [AVX-512] Add the special stack spilling pseudos for XMM16-31 and YMM16-31 ↵Craig Topper2016-09-301-0/+8
| | | | | | without VLX to teh isFrameLoadOpcode and isFrameStoreOpcode. llvm-svn: 282842
* Revert r282835 "[AVX-512] Always use the full 32 register vector classes for ↵Craig Topper2016-09-301-15/+30
| | | | | | | | addRegisterClass regardless of whether AVX512/VLX is enabled or not." Turns out this doesn't pass verify-machineinstrs. llvm-svn: 282841
* [libfuzzer] test for c-ares CVE-2016-5180Kostya Serebryany2016-09-303-0/+50
| | | | llvm-svn: 282839
* [LDist] Port to new streaming API for opt remarksAdam Nemet2016-09-301-17/+26
| | | | llvm-svn: 282838
* [X86] Add AVX-512 VTs to findRepresentativeClass as well as v16i16 which was ↵Craig Topper2016-09-301-3/+5
| | | | | | | | also missing. Change register class to include the extra 16 AVX512 registers. I'm not completely sure what this method does or why all the 256-bit VTs returned VR128RegClass when the comments on the method definiton say it should return the largest super register class. I just figured AVX-512 should be similar. llvm-svn: 282836
* [AVX-512] Always use the full 32 register vector classes for ↵Craig Topper2016-09-301-30/+15
| | | | | | | | | | addRegisterClass regardless of whether AVX512/VLX is enabled or not. If AVX512 is disabled, the registers should already be marked reserved. Pattern predicates and register classes on instructions should take care of most of the rest. Loads/stores and physical register copies for XMM16-31 and YMM16-31 without VLX have already been taken care of. I'm a little unclear why this changed the register allocation of the SSE2 run of the sad.ll test, but the registers selected appear to be valid after this change. llvm-svn: 282835
* [LoopUnroll] Port to the new streaming interface for opt remarks.Adam Nemet2016-09-302-31/+41
| | | | llvm-svn: 282834
* [thinlto] Don't decay threshold for hot callsitesPiotr Padlewski2016-09-301-5/+22
| | | | | | | | | | | | | | Summary: We don't want to decay hot callsites to import chains of hot callsites. The same mechanism is used in LIPO. Reviewers: tejohnson, eraman, mehdi_amini Subscribers: llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D24976 llvm-svn: 282833
* AMDGPU: Use unsigned compare for eq/neMatt Arsenault2016-09-306-19/+19
| | | | | | | | | | For some reason there are both of these available, except for scalar 64-bit compares which only has u64. I'm not sure why there are both (I'm guessing it's for the one bit inputs we don't use), but for consistency always using the unsigned one. llvm-svn: 282832
* [libFuzzer] remove the code for -print_pcs=1 with the old coverage. It still ↵Kostya Serebryany2016-09-304-47/+2
| | | | | | works with the new one (trace-pc-guard) llvm-svn: 282831
* [libFuzzer] more the feature set to InputCorpus; on feature update, change ↵Kostya Serebryany2016-09-304-39/+80
| | | | | | the feature counter of the old best input llvm-svn: 282829
* [LoopDataPrefetch] Port to new streaming API for opt remarksAdam Nemet2016-09-302-1/+9
| | | | llvm-svn: 282826
* Move UTF functions into namespace llvm.Justin Lebar2016-09-302-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This lets people link against LLVM and their own version of the UTF library. I determined this only affects llvm, clang, lld, and lldb by running $ git grep -wl 'UTF[0-9]\+\|\bConvertUTF\bisLegalUTF\|getNumBytesFor' | cut -f 1 -d '/' | sort | uniq clang lld lldb llvm Tested with ninja lldb ninja check-clang check-llvm check-lld (ninja check-lldb doesn't complete for me with or without this patch.) Reviewers: rnk Subscribers: klimek, beanz, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D24996 llvm-svn: 282822
* [LV] Port the remarks in processLoop to the new streaming APIAdam Nemet2016-09-301-22/+39
| | | | | | This completes LV. llvm-svn: 282821
* [LV] Port the last opt remark in Hints to the new streaming interfaceAdam Nemet2016-09-301-5/+6
| | | | llvm-svn: 282820
* [X86] Don't preserve Win64 SSE CSRs when SSE is disabledReid Kleckner2016-09-302-2/+9
| | | | | | | | | Code that doesn't use floating point and doesn't use SSE (kernel code) shouldn't save and restore SSE registers. Fixes PR30503 llvm-svn: 282819
* [AArch64][RegisterBankInfo] Use static mapping for 3-operands instrs.Quentin Colombet2016-09-301-0/+50
| | | | | | | | This uses a TableGen'ed like structure for all 3-operands instrs. The output of the RegBankSelect pass should be identical but the RegisterBankInfo will do less dynamic allocations. llvm-svn: 282817
* [AArch64][RegisterBankInfo] Add static value mapping for 3-op instrs.Quentin Colombet2016-09-302-12/+58
| | | | | | | This is the kind of input TableGen should generate at some point. NFC. llvm-svn: 282816
* [AArch64][RegisterBankInfo] Check the statically created ValueMapping.Quentin Colombet2016-09-301-0/+18
| | | | | | | | | Make sure that the ValueMappings contain the value we expect at the indices we expect. NFC. llvm-svn: 282815
* [LAA, LV] Port to new streaming interface for opt remarks. Update LVAdam Nemet2016-09-302-27/+44
| | | | | | | | | | | | | | (Recommit after making sure IsVerbose gets properly initialized in DiagnosticInfoOptimizationBase. See previous commit that takes care of this.) OptimizationRemarkAnalysis directly takes the role of the report that is generated by LAA. Then we need the magic to be able to turn an LAA remark into an LV remark. This is done via a new OptimizationRemark ctor. llvm-svn: 282813
* [InstCombine] fix function names; NFCSanjay Patel2016-09-292-44/+48
| | | | | | | | Also, make foldSelectExtConst() a member of InstCombiner, remove unnecessary parameters from its interface, and group visitSelectInst helpers together in the header file. llvm-svn: 282796
* Make HAVE_DECL_ARC4RANDOM always defined. Sort the entry correctly.Joerg Sonnenberger2016-09-291-2/+2
| | | | llvm-svn: 282768
* HAVE_UNWIND_BACKTRACE -> HAVE__UNWIND_BACKTRACEJoerg Sonnenberger2016-09-291-4/+4
| | | | | | Check for existance and not truth value. llvm-svn: 282767
* Next set of additional error checks for invalid Mach-O files for theKevin Enderby2016-09-291-0/+12
| | | | | | | | | load command that uses the MachO::entry_point_command type but not used in llvm libObject code but used in llvm tool code. This includes just the LC_MAIN load command. llvm-svn: 282766
* Clamp version number in S_COMPILE3 to avoid overflowing 16-bit field.Adrian McCarthy2016-09-291-5/+6
| | | | llvm-svn: 282761
* Revert "[LAA, LV] Port to new streaming interface for opt remarks. Update LV"Adam Nemet2016-09-292-44/+27
| | | | | | | | This reverts commit r282758. There are some clang failures I haven't seen. llvm-svn: 282759
* [LAA, LV] Port to new streaming interface for opt remarks. Update LVAdam Nemet2016-09-292-27/+44
| | | | | | | | | | OptimizationRemarkAnalysis directly takes the role of the report that is generated by LAA. Then we need the magic to be able to turn an LAA remark into an LV remark. This is done via a new OptimizationRemark ctor. llvm-svn: 282758
* [RegisterBankInfo] Change the default mapping for Copy and PHI.Quentin Colombet2016-09-292-54/+37
| | | | | | | | | | | | | | Instead of producing a mapping for all the operands, we only generate a mapping for the definition. Indeed, the other operands are not constrained by the instruction and thus, we should leave the choice to the actual definition to do the right thing. In pratice this is almost NFC, but with one advantage. We will have only one instance of OperandsMapping for each copy and phi that map to one register bank instead of one different instance for each different number of operands for each copy and phi. llvm-svn: 282756
* Generalize ArgList::AddAllArgs moreDouglas Katzman2016-09-291-5/+22
| | | | llvm-svn: 282755
* [LV] Port OptimizationRemarkAnalysisFPCommute andAdam Nemet2016-09-292-10/+21
| | | | | | OptimizationRemarkAnalysisAliasing to new streaming API for opt remarks llvm-svn: 282742
* [LV] Convert processLoop to new streaming API for opt remarksAdam Nemet2016-09-291-10/+10
| | | | llvm-svn: 282740
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