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* [AVX-512] Use FR32X/FR64X/VR128X/VR256X register classes in addRegisterClass ↵Craig Topper2016-08-011-15/+30
| | | | | | if AVX512(for FR32X/FR64) or VLX(for VR128X/VR256) is supported. This is a minimal requirement to be able to allocate all 32 registers. llvm-svn: 277319
* [X86] Move mask register handling into the main switch of ↵Craig Topper2016-08-011-22/+6
| | | | | | getLoadStoreRegOpcode. No functional change intended. llvm-svn: 277318
* Revert r277313 and r277314.Sean Silva2016-08-015-163/+23
| | | | | | | | | | | | | | | They seem to trigger an LSan failure: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/15140/steps/check-llvm%20asan/logs/stdio Revert "Add the tests for r277313" This reverts commit r277314. Revert "CodeExtractor : Add ability to preserve profile data." This reverts commit r277313. llvm-svn: 277317
* Fix - CodeExtractor : Inherit Target Dependent Attributes from the parent ↵Sean Silva2016-08-011-1/+16
| | | | | | | | | | | | | | | | | | | function. When extracting a set of blocks make sure to inherit all of the target dependent attributes to make sure that the function will be valid for lowering. One example is the "target-features" attribute for x86, if the extracted region has functionality that relies on a specific feature it will fail to be lowered. This also allows for extracted functions to be valid for inlining, at least back into the parent function, as the target attributes are tested when inlining for compatibility. Patch by River Riddle! Differential Revision: https://reviews.llvm.org/D22713 llvm-svn: 277315
* CodeExtractor : Add ability to preserve profile data.Sean Silva2016-08-015-23/+163
| | | | | | | | | | | Added ability to estimate the entry count of the extracted function and the branch probabilities of the exit branches. Patch by River Riddle! Differential Revision: https://reviews.llvm.org/D22744 llvm-svn: 277313
* Fix the MemorySSA updating API to enable people to create memory accesses ↵Daniel Berlin2016-07-311-4/+6
| | | | | | before removing old ones llvm-svn: 277309
* [X86] Simplify code for determing GR or FR reg classes by querying for super ↵Craig Topper2016-07-311-49/+10
| | | | | | classes instead of manually listing individual classes. llvm-svn: 277306
* [AVX512] Always use EVEX encodings for 128/256-bit move instructions in ↵Craig Topper2016-07-311-24/+15
| | | | | | getLoadStoreRegOpcode if VLX is supported. llvm-svn: 277305
* [AVX512] Add VLX packed move instructions to the execution dependency fix ↵Craig Topper2016-07-311-5/+15
| | | | | | pass and update tests. llvm-svn: 277304
* [AVX512] Move FR32X/FR64X handling in getLoadStoreRegOpcode into the main ↵Craig Topper2016-07-311-15/+11
| | | | | | switch. No functional change intended. llvm-svn: 277303
* [AVX512] Stop treating VR512 specially in getLoadStoreRegOpcode and use the ↵Craig Topper2016-07-311-3/+1
| | | | | | regular switch which already tried to handle it, but was unreachable. This has the added benefit of enabling aligned loads/stores if the stack is aligned. llvm-svn: 277302
* [AVX512] Add X86::VR512RegClassID to X86RegisterInfo::getLargestLegalSuperClass.Craig Topper2016-07-311-0/+1
| | | | llvm-svn: 277301
* [X86] Improve 64-bit shifts on 32-bit targets (PR14593)Simon Pilgrim2016-07-311-4/+30
| | | | | | | | As discussed on PR14593, this patch adds support for lowering to SHLD/SHRD from the patterns generated by DAGTypeLegalizer::ExpandShiftWithKnownAmountBit. Differential Revision: https://reviews.llvm.org/D23000 llvm-svn: 277299
* [COFF] Expose iterators for ImportAddressTableRVADavid Majnemer2016-07-311-2/+17
| | | | | | Patch by Bandzi Michal! llvm-svn: 277298
* [COFF] Remove a duplicate import_directory_table_entry definitionDavid Majnemer2016-07-311-4/+4
| | | | | | | | We had import_directory_table_entry and coff_import_directory_table_entry, remove one. Also, factor out the logic which determins if a descriptor is a terminator. llvm-svn: 277296
* [AVX-512] Don't let ExeDependencyFix pass convert VPANDD/Q to VPANDPS/PD ↵Craig Topper2016-07-311-9/+31
| | | | | | | | unless DQI instructions are supported. Same for ANDN, OR, and XOR. Thanks to Igor Breger for pointing out my mistake. llvm-svn: 277292
* Fixed "copy-paste" mistake from revision 255245.Amjad Aboud2016-07-311-1/+1
| | | | llvm-svn: 277290
* AVX-512: Removed AssertZext node before TRUNCATEElena Demikhovsky2016-07-312-42/+38
| | | | | | | | Removed AssertZext node, which was inserted between X86ISD::SETCC and "truncate to i1". Differential Revision: https://reviews.llvm.org/D22850 llvm-svn: 277289
* [HexagonConstPropagation] Remove dead code.Davide Italiano2016-07-301-22/+0
| | | | llvm-svn: 277285
* [HexagonBitSimplify] Remove dead code.Davide Italiano2016-07-301-18/+0
| | | | llvm-svn: 277284
* [ARMConstantIslandPass] Remove dead code.Davide Italiano2016-07-301-20/+0
| | | | llvm-svn: 277283
* Strip trailing whitespaceSimon Pilgrim2016-07-301-6/+5
| | | | llvm-svn: 277280
* [X86] Use peekThroughOneUseBitcasts helper functionSimon Pilgrim2016-07-301-5/+2
| | | | llvm-svn: 277279
* [X86][SSE] Let 64-bit targets use the fast 2i32-2f32 UINT_TO_FP conversion ↵Simon Pilgrim2016-07-301-4/+3
| | | | | | | | as well as 32-bit The 2i32-2i64 legalization means that we can use the slightly quicker double bits + fptrunc approach for the same results llvm-svn: 277271
* [Hexagon] Perform bit arithmetic on unsigned to avoid accidentally shifting ↵Benjamin Kramer2016-07-301-2/+2
| | | | | | | | negative values. Found by ubsan. llvm-svn: 277268
* [X86] Fix lifetime of SMRange temporaries.Benjamin Kramer2016-07-301-4/+4
| | | | | | Found by asan -fsanitize-address-use-after-scope. llvm-svn: 277266
* [AMDGPU] Fix lifetime of SmallVector temporaries.Benjamin Kramer2016-07-301-6/+4
| | | | | | Found by asan -fsanitize-address-use-after-scope. llvm-svn: 277265
* AMDGPU: Fix shouldConvertConstantLoadToIntImm behaviorMatt Arsenault2016-07-301-2/+2
| | | | | | | This should really be true for any immediate, not just inline ones. llvm-svn: 277260
* AMDGPU: Set s_setpc_b64 as a terminatorMatt Arsenault2016-07-301-0/+3
| | | | llvm-svn: 277259
* AMDGPU: Remove unused patternMatt Arsenault2016-07-301-8/+7
| | | | llvm-svn: 277258
* DAG: avoid duplicated truncating for sign extended operandWeiming Zhao2016-07-291-8/+10
| | | | | | | | | | | | | | | Summary: When performing cmp for EQ/NE and the operand is sign extended, we can avoid the truncaton if the bits to be tested are no less than origianl bits. Reviewers: eli.friedman Subscribers: eli.friedman, aemerson, nemanjai, t.p.northover, llvm-commits Differential Revision: https://reviews.llvm.org/D22933 llvm-svn: 277252
* GlobalISel: translate "unreachable" (into nothing)Tim Northover2016-07-291-0/+3
| | | | | | Easiest instruction ever! llvm-svn: 277225
* GlobalISel: support translation of intrinsic calls.Tim Northover2016-07-293-1/+49
| | | | | | | | These come in two variants for now: G_INTRINSIC and G_INTRINSIC_W_SIDE_EFFECTS. We may decide to split the latter up with finer-grained restrictions later, if necessary. llvm-svn: 277224
* Think this will fix issues with the error messages generated for ↵Kevin Enderby2016-07-291-15/+13
| | | | | | | | | | | | | | | malformed-archives.test in r277177 and added back this test which was deleted in r277196 while I tracked down these problems. Changed from constructing Twine's to std::string's as Twine's don't work across statements. Also removed a few unneeded Twine() constructions. Fix the write_escaped() calls to not pass the unintended second argument fixing the warning on the ld-x86_64-win7 bot. llvm-svn: 277223
* [Hexagon] Referencify MachineInstr in HexagonInstrInfo, NFCKrzysztof Parzyszek2016-07-2915-808/+787
| | | | llvm-svn: 277220
* [X86] Match PSADBW in straight-line codeMichael Kuperstein2016-07-291-2/+135
| | | | | | | | | | | | | Up until now, we only had code to match PSADBW patterns that look like what comes out of the loop vectorizer - a partial reduction inside the loop body that gets fed into a horizontal operation in a different basic block. This adds support for straight-line patterns, like those generated by the SLP vectorizer. Differential Revision: https://reviews.llvm.org/D22889 llvm-svn: 277219
* pdbdump: Dump Free Page Map contents.Rui Ueyama2016-07-291-0/+11
| | | | | | Differential Revision: https://reviews.llvm.org/D22974 llvm-svn: 277216
* [X86][AVX] Fix VBROADCASTF128 selection bug (PR28770)Simon Pilgrim2016-07-291-7/+25
| | | | | | Support for lowering to VBROADCASTF128 etc. in D22460 was not correctly ensuring that the only users of the 128-bit vector load were the insertions of the vector into the lower/upper subvectors. llvm-svn: 277214
* [msf] Resubmit "Rename Msf -> MSF".Zachary Turner2016-07-2932-136/+136
| | | | | | | | | | | | | Previously this change was submitted from a Windows machine, so changes made to the case of filenames and directory names did not survive the commit, and as a result the CMake source file names and the on-disk file names did not match on case-sensitive file systems. I'm resubmitting this patch from a Linux system, which hopefully allows the case changes to make it through unfettered. llvm-svn: 277213
* CodeGen: add new "intrinsic" MachineOperand kind.Tim Northover2016-07-297-9/+78
| | | | | | | This will be used during GlobalISel, where we need a more robust and readable way to write tests than a simple immediate ID. llvm-svn: 277209
* [LoopUnroll] Include hotness of region in opt remarkAdam Nemet2016-07-293-34/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LoopUnroll is a loop pass, so the analysis of OptimizationRemarkEmitter is added to the common function analysis passes that loop passes depend on. The BFI and indirectly BPI used in this pass is computed lazily so no overhead should be observed unless -pass-remarks-with-hotness is used. This is how the patch affects the O3 pipeline: Dominator Tree Construction Natural Loop Information Canonicalize natural loops Loop-Closed SSA Form Pass Basic Alias Analysis (stateless AA impl) Function Alias Analysis Results Scalar Evolution Analysis + Lazy Branch Probability Analysis + Lazy Block Frequency Analysis + Optimization Remark Emitter Loop Pass Manager Rotate Loops Loop Invariant Code Motion Unswitch loops Simplify the CFG Dominator Tree Construction Basic Alias Analysis (stateless AA impl) Function Alias Analysis Results Combine redundant instructions Natural Loop Information Canonicalize natural loops Loop-Closed SSA Form Pass Scalar Evolution Analysis + Lazy Branch Probability Analysis + Lazy Block Frequency Analysis + Optimization Remark Emitter Loop Pass Manager Induction Variable Simplification Recognize loop idioms Delete dead loops Unroll loops ... llvm-svn: 277203
* Fixed (incorrectly firing) MSVC unused variable warningSimon Pilgrim2016-07-291-2/+1
| | | | llvm-svn: 277198
* [ConstantFolding] Handle bitcasts of undef fp vector elementsDavid Majnemer2016-07-291-1/+1
| | | | | | | | | We used the wrong type for constructing a zero vector element which led to type mismatches. This fixes PR28771. llvm-svn: 277197
* Fixed MSVC out of range shift warningSimon Pilgrim2016-07-291-1/+1
| | | | llvm-svn: 277195
* Revert "[msf] Rename Msf to MSF."Zachary Turner2016-07-2932-136/+136
| | | | | | This reverts commit 4d1557ffac41e079bcb1abbcf04f512474dcd6fe. llvm-svn: 277194
* [msf] Rename Msf to MSF.Zachary Turner2016-07-2932-136/+136
| | | | | | | | In a previous patch, it was suggested to use all caps instead of rolling caps for initialisms, so this patch changes everything to do this. llvm-svn: 277190
* Recommitting r275284: add support to inline __builtin_mempcpyAndrew Kaylor2016-07-294-0/+50
| | | | | | | | Patch by Sunita Marathe Third try, now following fixes to MSan to handle mempcy in such a way that this commit won't break the MSan buildbots. (Thanks, Evegenii!) llvm-svn: 277189
* GlobalISel: make translate* functions take the most specialized class possible.Tim Northover2016-07-291-15/+14
| | | | | | NFC. llvm-svn: 277188
* Codegen: MachineBlockPlacement Improve probability layout.Kyle Butt2016-07-291-15/+45
| | | | | | | | | | | | | | | | | | | | | | | | | The following pattern was being layed out poorly: A / \ B C / \ / \ D E ? (Doesn't matter) Where A->B is far more likely than A->C, and prob(B->D) = prob(B->E) The current algorithm gives: A,B,C,E (D goes on worklist) It does this even if C has a frequency count of 0. This patch adjusts the layout calculation so that if freq(B->E) >> freq(C->E) then we go ahead and layout E rather than C. Fallthrough half the time is better than fallthrough never, or fallthrough very rarely. The resulting layout is: A,B,E, (C and D are in a worklist) llvm-svn: 277187
* GlobalISel: add generic conditional branch.Tim Northover2016-07-292-7/+20
| | | | | | | Just the basic equivalent to DAG's condbr for now, we'll get to things like br_cc when we start doing more legalization. llvm-svn: 277184
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