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* Move PPC bits to lib/Target/PowerPC.Rafael Espindola2011-12-225-94/+120
| | | | llvm-svn: 147124
* Hopefully fix the cmake build.Rafael Espindola2011-12-221-0/+1
| | | | llvm-svn: 147121
* Fix name in comments.Rafael Espindola2011-12-221-1/+1
| | | | llvm-svn: 147119
* Local dynamic TLS model for direct object output. Create the correct TLS MIPSAkira Hatanaka2011-12-225-0/+49
| | | | | | | | ELF relocations. Patch by Jack Carter. llvm-svn: 147118
* Unbreak cmake build after r147115.Richard Smith2011-12-221-0/+1
| | | | llvm-svn: 147117
* Move the ARM specific parts of the ELF writer to Target/ARM.Rafael Espindola2011-12-226-275/+310
| | | | llvm-svn: 147115
* getEFlags is const.Rafael Espindola2011-12-222-5/+5
| | | | llvm-svn: 147114
* ARM NEON mnemonic aliase for vrecpeq.Jim Grosbach2011-12-211-0/+3
| | | | llvm-svn: 147109
* ARM VFP optional data type on VMOV GPR<-->SPR.Jim Grosbach2011-12-211-3/+11
| | | | llvm-svn: 147104
* ARM NEON optional data type on VSWP instructions.Jim Grosbach2011-12-211-0/+6
| | | | llvm-svn: 147103
* ARM NEON mnemonic aliases for vzipq and vswpq.Jim Grosbach2011-12-211-0/+3
| | | | llvm-svn: 147102
* Revert patch from 147090. There is not point to make code less readable if weJakub Staszak2011-12-211-43/+45
| | | | | | don't get any serious benefit there. llvm-svn: 147101
* ARM asm parser should be more lenient w/ .thumb_func directive.Jim Grosbach2011-12-211-8/+17
| | | | | | | | | | Rather than require the symbol to be explicitly an argument of the directive, allow it to look ahead and grab the symbol from the next non-whitespace line. rdar://10611140 llvm-svn: 147100
* Fix a copy+pasto. No testcase, because the symptoms of dereferencingDan Gohman2011-12-211-1/+1
| | | | | | an invalid iterator aren't reproducible. rdar://10614085. llvm-svn: 147098
* Thumb2 assembly parsing of 'mov rd, rn, rrx'.Jim Grosbach2011-12-211-1/+3
| | | | | | | | Maps to the RRX instruction. Missed this case earlier. rdar://10615373 llvm-svn: 147096
* Fix 80-column violations.Chad Rosier2011-12-211-6/+6
| | | | llvm-svn: 147095
* Thumb2 assembly parsing of 'mov(register shifted register)' aliases.Jim Grosbach2011-12-212-0/+41
| | | | | | | | These map to the ASR, LSR, LSL, ROR instruction definitions. rdar://10615373 llvm-svn: 147094
* Continue counting intrinsics as instructions (except when they aren't, such asNick Lewycky2011-12-211-3/+17
| | | | | | debug info) and for being vector operations. Fixes regression from r147037. llvm-svn: 147093
* Fix typo and spacing, no functionality change.Nick Lewycky2011-12-211-2/+2
| | | | llvm-svn: 147092
* - Change a few operator[] to lookup which is cheaper.Jakub Staszak2011-12-211-45/+43
| | | | | | - Add some constantness. llvm-svn: 147090
* Oops - LiveIntervalUnion.cpp file does use std::find. Moving STL header ↵Lang Hames2011-12-211-0/+2
| | | | | | include to LiveIntervalUnion.cpp file. llvm-svn: 147089
* Remove disused STL header include.Lang Hames2011-12-211-2/+0
| | | | llvm-svn: 147088
* Switch from WriteEFlags to getEFlags in preparation for moving itRafael Espindola2011-12-212-9/+8
| | | | | | to Target/. llvm-svn: 147087
* Move common code into an MRI function.Jakob Stoklund Olesen2011-12-213-24/+6
| | | | llvm-svn: 147071
* ARM NEON assmebly parsing for VLD2 to all lanes instructions.Jim Grosbach2011-12-214-30/+70
| | | | llvm-svn: 147069
* No case stmt for BUILD_VECTOR in PerformDAGCombine(), so I assume this isn't Chad Rosier2011-12-211-1/+0
| | | | | | necessary. Please chime in if I'm mistaken. llvm-svn: 147065
* Fix a couple of copy-n-paste bugs. Noticed by George Russell!Chad Rosier2011-12-211-4/+4
| | | | llvm-svn: 147064
* Changes the JSON parser to use the SourceMgr.Manuel Klimek2011-12-211-26/+33
| | | | | | | | Diagnostics are now emitted via the SourceMgr and we use MemoryBuffer for buffer management. Switched the code to make use of the trailing '0' that MemoryBuffer guarantees where it makes sense. llvm-svn: 147063
* Move the X86 specific bits of the ELF writer to the Target/X86 directory.Rafael Espindola2011-12-217-221/+251
| | | | | | Other targets will follow shortly. llvm-svn: 147060
* Reduce the exposure of Triple::OSType in the ELF object writer. This willRafael Espindola2011-12-217-53/+55
| | | | | | | avoid including ADT/Triple.h in many places when the target specific bits are moved. llvm-svn: 147059
* Small refactoring so that RelocNeedsGOT can stay in the target independentRafael Espindola2011-12-212-24/+16
| | | | | | side when the target specific bits are moved to the Target directory. llvm-svn: 147053
* Removes unused field TheError from LLLexer.Manuel Klimek2011-12-211-1/+0
| | | | llvm-svn: 147049
* Remove mode specific disassembler classes and just call ↵Craig Topper2011-12-213-43/+7
| | | | | | X86GenericDisassembler constructor with appropriate argument in the creation functions. This removes a few tables that needed to be anchored. llvm-svn: 147046
* Fix typo in a couple commentsCraig Topper2011-12-211-3/+3
| | | | llvm-svn: 147045
* A call to a function marked 'noinline' is not an inline candidate. The soleNick Lewycky2011-12-211-4/+4
| | | | | | | call site of an intrinsic is also not an inline candidate. While here, make it more obvious that this code ignores all intrinsics. Noticed by inspection! llvm-svn: 147037
* Make some intrinsics safe to speculatively execute.Nick Lewycky2011-12-212-4/+25
| | | | llvm-svn: 147036
* Fix a couple of copy-n-paste bugs. Noticed by George Russell.Evan Cheng2011-12-211-2/+2
| | | | llvm-svn: 147032
* ARM assembly parsing allows constant expressions for lane indices.Jim Grosbach2011-12-211-14/+25
| | | | llvm-svn: 147028
* ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.Jim Grosbach2011-12-215-16/+54
| | | | llvm-svn: 147025
* Fix bug in zero-store peephole pattern reported in pr11615.Akira Hatanaka2011-12-211-4/+8
| | | | | | The patch and test case were originally written by Mans Rullgard. llvm-svn: 147024
* Expand 64-bit CTLZ nodes if target architecture does not support it. Add testAkira Hatanaka2011-12-211-1/+3
| | | | | | case for DCLO and DCLZ. llvm-svn: 147022
* Expand 64-bit CTPOP and CTTZ.Akira Hatanaka2011-12-211-0/+2
| | | | llvm-svn: 147021
* Expand 64-bit atomic load and store.Akira Hatanaka2011-12-211-0/+2
| | | | llvm-svn: 147019
* Add definition of DSBH (Double Swap Bytes within Halfwords) and Akira Hatanaka2011-12-202-1/+9
| | | | | | | DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces 64-bit bswap with a DSBH and DSHD pair. llvm-svn: 147017
* Add definition of WSBH (Word Swap Bytes within Halfwords), which is anAkira Hatanaka2011-12-202-8/+10
| | | | | | | | | | instruction supported by mips32r2, and add a pattern which replaces bswap with a ROTR and WSBH pair. WSBW is removed since it is not an instruction the current architectures support. llvm-svn: 147015
* 64-bit uint-fp conversion nodes are expanded.Akira Hatanaka2011-12-201-0/+2
| | | | llvm-svn: 147014
* Enable custom lowering DYNAMIC_STACKALLOC nodes.Akira Hatanaka2011-12-201-0/+1
| | | | llvm-svn: 147013
* Set the correct stack pointer register that should be saved or restored.Akira Hatanaka2011-12-201-1/+1
| | | | llvm-svn: 147012
* Fix a nasty bug in the type remapping stuff that I added that is breaking ↵Chris Lattner2011-12-201-1/+8
| | | | | | | | | | | | | | | | kc++ on the build bot in some cases. The basic issue happens when a source module contains both a "%foo" type and a "%foo.42" type. It will see the later one, check to see if the destination module contains a "%foo" type, and it will return true... because both the source and destination modules are in the same LLVMContext. We don't want to map source types to other source types, so don't do the remapping if the mapped type came from the source module. Unfortunately, I've been unable to reduce a decent testcase for this, kc++ is pretty great that way. llvm-svn: 147010
* ARM .req register name aliases are case insensitive, just like regnames.Jim Grosbach2011-12-201-3/+4
| | | | llvm-svn: 147009
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