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* GlobalISel: don't leak super-entry BB when merging with IR-level one.Tim Northover2017-01-271-0/+1
| | | | | | | We have to delete the block manually or it leaks. That triggers failures in -fsanitize=leak bots (unsurprisingly), which should be fixed by this patch. llvm-svn: 293347
* [InstCombine] move icmp transforms that might be recognized as min/max and ↵Sanjay Patel2017-01-271-10/+21
| | | | | | | | | | | | | | | | | | | | | | inf-loop (PR31751) This is a minimal patch to avoid the infinite loop in: https://llvm.org/bugs/show_bug.cgi?id=31751 But the general problem is bigger: we're not canonicalizing all of the min/max forms reported by value tracking's matchSelectPattern(), and we don't define min/max consistently. Some code uses matchSelectPattern(), other code uses matchers like m_Umax, and others have their own inline definitions which may be subtly different from any of the above. The reason that the test cases in this patch need a cast op to trigger is because we don't (yet) canonicalize all min/max forms based on matchSelectPattern() in canonicalizeMinMaxWithConstant(), but we do make min/max+cast transforms based on matchSelectPattern() in visitSelectInst(). The location of the icmp transforms that trigger the inf-loop seems arbitrary at best, so I'm moving those behind the min/max fence in visitICmpInst() as the quick fix. llvm-svn: 293345
* Analysis: Add appropriate const qualification to functions in ↵Peter Collingbourne2017-01-271-5/+6
| | | | | | TypeMetadataUtils.cpp. NFC. llvm-svn: 293341
* [libFuzzer] make shmem more robust in the presence of signalsKostya Serebryany2017-01-272-3/+17
| | | | llvm-svn: 293339
* [AMDGPU][mc] Fix memory corruption uncovered by AddressSanitizer during ↵Artem Tamazov2017-01-272-2/+4
| | | | | | | | | | coverage/smoke Gfx7/8 testing. Coverage/smoke Gfx7/8 tests were committed r292922 but then reverted by r292974 due to AddressSanitizer failure, which is fixed by this patch. Tests to be re-committed soon. llvm-svn: 293338
* GlobalISel: set correct regclass for LOAD_STACK_GUARD.Tim Northover2017-01-271-0/+2
| | | | | | | Since it's not actually a generic MI, its register operands need a RegClass, which is conveniently the target's pointer RegClass. llvm-svn: 293335
* GlobalISel: mark incoming landing-pad registers as live.Tim Northover2017-01-271-0/+2
| | | | | | Should fix machine verifier failures. llvm-svn: 293334
* [Hexagon] Remove unused variable (and silence a warning)Krzysztof Parzyszek2017-01-271-4/+2
| | | | llvm-svn: 293331
* Fix ASAN failure in cxa_demangleMehdi Amini2017-01-271-1/+2
| | | | | | Found with ASAN + libFuzzer by Kostya Serebryany <kcc@google.com> llvm-svn: 293330
* Global DCE performance improvementMehdi Amini2017-01-271-60/+83
| | | | | | | | | | | | | | | | | | | Change the original algorithm so that it scales better when meeting very large bitcode where every instruction does not implies a global. The target query is "how to you get all the globals referenced by another global"? Before this patch, it was doing this by walking the body (or the initializer) and collecting the references. What this patch is doing, it precomputing the answer to this query for the whole module by walking the use-list of every global instead. Patch by: Serge Guelton <serge.guelton@telecom-bretagne.eu> Differential Revision: https://reviews.llvm.org/D28549 llvm-svn: 293328
* [PGO] add debug option to view raw count after prof use annotationXinliang David Li2017-01-271-1/+59
| | | | | | Differential Revision: https://reviews.llvm.org/D29045 llvm-svn: 293325
* ScheduleDAGInstrs: Do not try to toggle kill flags on debug usesMatthias Braun2017-01-271-0/+3
| | | | | | | | Preparation for upcoming changes. No testcase as none of the public targets bundles early enough and has a post machine scheduler enabled at the same time. The error is also easily catched by asserts. llvm-svn: 293324
* ScheduleDAGInstrs: Cleanup toggleKillFlag(); NFCMatthias Braun2017-01-271-11/+10
| | | | llvm-svn: 293323
* ScheduleDAGInstrs: Cleanup; NFCMatthias Braun2017-01-271-69/+45
| | | | | | Comment, doxygen and a bit of whitespace cleanup. llvm-svn: 293322
* AMDGPU/SI: Move some ISel helpers into utils so they can be shared with GISelTom Stellard2017-01-274-24/+44
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D29068 llvm-svn: 293321
* [AMDGPU] Grab MCSubtargetInfo from TargetMachine instead of constructing itKonstantin Zhuravlyov2017-01-271-6/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D29224 llvm-svn: 293318
* [X86] Adding FFREEP instruction.Chris Ray2017-01-271-0/+3
| | | | | | | | | | | | | | Summary: Small change to get the FREEP instruction to decode properly. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29193 llvm-svn: 293314
* NFC: Add debug tracing for more cases where loop unrolling fails.Anna Thomas2017-01-271-2/+8
| | | | llvm-svn: 293313
* AMDGPU: Enable FeatureFlatForGlobal on Volcanic IslandsMatt Arsenault2017-01-273-11/+9
| | | | | | | | | | | Accomplishes what r292982 was supposed to, which ended up only really making the necessary test changes. This should be applied to the 4.0 branch. Patch by Vedran Miletić <vedran@miletic.net> llvm-svn: 293310
* NVPTX: Make NVPTXInferAddressSpaces preserve CFGMatt Arsenault2017-01-271-0/+4
| | | | llvm-svn: 293308
* [CodeGenPrep]No negative cost in the ExtLd promotionJun Bum Lim2017-01-271-1/+4
| | | | | | | | | | | | | | Summary: This change prevent the signed value of cost from being negative as the value is passed as an unsigned argument. Reviewers: mcrosier, jmolloy, qcolombet, javed.absar Reviewed By: mcrosier, qcolombet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28871 llvm-svn: 293307
* [AMDGPU] Turn AMDGPUUnifyMetadata back into module passStanislav Mekhanoshin2017-01-273-17/+5
| | | | | | | | | With the adjustPassManager interface that is now possible to use custom early module passes. Differential Revision: https://reviews.llvm.org/D29189 llvm-svn: 293300
* Fix BasicAA incorrect assumption on GEPMehdi Amini2017-01-271-5/+5
| | | | | | | | | | | | | | This is fixing pr31761: BasicAA is deducing NoAlias on the result of the GEP if the base pointer is itself NoAlias. This is possible only if the NoAlias on the base pointer is deduced with a non-sized query: this should guarantee that the pointers are belonging to different memory allocation and that the GEP can't legally jump from one to another. Differential Revision: https://reviews.llvm.org/D29216 llvm-svn: 293293
* Avoid using unspecified ordering in ↵Ivan Krasin2017-01-271-33/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MetadataLoader::MetadataLoaderImpl::parseOneMetadata. Summary: MetadataLoader::MetadataLoaderImpl::parseOneMetadata uses the following construct in a number of places: ``` MetadataList.assignValue(<...>, NextMetadataNo++); ``` There, NextMetadataNo gets incremented, and since the order of arguments evaluation is not specified, that can happen before or after other arguments are evaluated. In a few cases the other arguments indirectly use NextMetadataNo. For instance, it's ``` MetadataList.assignValue( GET_OR_DISTINCT(DIModule, (Context, getMDOrNull(Record[1]), getMDString(Record[2]), getMDString(Record[3]), getMDString(Record[4]), getMDString(Record[5]))), NextMetadataNo++); ``` getMDOrNull calls getMD that uses NextMetadataNo: ``` MetadataList.getMetadataFwdRef(NextMetadataNo); ``` Therefore, the order of evaluation becomes important. That caused a very subtle LLD crash that only happens if compiled with GCC or if LLD is built with LTO. In the case if LLD is compiled with Clang and regular linking mode, everything worked as intended. This change extracts incrementing of NextMetadataNo outside of the arguments list to guarantee the correct order of evaluation. For the record, this has taken 3 days to track to the origin. It all started with a ThinLTO bot in Chrome not being able to link a target if debug info is enabled. Reviewers: pcc, mehdi_amini Reviewed By: mehdi_amini Subscribers: aprantl, llvm-commits Differential Revision: https://reviews.llvm.org/D29204 llvm-svn: 293291
* [mips] Recommit: "N64 static relocation model support"Simon Dardis2017-01-2712-117/+241
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes one change to GOT handling and two changes to N64's relocation model handling. Furthermore, the jumptable encodings have been corrected for static N64. Big GOT handling is now done via a new SDNode MipsGotHi - this node is unconditionally lowered to an lui instruction. The first change to N64's relocation handling is the lifting of the restriction that N64 always uses PIC. Now it is possible to target static environments. The second change adds support for 64 bit symbols and enables them by default. Previously N64 had patterns for sym32 mode only. In this mode all symbols are assumed to have 32 bit addresses. sym32 mode support is selectable with attribute 'sym32'. A follow on patch for clang will add the necessary frontend parameter. This partially resolves PR/23485. Thanks to Brooks Davis for reporting the issue! This version corrects a "Conditional jump or move depends on uninitialised value(s)" error detected by valgrind present in the original commit. Reviewers: dsanders, seanbruno, zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D23652 llvm-svn: 293279
* [SLP] Refactoring of horizontal reduction analysis, NFC.Alexey Bataev2017-01-271-24/+25
| | | | | | | | | | | Some checks in SLP horizontal reduction analysis function are performed several times, though it is enough to perform these checks only once during an initial attempt at adding candidate for the reduction instruction/reduced value. Differential Revision: https://reviews.llvm.org/D29175 llvm-svn: 293274
* [LICM] When we are recomputing the alias sets for a subloop, we cannotChandler Carruth2017-01-271-3/+0
| | | | | | | | | | | | | | | | | | | | | | | skip sub-subloops. The logic to skip subloops dated from when this code was shared with the cached case. Once it was factored out to only run in the case of recomputed subloops it became a dangerous bug. If a subsubloop contained an interfering instruction it would be silently skipped from the alias sets for LICM. With the old pass manager this was extremely hard to trigger as it would require failing to visit these subloops with the LICM pass but then visiting the outer loop somehow. I've not yet contrived any test case that actually manages to trigger this. But with the new pass manager we don't do the cross-loop caching hack that the old PM does and so we recompute alias set information from first principles. While this seems much cleaner and simpler it exposed this bug and would subtly miscompile code due to failing to correctly model the aliasing constraints of deeply nested loops. llvm-svn: 293273
* [DAGTypeLegalizer] Handle SIGN/ZERO_EXTEND in WidenVecRes_Convert().Jonas Paulsson2017-01-271-0/+9
| | | | | | | | | | | | | In case of a SIGN/ZERO_EXTEND of an incomplete vector type (using only a partial number of available vector elements), WidenVecRes_Convert() used to resort to scalarization. This patch adds a handling of the (common) case where an input vector can be found of same width as the widened result vector, by converting the node to SIGN/ZERO_EXTEND_VECTOR_INREG. Review: Eli Friedman llvm-svn: 293268
* Fix unused variable warning.Richard Trieu2017-01-271-0/+1
| | | | llvm-svn: 293260
* ARM: fix vectorized division on WoASaleem Abdulrasool2017-01-271-2/+2
| | | | | | | | | | | | | | The Windows on ARM target uses custom division for normal division as the backend needs to insert division-by-zero checks. However, it is designed to only handle non-vectorized division. ARM has custom lowering for vectorized division as that can avoid loading registers with the values and invoke a division routine for each one, preferring to lower using NEON instructions. Fall back to the custom lowering for the NEON instructions if we encounter a vectorized division. Resolves PR31778! llvm-svn: 293259
* NewGVN: Add basic dead and redundant store eliminationDaniel Berlin2017-01-271-29/+114
| | | | | | | | | | | | | | | | | | | | Summary: This adds basic dead and redundant store elimination to NewGVN. Unlike our current DSE, it will happily do cross-block DSE if it meets our requirements. We get a bunch of DSE's simple.ll cases, and some stuff it doesn't. Unlike DSE, however, we only try to eliminate stores of the same value to the same memory location, not just general stores to the same memory location. Reviewers: davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29149 llvm-svn: 293258
* NVPTXCodeGen: Add IPO to libdeps, since r293189.NAKAMURA Takumi2017-01-271-1/+1
| | | | llvm-svn: 293256
* [APFloat] Reduce some dispatch boilerplates. NFC.Tim Shen2017-01-271-5/+12
| | | | | | | | | | | | Summary: This is an attempt to reduce the verbose manual dispatching code in APFloat. This doesn't handle multiple dispatch on single discriminator (e.g. APFloat::add(const APFloat&)), nor handles multiple dispatch on multiple discriminators (e.g. APFloat::convert()). Reviewers: hfinkel, echristo, jlebar Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D29161 llvm-svn: 293255
* [NVPTX] [InstCombine] Add llvm_unreachable to appease MSVC.Justin Lebar2017-01-271-0/+1
| | | | llvm-svn: 293253
* [NVPTX] Fix use-after-stack-free bug in InstCombineCalls.Justin Lebar2017-01-271-1/+1
| | | | | | Introduced in r293244. llvm-svn: 293251
* Constant fold switch inst when looking for trivial conditions to unswitch on.Xin Tong2017-01-271-2/+10
| | | | | | | | | | | | Summary: Constant fold switch inst when looking for trivial conditions to unswitch on. Reviewers: sanjoy, chenli, hfinkel, efriedma Subscribers: llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D29037 llvm-svn: 293250
* [PM] Port LoopLoadElimination to the new pass manager and wire it intoChandler Carruth2017-01-273-28/+65
| | | | | | | | | | | the main pipeline. This is a very straight forward port. Nothing weird or surprising. This brings the number of missing passes from the new PM's pipeline down to three. llvm-svn: 293249
* [ARM][LegalizerInfo] Specify the type of the opcode.Quentin Colombet2017-01-271-1/+1
| | | | | | | This is to fix the win7 bot that does not seem to be very good at infering the type when it gets used in an initiliazer list. llvm-svn: 293248
* [AArch64][LegalizerInfo] Specify the type of the opcode.Quentin Colombet2017-01-271-6/+6
| | | | | | | This is an attempt to fix the win7 bot that does not seem to be very good at infering the type when it gets used in an initiliazer list. llvm-svn: 293246
* Revert "[AArch64][LegalizerInfo] Specify the type of the initialization list."Quentin Colombet2017-01-271-76/+70
| | | | | | | | This reverts commit r293238. Even with that the win7 bot is still failing: http://lab.llvm.org:8011/builders/lld-x86_64-win7/builds/3862 llvm-svn: 293245
* [NVPTX] Upgrade NVVM intrinsics in InstCombineCalls.Justin Lebar2017-01-271-0/+250
| | | | | | | | | | | | | | | | | | | | | | | | Summary: There are many NVVM intrinsics that we can't entirely get rid of, but that nonetheless often correspond to target-generic LLVM intrinsics. For example, if flush denormals to zero (ftz) is enabled, we can convert @llvm.nvvm.ceil.ftz.f to @llvm.ceil.f32. On the other hand, if ftz is disabled, we can't do this, because @llvm.ceil.f32 will be lowered to a non-ftz PTX instruction. In this case, we can, however, simplify the non-ftz nvvm ceil intrinsic, @llvm.nvvm.ceil.f, to @llvm.ceil.f32. These transformations are particularly useful because they let us constant fold instructions that appear in libdevice, the bitcode library that ships with CUDA and essentially functions as its libm. Reviewers: tra Subscribers: hfinkel, majnemer, llvm-commits Differential Revision: https://reviews.llvm.org/D28794 llvm-svn: 293244
* [ValueTracking] Add comment that CannotBeOrderedLessThanZero does the wrong ↵Justin Lebar2017-01-271-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | thing for powi. Summary: CannotBeOrderedLessThanZero(powi(x, exp)) returns true if CannotBeOrderedLessThanZero(x). But powi(-0, exp) is negative if exp is odd, so we actually want to return SignBitMustBeZero(x). Except that also isn't right, because we want to return true if x is NaN, even if x has a negative sign bit. What we really need in order to fix this is a consistent approach in this function to handling the sign bit of NaNs. Without this it's very difficult to say what the correct behavior here is. Reviewers: hfinkel, efriedma, sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28927 llvm-svn: 293243
* [LangRef] Make @llvm.sqrt(x) return undef, rather than have UB, for negative x.Justin Lebar2017-01-271-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Some frontends emit a speculate-and-select idiom for sqrt, wherein they compute sqrt(x), check if x is negative, and select NaN if it is: %cmp = fcmp olt double %a, -0.000000e+00 %sqrt = call double @llvm.sqrt.f64(double %a) %ret = select i1 %cmp, double 0x7FF8000000000000, double %sqrt This is technically UB as the LangRef is written today if %a is ever less than -0. But emitting code that's compliant with the current definition of sqrt would require a branch, which would then prevent us from matching this idiom in SelectionDAG (which we do today -- ISD::FSQRT has defined behavior on negative inputs), because SelectionDAG looks at one BB at a time. Nothing in LLVM takes advantage of this undefined behavior, as far as we can tell, and the fact that llvm.sqrt has UB dates from its initial addition to the LangRef. Reviewers: arsenm, mehdi_amini, hfinkel Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D28797 llvm-svn: 293242
* [PM] Flesh out almost all of the late loop passes.Chandler Carruth2017-01-271-9/+37
| | | | | | | | | | | | | | | | | | | | | | | | | With this the per-module pass pipeline is *extremely* close to the legacy PM. The missing pieces are: - PruneEH (or some equivalent) - ArgumentPromotion - LoopLoadElimination - LoopUnswitch I'm going to work through those in essentially that order but this seems like a worthwhile incremental step toward the end state. One difference in what I have here from the legacy PM is that I've consolidated some of the per-function passes at the very end of the pipeline into the main optimization function pipeline. The intervening passes are *really* uninteresting and so this seems very likely to have any effect other than minor improvement to locality. Note that there are still some failures in the test suite, but the compiler doesn't crash or assert. Differential Revision: https://reviews.llvm.org/D29114 llvm-svn: 293241
* [libFuzzer] simplify the value profiling callback further: don't use (idx ↵Kostya Serebryany2017-01-273-10/+11
| | | | | | MOD prime) on the hot path where it is useless anyway llvm-svn: 293239
* [AArch64][LegalizerInfo] Specify the type of the initialization list.Quentin Colombet2017-01-271-70/+76
| | | | | | | This is an attempt to fix the win7 bot that does not seem to be very good at infering the type. llvm-svn: 293238
* [libFuzzer] make sure (again) that __builtin_popcountl is compiled into popcntKostya Serebryany2017-01-271-0/+8
| | | | llvm-svn: 293237
* [libFuzzer] simplify the value profile code and disable asan/msan on itKostya Serebryany2017-01-273-6/+19
| | | | llvm-svn: 293236
* NFC: Rename PDB_ReaderType::Raw to Native for consistency with the ↵Adrian McCarthy2017-01-271-2/+2
| | | | | | NativeSession rename. llvm-svn: 293235
* [ARM] Fix some Clang-tidy modernize and Include What You Use warnings; other ↵Eugene Zelenko2017-01-2613-131/+244
| | | | | | minor fixes (NFC). llvm-svn: 293229
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