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* MC] Provide an MCTargetOptions to implementors of MCAsmBackendCtorTy, NFCJoel Jones2016-07-2521-47/+99
| | | | | | | | | | | | | | | Some targets, notably AArch64 for ILP32, have different relocation encodings based upon the ABI. This is an enabling change, so a future patch can use the ABIName from MCTargetOptions to chose which relocations to use. Tested using check-llvm. The corresponding change to clang is in: http://reviews.llvm.org/D16538 Patch by: Joel Jones Differential Revision: https://reviews.llvm.org/D16213 llvm-svn: 276654
* StringSwitch cannot be copied or moved.Jordan Rose2016-07-251-7/+7
| | | | | | | | | | | | ...but most importantly, it cannot be used well with 'auto', because the inferred type is StringSwitch rather than the result type. This is a problem because StringSwitch stores addresses of temporary values rather than copying or moving the value into its own storage. Changing this uncovered the bug in PassBuilder, also in this patch. Clang doesn't seem to have any occurrences of the issue. llvm-svn: 276652
* AVX-512: Fixed [US]INT_TO_FP selection for i1 vectors.Elena Demikhovsky2016-07-251-0/+21
| | | | | | | | It failed with assertion before this patch. Differential Revision: https://reviews.llvm.org/D22735 llvm-svn: 276648
* [Hexagon] Add target feature to generate long callsKrzysztof Parzyszek2016-07-256-29/+73
| | | | llvm-svn: 276638
* [ARM] Improve longMAC codegen testSam Parker2016-07-252-1/+6
| | | | | | | | Added thumb targets and dataflow checks to the longMAC test. Differential Revision: https://reviews.llvm.org/D22684 llvm-svn: 276629
* [mips] Optimize materialization of i64 constantsSimon Dardis2016-07-255-13/+49
| | | | | | | | | | | | | | | | | Avoid MipsAnalyzeImmediate usage if the constant fits in an 32-bit integer. This allows us to generate the same instructions for the materialization of the same constants regardless the width of their type. Patch by: Vasileios Kalintiris Contributions by: Simon Dardis Reviewers: Daniel Sanders Differential Review: https://reviews.llvm.org/D21689 llvm-svn: 276628
* [ARM] Small refactor of Thumb2 SMLA instsSam Parker2016-07-251-12/+8
| | | | | | | | | Follow up to r276624. Changes bits 22-20 to be parameters to instruction class. Differential Revision: https://reviews.llvm.org/D22562 llvm-svn: 276626
* [ARM] Enable ISel of SMMLS for ARM and Thumb2Sam Parker2016-07-252-5/+34
| | | | | | | | Use ISelDAGToDAG to recognise the SMMLS instruction pattern. Differential Revision: https://reviews.llvm.org/D22562 llvm-svn: 276624
* [AVX512] Add load folding support for the unmasked forms of the FMA ↵Craig Topper2016-07-251-0/+144
| | | | | | instructions. llvm-svn: 276615
* [AVX512] Add some additional patterns so that we can fold broadcast loads in ↵Craig Topper2016-07-251-45/+76
| | | | | | the first argument of an FMADD/FMSUB/FNMADD/FNMSUB/FMADDSUB/FMSUBADD node. Also add patterns to support all combinations of the broadcast input and the preserved input for masked versions. llvm-svn: 276614
* [AVX512] Cleanup FMA operand order in patterns to match the VEX versions and ↵Craig Topper2016-07-251-19/+19
| | | | | | to really be 213, 231, and 132. llvm-svn: 276613
* Cleanup : Reformat PartialInliner.cpp to have current LLVM style conventionsSean Silva2016-07-251-71/+74
| | | | | | | | | | Modify the variable names and code style to be that of modern LLVM. Patch by River Riddle! Differential Revision: https://reviews.llvm.org/D22743 llvm-svn: 276610
* Fix : Partial Inliner requires AssumptionCacheTrackerSean Silva2016-07-251-35/+58
| | | | | | | | | | | The public InlineFunction utility assumes that the passed in InlineFunctionInfo has a valid AssumptionCacheTracker. Patch by River Riddle! Differential Revision: https://reviews.llvm.org/D22706 llvm-svn: 276609
* [InstSimplify] Fold trunc([zs]ext(%V)) -> %VDavid Majnemer2016-07-251-1/+7
| | | | | | Truncates can completely cancel out a zext or sext instruction. llvm-svn: 276604
* [GVNHoist] Merge metadata on hoisted instructions less conservativelyDavid Majnemer2016-07-251-7/+17
| | | | | | | We can combine metadata from multiple instructions intelligently for certain metadata nodes. llvm-svn: 276602
* [GVNHoist] Properly merge alignments when hoistingDavid Majnemer2016-07-251-4/+14
| | | | | | | | | If we two loads of two different alignments, we must use the minimum of the two alignments when hoisting. Same deal for stores. For allocas, use the maximum of the two allocas. llvm-svn: 276601
* [Utils] Simplify combineMetadataDavid Majnemer2016-07-251-3/+3
| | | | | | Use a range-based for loop, no functional change is intended. llvm-svn: 276600
* Untabify.NAKAMURA Takumi2016-07-251-1/+1
| | | | llvm-svn: 276597
* Trailing whitespace.NAKAMURA Takumi2016-07-251-4/+4
| | | | llvm-svn: 276596
* [CommandLine] Use Process::GetEnv instead of _wgetenvDavid Majnemer2016-07-241-21/+4
| | | | | | | | | | Process::GetEnv does the right thing across our platforms. CommandLine.cpp had, more or less, the same logic. Let's remove the duplication. No functional change is intended. llvm-svn: 276572
* [X86] Add 'FeatureSlowSHLD' to cpu 'bdver4'Simon Pilgrim2016-07-241-0/+1
| | | | | | As with all AMD CPUs, excavator has poor SHLD/SHRD performance. Also added bdver3 to the test as it was missing. llvm-svn: 276569
* [X86] Make the FMA3 instruction names consistent between VEX and EVEX ↵Craig Topper2016-07-244-407/+383
| | | | | | | | encoded versions. This places the 132/213/231 form number in front of the SS/SD/PS/PD. Move the Y for 256-bit versions to be after the PS/PD. Change the AVX512 scalar forms to include a Z in the their name. This new format should be consistent with the general naming of instructions. llvm-svn: 276559
* [X86] Replace CodeGenOnly VPSRAVW/D/Q_Int instructions with patterns since ↵Craig Topper2016-07-244-8/+87
| | | | | | the operand types exactly match the normal VPSRAVW/D/Q instructions. llvm-svn: 276555
* [Loop Vectorizer] Handling loops FP induction variables.Elena Demikhovsky2016-07-243-45/+210
| | | | | | | | | | | | | | | | Allowed loop vectorization with secondary FP IVs. Like this: float *A; float x = init; for (int i=0; i < N; ++i) { A[i] = x; x -= fp_inc; } The auto-vectorization is possible when the induction binary operator is "fast" or the function has "unsafe" attribute. Differential Revision: https://reviews.llvm.org/D21330 llvm-svn: 276554
* [MSSA] Make EXPENSIVE_CHECKS check more.George Burgess IV2016-07-241-13/+11
| | | | | | | | checkClobberSanity will now be run for all results of `ClobberWalk`, instead of just the crazy phi-optimized ones. This can help us catch cases where our cache is being wonky. llvm-svn: 276553
* [MSSA] Remove useless assert. NFC.George Burgess IV2016-07-241-1/+0
| | | | | | | liveOnEntry is always a MemoryDef; asserting that a MemoryPhi isn't liveOnEntry, while correct, isn't very helpful. :) llvm-svn: 276542
* [X86] Fix typo in comment.Craig Topper2016-07-231-1/+1
| | | | llvm-svn: 276528
* [InstCombine] allow icmp (bit-manipulation-intrinsic(), C) folds for vectorsSanjay Patel2016-07-232-15/+17
| | | | llvm-svn: 276523
* Fix a GCC error due to this member name also being a type name. ThisChandler Carruth2016-07-231-3/+3
| | | | | | | should fix the build with GCC 4.9 at least. Not sure if this is the right name or fix, but I've followed up on the original commit. llvm-svn: 276522
* [AVX512] Implement commuting support for EVEX encoded FMA3 instructions.Craig Topper2016-07-231-218/+186
| | | | llvm-svn: 276521
* [X86] Make one of the FMA3 commuting methods static. Remove a call to isFMA3 ↵Craig Topper2016-07-232-212/+212
| | | | | | just to get the IsIntrisic flag, instead get it during the first call and pass it along. NFC llvm-svn: 276520
* [X86] Fix switch statement indentation per coding standards.Craig Topper2016-07-231-136/+136
| | | | llvm-svn: 276519
* AMDGPU: Delete dead codeMatt Arsenault2016-07-232-97/+0
| | | | | | This has been dead since r269479 llvm-svn: 276518
* [Profile] Use explicit flag to enable IR PGOXinliang David Li2016-07-231-8/+13
| | | | | | | | Patch by Jake VanAdrighem Differential Revision: http://reviews.llvm.org/D22607 llvm-svn: 276516
* Avoid using a raw AssumptionCacheTracker in various inliner functions.Sean Silva2016-07-235-62/+98
| | | | | | | | | | This unblocks the new PM part of River's patch in https://reviews.llvm.org/D22706 Conveniently, this same change was needed for D21921 and so these changes are just spun out from there. llvm-svn: 276515
* [LoopUnrollAnalyzer] Handle out of bounds accesses in visitLoadDavid Majnemer2016-07-231-4/+10
| | | | | | | | | | | | While we handed loads past the end of an array, we didn't handle loads _before_ the array. This fixes PR28062. N.B. While the bug in the code is obvious, I am struggling to craft a test case which is reasonable in size. llvm-svn: 276510
* [SCEV] Make isImpliedCondOperandsViaRanges smarterSanjoy Das2016-07-231-11/+1
| | | | | | | | | | | | This change lets us prove things like "{X,+,10} s< 5000" implies "{X+7,+,10} does not sign overflow" It does this by replacing replacing getConstantDifference by computeConstantDifference (which is smarter) in isImpliedCondOperandsViaRanges. llvm-svn: 276505
* [SCEV] Change the interface of computeConstantDifference; NFCSanjoy Das2016-07-231-24/+17
| | | | | | | This is in preparation of s/getConstantDifference/computeConstantDifference/ in a later change. llvm-svn: 276503
* [InstCombine] move udiv+cmp fold over with other BinOp+cmp folds; NFCISanjay Patel2016-07-231-9/+8
| | | | llvm-svn: 276502
* Revert "[AMDGPU] Emit read-only data to .rodata for hsa"Tom Stellard2016-07-221-2/+1
| | | | | | | | | | | | This reverts commit r276298. Data stored in .rodata can have a negative offset from .text, but we don't support negative values in relocations yet. This caused a regression in one of the amp conformance tests: 5_Data_Cont/5_2_a_v/5_2_3_m/Assignment/Test.02.01 llvm-svn: 276498
* [LoopDataPrefetch] Fix unused variable in release buildAdam Nemet2016-07-221-2/+1
| | | | llvm-svn: 276491
* [LoopDataPrefetch] Include hotness of region in opt remarkAdam Nemet2016-07-221-4/+6
| | | | llvm-svn: 276488
* [LoopDataPrefetch] Sort headersAdam Nemet2016-07-221-1/+1
| | | | llvm-svn: 276487
* [CFLAA] Add more offset-sensitivity tracking.George Burgess IV2016-07-225-43/+162
| | | | | | | | | | | | | | | | | | | This patch teaches FunctionInfo about offsets. Like the last patch, this one doesn't introduce any visible functionality change (the core algorithm knows nothing about offsets; they're just plumbed through). Tests will come when we start acting differently because of the offsets. Patch by Jia Chen. (N.B. I made a tiny change to Jia's patch to avoid warnings by GCC: I put DenseMapInfo specializations in the `llvm` namespace. Only realized that those appeared when compiling locally. :) ) Differential Revision: https://reviews.llvm.org/D22634 llvm-svn: 276486
* GlobalISel: allow multiple types on MachineInstrs.Tim Northover2016-07-223-20/+42
| | | | llvm-svn: 276481
* Unpoison stack before resume instructionVitaly Buka2016-07-221-0/+6
| | | | | | | | | | | | | | | | | | | Summary: Clang inserts cleanup code before resume similar way as before return instruction. This makes asan poison local variables causing false use-after-scope reports. __asan_handle_no_return does not help here as it was executed before llvm.lifetime.end inserted into resume block. To avoid false report we need to unpoison stack for resume same way as for return. PR27453 Reviewers: kcc, eugenis Differential Revision: https://reviews.llvm.org/D22661 llvm-svn: 276480
* Add flag to PassManagerBuilder to disable GVN Hoist Pass.Alina Sbirlea2016-07-221-1/+6
| | | | | | | | | | | | | | Summary: Adding a flag to diable GVN Hoisting by default. Note: The GVN Hoist Pass causes some Halide tests to hang. Halide will disable the pass while investigating. Reviewers: llvm-commits, chandlerc, spop, dberlin Subscribers: mehdi_amini Differential Revision: https://reviews.llvm.org/D22639 llvm-svn: 276479
* [SLPVectorizer] Vectorize reverse-order loads in horizontal reductionsMichael Kuperstein2016-07-221-16/+53
| | | | | | | | | | | | | | | | | | When vectorizing a tree rooted at a store bundle, we currently try to sort the stores before building the tree, so that the stores can be vectorized. For other trees, the order of the root bundle - which determines the order of all other bundles - is arbitrary. That is bad, since if a leaf bundle of consecutive loads happens to appear in the wrong order, we will not vectorize it. This is partially mitigated when the root is a binary operator, by trying to build a "reversed" tree when that's considered profitable. This patch extends the workaround we have for binops to trees rooted in a horizontal reduction. This fixes PR28474. Differential Revision: https://reviews.llvm.org/D22554 llvm-svn: 276477
* Add invariant start call creation in IRBuilder.NFCAnna Thomas2016-07-221-0/+20
| | | | | | Differential Revision: https://reviews.llvm.org/D22700 llvm-svn: 276471
* Use RValue refs in APInt add/sub methods.Pete Cooper2016-07-221-38/+16
| | | | | | | | | | | | | This adds versions of operator + and - which are optimized for the LHS/RHS of the operator being RValue's. When an RValue is available, we can use its storage space instead of allocating new space. On code such as ConstantRange which makes heavy use of APInt's over 64-bits in size, this results in significant numbers of saved allocations. Thanks to David Blaikie for all the review and most of the code here. llvm-svn: 276470
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