| Commit message (Collapse) | Author | Age | Files | Lines |
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landing pad as its successor.
SjLj exception handling jumps to the correct landing pad via a switch statement
that's generated right before code-gen. Loosen the constraint in the machine
instruction verifier to allow for this. Note, this isn't the most rigorous check
since we cannot determine where that switch statement came from. But it's
marginally better than turning this check off when SjLj exceptions are used.
<rdar://problem/9187612>
llvm-svn: 130881
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llvm-svn: 130880
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edge in some cases.
Original message:
Teach MachineCSE how to do simple cross-block CSE involving physregs. This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 .
llvm-svn: 130877
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llvm-svn: 130876
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llvm-svn: 130869
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llvm-svn: 130867
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allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 .
llvm-svn: 130862
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cross-class joins.
llvm-svn: 130857
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llvm-svn: 130854
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llvm-svn: 130850
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instruction that restores the clobbered $gp.
llvm-svn: 130847
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it is both inefficient and unexpected by dwarfdump. Change to
a DW_FORM_data4.
While in here, change the predicate name to reflect that the position
is not really absolute (it is an offset), just that the linker needs a
relocation.
llvm-svn: 130846
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Physreg joining is still on by default, but I will turn it off shortly.
llvm-svn: 130844
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fixes dwarf-die2.c test case from gcc test suite.
llvm-svn: 130842
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but according to my super-optimizer there are only two missed simplifications
of -instsimplify kind when compiling bzip2, and this is one of them. It amuses
me to have bzip2 be perfectly optimized as far as instsimplify goes!
llvm-svn: 130840
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frontend, if applicable.
llvm-svn: 130835
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This adds functionality to remove size/zero extension during indvars
without generating a canonical IV and rewriting all IV users. It's
disabled by default so should have no effect on codegen. Work in progress.
llvm-svn: 130829
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coalescing.
llvm-svn: 130814
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sub-registers.
LiveVariables doesn't understand that clobbering D0 and D1 completely overwrites
Q0, so if Q0 is live-in to a function, its live range will extend beyond a
function call that only clobbers D0 and D1. This shows up in the
ARM/2009-11-01-NeonMoves test case.
LiveVariables should probably implement the much stricter rules for physreg
liveness that RAFast imposes - a physreg is killed by the first use of any
alias.
llvm-svn: 130801
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Only create a canonical IV for backedge taken count if it will
actually be used by LinearFunctionTestReplace. And some related
cleanup, preparing to reduce dependence on canonical IVs.
No significant effect on x86 or arm in the test-suite.
llvm-svn: 130799
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DW_AT_MIPS_linkage_name. This helps gdb and fixes var-path-expr.exp regression reported by gdb testsuite.
llvm-svn: 130794
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(and should thus never be done).
- Should fix a crash on win32.
llvm-svn: 130793
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<rdar://problem/8460511>
llvm-svn: 130791
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Register coalescing can sometimes create live ranges that end in the middle of a
basic block without any killing instruction. When SplitKit detects this, it will
repair the live range by shrinking it to its uses.
Live range splitting also needs to know about this. When the range shrinks so
much that it becomes allocatable, live range splitting fails because it can't
find a good split point. It is paranoid about making progress, so an allocatable
range is considered an error.
The coalescer should really not be creating these bad live ranges. They appear
when coalescing dead copies.
llvm-svn: 130787
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max(a,b) >= a -> true. According to my super-optimizer, these are
by far the most common simplifications (of the -instsimplify kind)
that occur in the testsuite and aren't caught by -std-compile-opts.
llvm-svn: 130780
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llvm-svn: 130774
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llvm-svn: 130766
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it's possible.
llvm-svn: 130764
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llvm-svn: 130763
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does it now) then use them directly. This saves one scan of entire module, to collect debug info, which in turns saves few machine cycles at compile time.
llvm-svn: 130759
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llvm-svn: 130756
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llvm-svn: 130755
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llvm-svn: 130749
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string template.
Fixes rdar://8493866
llvm-svn: 130747
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model constants which can be added to base registers via add-immediate
instructions which don't require an additional register to materialize
the immediate.
llvm-svn: 130743
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pointer type for vector indices. Make the vector unrolling code respect that.
llvm-svn: 130733
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Instead, just use whatever location info first non-phi instruction has.
llvm-svn: 130729
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llvm-svn: 130718
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llvm-svn: 130716
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llvm-svn: 130715
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Def operands may also have an <undef> flag, but that just means that a
sub-register redef doesn't actually read the super-register. For physical
registers, it has no meaning.
llvm-svn: 130714
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a vector compare, generate a vector result rather than i1 (and crashing).
llvm-svn: 130706
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llvm-svn: 130705
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This works around a limitation in gdb which is reported by following inherit.exp test failures from gdb testsuite.
gdb.cp/inherit.exp: print g_vB.vB::vb
gdb.cp/inherit.exp: print g_vB.vB::vx
gdb.cp/inherit.exp: print g_vC.vC::vc
gdb.cp/inherit.exp: print g_vC.vC::vx
gdb.cp/inherit.exp: print g_vD.vB::vb
...
llvm-svn: 130702
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This automagically provides a transform noticed by my super-optimizer
as occurring quite often: "rem x, (select cond, x, 1)" -> 0.
llvm-svn: 130694
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llvm-svn: 130693
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llvm-svn: 130692
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llvm-svn: 130691
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take some time.
llvm-svn: 130690
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When an interfering live range ends at a dead slot index between two
instructions, make sure that the inserted copy instruction gets a slot index
after the dead ones. This makes it possible to avoid the interference.
Ideally, there shouldn't be interference ending at a deleted instruction, but
physical register coalescing can sometimes do that to sub-registers.
This fixes PR9823.
llvm-svn: 130687
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