summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* Use report_fatal_error instead of unreachable for -fast-isel-abortMehdi Amini2015-03-041-3/+3
| | | | | | | Suggestion by Andrea Di Biagio From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 231201
* unique_ptrify ValID::ConstantStructEltsDavid Blaikie2015-03-042-11/+9
| | | | llvm-svn: 231200
* LLParser: Avoid copying ValIDs, the copy ctor is deprecated in C++11 due to ↵David Blaikie2015-03-041-1/+6
| | | | | | the presence of a user-declared dtor llvm-svn: 231199
* Use the vanilla func_end symbol for .size.Rafael Espindola2015-03-041-7/+4
| | | | | | No need to create yet another temp symbol. llvm-svn: 231198
* Remove MCStreamer include which isn't used here. NFCPete Cooper2015-03-041-1/+0
| | | | llvm-svn: 231195
* This file should always have included MCAssembler and not MCStreamer. NFCPete Cooper2015-03-041-1/+1
| | | | llvm-svn: 231194
* Remove MCStreamer.h include from MCContext.h and explictly include it where ↵Pete Cooper2015-03-046-0/+6
| | | | | | necessary. NFC llvm-svn: 231193
* Recommit r231168: unique_ptrify LiveRange::segmentSetDavid Blaikie2015-03-042-3/+4
| | | | | | | | | | | | | | | | | | | | | | | GCC 4.7's libstdc++ doesn't have std::map::emplace, but it does have std::unordered_map::emplace, and the use case here doesn't appear to need ordering. The container has been changed in a separate/precursor patch, and now this patch should hopefully build cleanly even with GCC 4.7. & then I realized the order of the container did matter, so extra handling of ordering was added in r231189. Original commit message: This makes LiveRange non-copyable, and LiveInterval is already non-movable (due to the explicit dtor), so now it's non-copyable and non-movable. Fix the one case where we were relying on the (deprecated in C++11) implicit copy ctor of LiveInterval (which happened to work because the ctor created an object with a null segmentSet, so double-deleting the null pointer was fine). llvm-svn: 231192
* Recommit r231175: Change LiveStackAnalysis::SS2IntervalMap from std::map to ↵David Blaikie2015-03-041-2/+10
| | | | | | | | | | | | | | | | std::unordered_map The order of this container was needed at one point - so, at that point create a temporary array of pointers, sort those, then iterate them. This keeps lookup efficient (& the lesser issue, of allowing the use of emplace... ), object identity preserved, and ordered iteration in the one place that requires it. While this has no functional change, I realize it does mean allocating an extra data structure and performing a sort - so if this looks suspect to anyone regarding perf characteristics, I'm all ears. llvm-svn: 231189
* RegisterCoalescer: Gracefully continue if subrange merging fails.Matthias Braun2015-03-041-18/+48
| | | | | | | | | | | There is a known bug where the register coalescer fails to merge subranges when multiple ranges end up in the "overflow" bit 32 of the lanemasks. A proper fix for this is complicated so for now this is a workaround which lets the register coalescer drop the subregister liveness information (we just loose some precision by that) and continue. llvm-svn: 231186
* Drop the "eh_" from eh_func_begin and eh_func_end.Rafael Espindola2015-03-041-2/+2
| | | | | | They will be used for more than eh tables. llvm-svn: 231185
* Revert "unique_ptrify LiveRange::segmentSet"David Blaikie2015-03-042-4/+3
| | | | | | | | Apparently something does care about ordering of LiveIntervals... so revert all that stuff (r231175, r231176, r231177) & take some time to re-evaluate. llvm-svn: 231184
* [RewriteStatepointsForGC] Fix a relocation bug w.r.t values defined by ↵Philip Reames2015-03-041-2/+12
| | | | | | | | | | | | | | | invoke instructions RewriteStatepointsForGC pass emits an alloca for each GC pointer which will be relocated. It then inserts stores after def and all relocations, and inserts loads before each use as well. In the end, mem2reg is used to update IR with relocations in SSA form. However, there is a problem with inserting stores for values defined by invoke instructions. The code didn't expect a def was a terminator instruction, and inserting instructions after these terminators resulted in malformed IR. This patch fixes this problem by handling invoke instructions as a special case. If the def is an invoke instruction, the store will be inserted at the beginning of the normal destination block. Since return value from invoke instruction does not dominate the unwind destination block, no action is needed there. Patch by: Chen Li Differential Revision: http://reviews.llvm.org/D7923 llvm-svn: 231183
* Remove 'llvm.x86.avx2.vbroadcasti128' intrinsic.Juergen Ributzka2015-03-042-5/+12
| | | | | | | | | | | The intrinsic is no longer generated by the front-end. Remove the intrinsic and auto-upgrade it to a vector shuffle. Reviewed by Nadav This is related to rdar://problem/18742778. llvm-svn: 231182
* Recommit r231168: unique_ptrify LiveRange::segmentSetDavid Blaikie2015-03-032-3/+4
| | | | | | | | | | | | | | | | | | | | GCC 4.7's libstdc++ doesn't have std::map::emplace, but it does have std::unordered_map::emplace, and the use case here doesn't appear to need ordering. The container has been changed in a separate/precursor patch, and now this patch should hopefully build cleanly even with GCC 4.7. Original commit message: This makes LiveRange non-copyable, and LiveInterval is already non-movable (due to the explicit dtor), so now it's non-copyable and non-movable. Fix the one case where we were relying on the (deprecated in C++11) implicit copy ctor of LiveInterval (which happened to work because the ctor created an object with a null segmentSet, so double-deleting the null pointer was fine). llvm-svn: 231176
* Revert "unique_ptrify LiveRange::segmentSet"David Blaikie2015-03-032-4/+3
| | | | | | | | GCC 4.7 *shakes fist* (doesn't have std::map::emplace... ) This reverts commit r231168. llvm-svn: 231173
* Move TargetLibraryInfo data from two files into one common .def file.Jan Wen Voung2015-03-031-330/+2
| | | | | | | | | | | | | | | Summary: This makes it more obvious that the enum definition and the "StandardName" array is in sync. Mechanically refactored w/ a python script. Test Plan: still compiles Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7845 llvm-svn: 231172
* unique_ptrify LiveRange::segmentSetDavid Blaikie2015-03-032-3/+4
| | | | | | | | | | | | | This makes LiveRange non-copyable, and LiveInterval is already non-movable (due to the explicit dtor), so now it's non-copyable and non-movable. Fix the one case where we were relying on the (deprecated in C++11) implicit copy ctor of LiveInterval (which happened to work because the ctor created an object with a null segmentSet, so double-deleting the null pointer was fine). llvm-svn: 231168
* [sanitizer/coverage] Add AFL-style coverage counters (search heuristic for ↵Kostya Serebryany2015-03-038-8/+98
| | | | | | | | | | | | | | | | | | | | | | | | | fuzzing). Introduce -mllvm -sanitizer-coverage-8bit-counters=1 which adds imprecise thread-unfriendly 8-bit coverage counters. The run-time library maps these 8-bit counters to 8-bit bitsets in the same way AFL (http://lcamtuf.coredump.cx/afl/technical_details.txt) does: counter values are divided into 8 ranges and based on the counter value one of the bits in the bitset is set. The AFL ranges are used here: 1, 2, 3, 4-7, 8-15, 16-31, 32-127, 128+. These counters provide a search heuristic for single-threaded coverage-guided fuzzers, we do not expect them to be useful for other purposes. Depending on the value of -fsanitize-coverage=[123] flag, these counters will be added to the function entry blocks (=1), every basic block (=2), or every edge (=3). Use these counters as an optional search heuristic in the Fuzzer library. Add a test where this heuristic is critical. llvm-svn: 231166
* Remove subtarget dependence in pass pipeline setup for AArch64.Eric Christopher2015-03-032-4/+6
| | | | llvm-svn: 231165
* WinEH: Remove vestigial EH objectReid Kleckner2015-03-031-43/+13
| | | | | | | | Ultimately, we'll need to leave something behind to indicate which alloca will hold the exception, but we can figure that out when it comes time to emit the __CxxFrameHandler3 catch handler table. llvm-svn: 231164
* InstCombine: Ensure select condition types are identical before mergingDavid Majnemer2015-03-031-28/+32
| | | | | | | | | | Selection conditions may be vectors or scalars. Make sure InstCombine doesn't indiscriminately assume that a select which is value dependent on another select have identical select condition types. This fixes PR22773. llvm-svn: 231156
* Avoid copying LiveInterval, this could lead to a double-deleteDavid Blaikie2015-03-031-1/+1
| | | | llvm-svn: 231154
* Fix a problem where the TwoAddressInstructionPass which generate redundant ↵Eric Christopher2015-03-031-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | register moves in a loop. From: int M, total; void foo() { int i; for (i = 0; i < M; i++) { total = total + i / 2; } } This is the kernel loop: .LBB0_2: # %for.body =>This Inner Loop Header: Depth=1 movl %edx, %esi movl %ecx, %edx shrl $31, %edx addl %ecx, %edx sarl %edx addl %esi, %edx incl %ecx cmpl %eax, %ecx jl .LBB0_2 -------------------------- The first mov insn "movl %edx, %esi" could be removed if we change "addl %esi, %edx" to "addl %edx, %esi". The IR before TwoAddressInstructionPass is: BB#2: derived from LLVM BB %for.body Predecessors according to CFG: BB#1 BB#2 %vreg3<def> = COPY %vreg12<kill>; GR32:%vreg3,%vreg12 %vreg2<def> = COPY %vreg11<kill>; GR32:%vreg2,%vreg11 %vreg7<def,tied1> = SHR32ri %vreg3<tied0>, 31, %EFLAGS<imp-def,dead>; GR32:%vreg7,%vreg3 %vreg8<def,tied1> = ADD32rr %vreg3<tied0>, %vreg7<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg8,%vreg3,%vreg7 %vreg9<def,tied1> = SAR32r1 %vreg8<kill,tied0>, %EFLAGS<imp-def,dead>; GR32:%vreg9,%vreg8 %vreg4<def,tied1> = ADD32rr %vreg9<kill,tied0>, %vreg2<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg4,%vreg9,%vreg2 %vreg5<def,tied1> = INC64_32r %vreg3<kill,tied0>, %EFLAGS<imp-def,dead>; GR32:%vreg5,%vreg3 CMP32rr %vreg5, %vreg0, %EFLAGS<imp-def>; GR32:%vreg5,%vreg0 %vreg11<def> = COPY %vreg4; GR32:%vreg11,%vreg4 %vreg12<def> = COPY %vreg5<kill>; GR32:%vreg12,%vreg5 JL_4 <BB#2>, %EFLAGS<imp-use,kill> Now TwoAddressInstructionPass will choose vreg9 to be tied with vreg4. However, it doesn't see that there is copy from vreg4 to vreg11 and another copy from vreg11 to vreg2 inside the loop body. To remove those copies, it is necessary to choose vreg2 to be tied with vreg4 instead of vreg9. This code pattern commonly appears when there is reduction operation in a loop. So check for a reversed copy chain and if we encounter one then we can commute the add instruction so we can avoid a copy. Patch by Wei Mi. http://reviews.llvm.org/D7806 llvm-svn: 231148
* Remove getDataLayout() from Instruction/GlobalValue/BasicBlock/FunctionMehdi Amini2015-03-035-16/+12
| | | | | | | | | | | | | | | | | Summary: This does not conceptually belongs here. Instead provide a shortcut getModule() that provides access to the DataLayout. Reviewers: chandlerc, echristo Reviewed By: echristo Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8027 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 231147
* DAGCombiner::LoadedSlice: Remove explicit copy ctor in favor of the Rule of ZeroDavid Blaikie2015-03-031-3/+0
| | | | | | | This way, the copy assignment operator can be used without hitting the deprecated case in C++11. llvm-svn: 231144
* RewriteStatepointsForGC::PhiState: Remove explicit copy ctor in favor of the ↵David Blaikie2015-03-031-3/+0
| | | | | | | | | | | | Rule of Zero The assertion was just checking a class invariant that's pretty easy to verify by inspection (no mutating operations, and the two non-copy ctors already ensure the state is maintained) so remove the explicit copy ctor in favor of the default, thus allowing the use of the default copy assignment operator without hitting the C++11 deprecation here. llvm-svn: 231143
* Teach ComputeNumSignBits about signed divisions.Nadav Rotem2015-03-031-0/+17
| | | | | | | http://reviews.llvm.org/D8028 rdar://20023136 llvm-svn: 231140
* Revert "Remove the explicit SDNodeIterator::operator= in favor of the ↵David Blaikie2015-03-038-20/+22
| | | | | | | | | | | implicit default" Accidentally committed a few more of these cleanup changes than intended. Still breaking these out & tidying them up. This reverts commit r231135. llvm-svn: 231136
* Remove the explicit SDNodeIterator::operator= in favor of the implicit defaultDavid Blaikie2015-03-038-22/+20
| | | | | | | | | | There doesn't seem to be any need to assert that iterator assignment is between iterators over the same node - if you want to reuse an iterator variable to iterate another node, that's perfectly acceptable. Just don't mix comparisons between iterators into disjoint sequences, as usual. llvm-svn: 231135
* Remove LatencyPriorityQueue::dump because it relies on an implicit copy ctor ↵David Blaikie2015-03-031-13/+0
| | | | | | | | | | | | | which is deprecated in C++11 (due to the presence of a user-declare dtor in the base class) This type could be made copyable (= default a protected copy ctor in the base class, and preferably make the derived class final to avoid risks of providing a slicing copy operation to further derived classes) but it seemed easier to avoid that complexity for a dump function that I assume (by symmetry with ResourcePriorityQueue's dump, which was actively buggy) not often used. llvm-svn: 231133
* [X86][ELF] Correct relocation for DWARF TLS referencesPaul Robinson2015-03-033-11/+14
| | | | | | | | | Previously we had only Linux using DTPOFF for these; all X86 ELF targets should. Fixes a side issue mentioned in PR21077. Differential Revision: http://reviews.llvm.org/D8011 llvm-svn: 231130
* remove enum value names from comments; NFCSanjay Patel2015-03-031-70/+68
| | | | llvm-svn: 231129
* unique_ptrify ResourcePriorityQueue::ResourceModelDavid Blaikie2015-03-031-1/+1
| | | | llvm-svn: 231127
* Remove ResourcePriorityQueue::dump as it relies on copying a non-copyable ↵David Blaikie2015-03-031-14/+0
| | | | | | type which would result in a double-delete llvm-svn: 231126
* use bool operator shortcut; NFCSanjay Patel2015-03-031-2/+1
| | | | llvm-svn: 231123
* Fixing problem with field initialization orderAndrew Kaylor2015-03-031-2/+2
| | | | llvm-svn: 231122
* Fix PR22762. When emitting a DWARF expression check whether this is theAdrian Prantl2015-03-031-6/+7
| | | | | | | | frame register before checking if there is a DWARF register number for it. Thanks to H.J. Lu for diagnosing this and providing the testcase! llvm-svn: 231121
* Outline cleanup handlers for native Windows C++ exception handlingAndrew Kaylor2015-03-031-97/+251
| | | | | | Differential Revision: http://reviews.llvm.org/D7865 llvm-svn: 231117
* Add the following 64-bit vector integer arithmetic instructions added in POWER8:Kit Barton2015-03-035-10/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | vaddudm vsubudm vmulesw vmulosw vmuleuw vmulouw vmuluwm vmaxsd vmaxud vminsd vminud vcmpequd vcmpequd. vcmpgtsd vcmpgtsd. vcmpgtud vcmpgtud. vrld vsld vsrd vsrad Phabricator review: http://reviews.llvm.org/D7959 llvm-svn: 231115
* Remove explicit no-op dtor in favor of the implicit dtor so as not to ↵David Blaikie2015-03-031-3/+0
| | | | | | disable/deprecate the copy operations. llvm-svn: 231113
* Add a comment above findRepresentativeClass explaining why it'sEric Christopher2015-03-031-0/+4
| | | | | | where it is so that future generations can understand. llvm-svn: 231111
* unique_ptrify FullDependenceAnalysis::DVDavid Blaikie2015-03-031-9/+5
| | | | | | | Making this type a little harder to abuse (see workaround relating to use of the implicit copy ctor in the prior commit) llvm-svn: 231104
* FullDependenceAnalysis: Avoid using the (deprecated in C++11) copy ctorDavid Blaikie2015-03-031-23/+22
| | | | llvm-svn: 231103
* Fix PR22750: non-determinism causes assertion failure in DWARF generationDario Domizioli2015-03-031-2/+5
| | | | | | | | | | | | | | | | | | | | | | | The cause of the issue is the interaction of two factors: 1) When generating a DW_TAG_imported_declaration DIE which imports another imported declaration, the code in AsmPrinter/DwarfCompileUnit.cpp asserts that the second imported declaration must already have a DIE. 2) There is a non-determinism in the order in which imported declarations within the same scope are processed. Because of the non-determinism (2), it is possible that an imported declaration is processed before another one it depends on, breaking the assumption in (1). The source of the non-determinism is that the imported declaration DIDescriptors are sorted by scope in DwarfDebug::beginModule(); however that sort is not a stable_sort, therefore the order of the declarations within the same scope is not preserved. The attached patch changes the std::sort to a std::stable_sort and it fixes the problem. Test omitted due to it being non-deterministic and depending on the implementation of std::sort. llvm-svn: 231100
* Make Triple::getOSVersion make sense for Android.Dan Albert2015-03-031-0/+8
| | | | | | | | | | | | Reviewers: srhines Reviewed By: srhines Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7928 llvm-svn: 231090
* 80-column fixup.Eric Christopher2015-03-031-1/+2
| | | | llvm-svn: 231088
* [AArch64] When combining constant mul of -3, prefer (sub x, (shl x, N)).Chad Rosier2015-03-031-9/+9
| | | | | | This change only effects codegen when the constant is -3. llvm-svn: 231085
* DebugInfo: Move new hierarchy into placeDuncan P. N. Exon Smith2015-03-034-1272/+297
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the specialized metadata nodes for the new debug info hierarchy into place, finishing off PR22464. I've done bootstraps (and all that) and I'm confident this commit is NFC as far as DWARF output is concerned. Let me know if I'm wrong :). The code changes are fairly mechanical: - Bumped the "Debug Info Version". - `DIBuilder` now creates the appropriate subclass of `MDNode`. - Subclasses of DIDescriptor now expect to hold their "MD" counterparts (e.g., `DIBasicType` expects `MDBasicType`). - Deleted a ton of dead code in `AsmWriter.cpp` and `DebugInfo.cpp` for printing comments. - Big update to LangRef to describe the nodes in the new hierarchy. Feel free to make it better. Testcase changes are enormous. There's an accompanying clang commit on its way. If you have out-of-tree debug info testcases, I just broke your build. - `upgrade-specialized-nodes.sh` is attached to PR22564. I used it to update all the IR testcases. - Unfortunately I failed to find way to script the updates to CHECK lines, so I updated all of these by hand. This was fairly painful, since the old CHECKs are difficult to reason about. That's one of the benefits of the new hierarchy. This work isn't quite finished, BTW. The `DIDescriptor` subclasses are almost empty wrappers, but not quite: they still have loose casting checks (see the `RETURN_FROM_RAW()` macro). Once they're completely gutted, I'll rename the "MD" classes to "DI" and kill the wrappers. I also expect to make a few schema changes now that it's easier to reason about everything. llvm-svn: 231082
* [X86][Haswell][SchedModel] Fix patterns for scalar FMA3 variants.Michael Kuperstein2015-03-031-2/+2
| | | | llvm-svn: 231073
OpenPOWER on IntegriCloud