summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* Test CommitMichael Kuperstein2013-02-081-1/+1
| | | | llvm-svn: 174709
* Parse the attribute group reference on a function.Bill Wendling2013-02-082-8/+94
| | | | | | | | | | | Attribute references are of this form: define void @foo() #0 #1 #2 { ... } Parse them for function attributes. If there's more than one reference, then they are merged together. llvm-svn: 174697
* When Mips16 frames grow large, the immediate field may exceed the maximumReed Kotler2013-02-083-10/+90
| | | | | | | | allowed size for the instruction. This code uses RegScavenger to fix this. We sometimes need 2 registers for Mips16 so we must handle things differently than how register scavenger is normally used. llvm-svn: 174696
* Revert "Have InstCombine call SipmlifyCall when handling calls. Test case ↵Andrew Trick2013-02-081-6/+0
| | | | | | | | | | included." This reverts commit 3854a5d90fee52af1065edbed34521fff6cdc18d. This causes a clang unit test to hang: vtable-available-externally.cpp. llvm-svn: 174692
* Use ParseFnAttributeValuePairs instead of ParseOptionalFuncAttrs Bill Wendling2013-02-082-90/+50
| | | | | | | The functionality of ParseOptionalFuncAttrs was there in ParseFnAttributeValuePairs. So just use that instead. llvm-svn: 174686
* Have InstCombine call SipmlifyCall when handling calls. Test case included.Michael Ilseman2013-02-071-0/+6
| | | | llvm-svn: 174675
* fix 80-col violation and fix the docs.Nadav Rotem2013-02-071-3/+7
| | | | llvm-svn: 174671
* [mips] Make Filler a class and reduce indentation.Akira Hatanaka2013-02-071-34/+38
| | | | llvm-svn: 174666
* Formatting.Eric Christopher2013-02-071-2/+1
| | | | llvm-svn: 174664
* "Clean up" line section symbol emission by emitting the sectionEric Christopher2013-02-072-8/+12
| | | | | | | syms before constructing the compile units so we're not emitting section references to sections not there already. llvm-svn: 174663
* [patch] bug 15055 Add Unistd.h to OProfileWrapper.cppWill Schmidt2013-02-071-0/+1
| | | | | | | | Add #include <unistd.h> to OProfileWrapper.cpp. This provides the declarations for 'read' and 'close' that are otherwise missing, and result in 'error: <foo> was not declared in this scope'. This matches the issue as reported in bug 15055 "Can no longer compile LLVM with --with-oprofile" llvm-svn: 174661
* Constrain PowerPC autovectorization to fix bug 15041.Bill Schmidt2013-02-071-0/+19
| | | | | | | | | | | | | Certain vector operations don't vectorize well with the current PowerPC implementation. Element insert/extract performs poorly without VSX support because Altivec requires going through memory. SREM, UREM, and VSELECT all produce bad scalar code. There's a lot of work to do for the cost model before autovectorization will be tuned well, and this is not an attempt to address the larger problem. llvm-svn: 174660
* [mips] Add definition of JALR instruction which has two register operands. ↵Akira Hatanaka2013-02-073-3/+14
| | | | | | | | Change the original JALR instruction with one register operand to be a pseudo-instruction. llvm-svn: 174657
* R600/SI: cleanup VGPR encodingTom Stellard2013-02-075-178/+16
| | | | | | | | | | Remove all the unused code. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174656
* R600/SI: Handle VGPR64 destination in copyPhysReg().Tom Stellard2013-02-071-1/+9
| | | | | | | | | | Allows nexuiz to run with radeonsi. Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174655
* R600/SI: Add pattern for mul.Tom Stellard2013-02-071-0/+4
| | | | | | | | | | 20 more little piglits with radeonsi. Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174654
* R600/SI: simplify and fix SMRD encodingTom Stellard2013-02-076-154/+70
| | | | | | | | | | The _SGPR variants where wrong. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174653
* R600/SI: add proper 64bit immediate support v2Tom Stellard2013-02-073-12/+18
| | | | | | | | | | v2: rebased on current upstream Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174652
* R600: Add an explicit default processorTom Stellard2013-02-071-0/+1
| | | | | | | | | | | This is for the case when no processor is passed to the backend. This prevents the '' is not a recognized processor for this target (ignoring processor) warning from being generated by clang. llvm-svn: 174651
* Identify and simplify idempotent intrinsics. Test case included.Michael Ilseman2013-02-071-0/+36
| | | | llvm-svn: 174650
* Loop Vectorizer: Refactor Memory Cost ComputationArnold Schwaighofer2013-02-071-180/+52
| | | | | | | | | | We don't want too many classes in a pass and the classes obscure the details. I was going a little overboard with object modeling here. Replace classes by generic code that handles both loads and stores. No functionality change intended. llvm-svn: 174646
* R600/SI: Use proper instructions for array/shadow samplers.Tom Stellard2013-02-072-4/+54
| | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174634
* R600/SI: Make sample intrinsic address parameter type overloaded.Tom Stellard2013-02-073-22/+38
| | | | | | | | | | | | | Handle vectors of 1 to 16 integers. Change the intrinsic names to prevent the wrong one from being selected at runtime due to the overloading. Patch By: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174633
* R600/SI: Add basic support for more integer vector types.Tom Stellard2013-02-075-11/+110
| | | | | | | | | | | | | v1i32, v2i32, v8i32 and v16i32. Only add VGPR register classes for integer vector types, to avoid attempts copying from VGPR to SGPR registers, which is not possible. Patch By: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174632
* ARM cost model: Add costs for vector selectsArnold Schwaighofer2013-02-071-0/+15
| | | | | | | | Vector selects are cheap on NEON. They get lowered to a vbsl instruction. radar://13158753 llvm-svn: 174631
* R600/SI: Add pattern for flog2Michel Danzer2013-02-071-1/+3
| | | | | | | 22 more little piglits with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174615
* FDE::dumpHeader(): Forgot to fix one more formatting, ... take two!NAKAMURA Takumi2013-02-071-2/+2
| | | | | | Excuse me, I could not test it locally. llvm-svn: 174614
* R600: Consolidate sub register indices.Tom Stellard2013-02-078-93/+73
| | | | | | | | | | Use sub0-15 everywhere. Patch by: Michel Dänzerr Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 174610
* R600: Add support for SET*_DX10 instructionsTom Stellard2013-02-072-29/+131
| | | | | | | | | | | These instructions compare two floating point values and return an integer true (-1) or false (0) value. When compiling code generated by the Mesa GLSL frontend, the SET*_DX10 instructions save us four instructions for most branch decisions that use floating-point comparisons. llvm-svn: 174609
* R600: Fix assembly name for SETGT_INTTom Stellard2013-02-071-1/+1
| | | | llvm-svn: 174607
* FDE::dumpHeader(): Forgot to fix one more formatting. It affected bigendian ↵NAKAMURA Takumi2013-02-071-2/+3
| | | | | | hosts. llvm-svn: 174602
* Make sure we call externals from libraries properly when -static.Reed Kotler2013-02-071-0/+3
| | | | | | For example, when we are doing mips16 hard float or soft float. llvm-svn: 174583
* tblgen: Diagnose duplicate includes.Sean Silva2013-02-074-10/+23
| | | | | | | | | | | | | | | A double inclusion will pretty much always be an error in TableGen, so there's no point going on just to die with "def already defined" or whatnot. I'm not too thrilled about the "public: ... private: ..." to expose the DependenciesMapTy, but I really didn't see a better way to keep that type centralized. It's a smell that indicates that some refactoring is needed to make this code more loosely coupled. This should avoid all bugs of the same nature as PR15189. llvm-svn: 174582
* Moved some comments due to the recent refactoring of ObjCARC.Michael Gottesman2013-02-072-5/+4
| | | | | | | | 1. Moved a comment from ObjCARCOpts.cpp -> ObjCARCContract.cpp. 2. Removed a comment from ObjCARCOpts.cpp that was already moved to ObjCARCAliasAnalysis.h/.cpp. llvm-svn: 174581
* Enable jumps when in -static mode.Reed Kotler2013-02-071-1/+1
| | | | llvm-svn: 174580
* DWARFDebugFrame.cpp: Fix formatting on i686 hosts.NAKAMURA Takumi2013-02-071-3/+6
| | | | | FIXME: Are they really truncated to i32 from i64 unconditionally? llvm-svn: 174574
* Preserve fast-math flags after reassociation and commutation. Update test casesMichael Ilseman2013-02-071-5/+20
| | | | llvm-svn: 174571
* Conditionalize constant folding of math intrinsics on the availability of an ↵Owen Anderson2013-02-071-0/+10
| | | | | | implementation on the host. This is a little bit unfortunate, but until someone decides to implement a full libm for APFloat, we don't have a better way to get this functionality. llvm-svn: 174561
* Signficantly generalize our ability to constant fold floating point ↵Owen Anderson2013-02-061-14/+88
| | | | | | intrinsics, including ones on half types. llvm-svn: 174555
* Code Custodian (trivial whitespace cleanup)Joe Abbey2013-02-062-67/+66
| | | | llvm-svn: 174550
* Clean up multiple skeleton compile units if we have multiple compileEric Christopher2013-02-062-8/+6
| | | | | | units coming in. llvm-svn: 174548
* Remove some dead code.Eric Christopher2013-02-062-34/+0
| | | | llvm-svn: 174547
* [mips] Make NOP a pseudo instruction and expand it to "sll $zero, $zero, 0".Akira Hatanaka2013-02-063-15/+7
| | | | llvm-svn: 174546
* This is a follow-up on r174446, now taking Atom processors intoEli Bendersky2013-02-061-6/+6
| | | | | | | | | | | | account. Atoms use LEA for updating SP in prologs/epilogs, and the exact LEA opcode depends on the data model. Also reapplying the test case which was added and then reverted (because of Atom failures), this time specifying explicitly the CPU in addition to the triple. The test case now checks all variations (data mode, cpu Atom vs. Core). llvm-svn: 174542
* PPC calling convention cleanup.Bill Schmidt2013-02-062-75/+46
| | | | | | | | Most of PPCCallingConv.td is used only by the 32-bit SVR4 ABI. Rename things to clarify this. Also delete some code that's been commented out for a long time. llvm-svn: 174526
* R600: Support for indirect addressing v4Tom Stellard2013-02-0630-75/+1124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines llvm-svn: 174525
* Implement external weak (ELF) symbols on AArch64Tim Northover2013-02-062-4/+17
| | | | | | | | | Weakly defined symbols should evaluate to 0 if they're undefined at link-time. This is impossible to do with the usual address generation patterns, so we should use a literal pool entry to materlialise the address. llvm-svn: 174518
* Add some comments to new frame entriesEli Bendersky2013-02-061-0/+4
| | | | llvm-svn: 174515
* Add AArch64 CRC32 instructionsTim Northover2013-02-061-1/+19
| | | | | | | | These instructions are a late addition to the architecture, and may yet end up behind an optional attribute, but for now they're available at all times. llvm-svn: 174496
* Add icache prefetch operations to AArch64Tim Northover2013-02-062-0/+12
| | | | | | | This adds hints to the various "prfm" instructions so that they can affect the instruction cache as well as the data cache. llvm-svn: 174495
OpenPOWER on IntegriCloud