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* Fix logic error optimizing "icmp pred (urem X, Y), Y" where pred is signed.Nick Lewycky2013-07-121-4/+7
| | | | | | Fixes PR16605. llvm-svn: 186229
* [mips] Implement MipsTargetMachine::getInstrItineraryData().Akira Hatanaka2013-07-123-2/+9
| | | | llvm-svn: 186227
* Fix ARM paired GPR COPY loweringJF Bastien2013-07-121-0/+3
| | | | | | | | | | | | | ARM paired GPR COPY was being lowered to two MOVr without CC. This patch puts the CC back. My test is a reduction of the case where I encountered the issue, 64-bit atomics use paired GPRs. The issue only occurs with selectionDAG, FastISel doesn't encounter it so I didn't bother calling it. llvm-svn: 186226
* Fix a crash in EvaluateInDifferentElementOrder where it would generate anJoey Gouly2013-07-121-1/+3
| | | | | | | | undef vector of the wrong type. LGTM'd by Nick Lewycky on IRC. llvm-svn: 186224
* [mips] Add instruction itinerary classes for mult, seb and slt instructions.Akira Hatanaka2013-07-123-13/+16
| | | | llvm-svn: 186222
* Use the function attributes to pass along the stack protector buffer size.Bill Wendling2013-07-121-7/+19
| | | | | | | Now that we have robust function attributes, don't use a command line option to specify the stack protecto buffer size. llvm-svn: 186217
* LFTR improvement to avoid truncation.Andrew Trick2013-07-121-6/+32
| | | | | | This is a reimplemntation of the patch originally in r186107. llvm-svn: 186215
* Cleanup LFTR logic.Andrew Trick2013-07-121-28/+9
| | | | llvm-svn: 186214
* Cleanup: rename a variable to make the logic easier to follow.Andrew Trick2013-07-121-7/+7
| | | | llvm-svn: 186213
* Remove extraneous braces.Eric Christopher2013-07-121-6/+3
| | | | llvm-svn: 186212
* Change llvm-ar to use lib/Object.Rafael Espindola2013-07-121-26/+23
| | | | | | | | | | | | | | | | | | | | | | This fixes two bugs is lib/Object that the use in llvm-ar found: * In OS X created archives, the name can be padded with nulls. Strip them. * In the constructor, remember the first non special member and use that in begin_children. This makes sure we skip all special members, not just the first one. The change to llvm-ar itself consist of * Using lib/Object for reading archives instead of ArchiveReader.cpp. * Writing the modified archive directly, instead of creating an in memory representation. The old Archive library was way more general than what is needed, as can be seen by the diffstat of this patch. Having llvm-ar using lib/Object now opens the way for creating regular symbol tables for both native objects and bitcode files so that we can use those archives for LTO. llvm-svn: 186197
* R600: Remove unsafe type punning. No intended functionality change.Benjamin Kramer2013-07-121-6/+4
| | | | llvm-svn: 186196
* X86 cost model: Add cost for vectorized gather/scatherArnold Schwaighofer2013-07-121-0/+15
| | | | | | radar://14351991 llvm-svn: 186189
* ARM cost model: Add cost for gather/scatherArnold Schwaighofer2013-07-121-0/+9
| | | | | | | | | | Fixes a 35% degradation compared to unvectorized code in MiBench/automotive-susan and an equally serious regression on a private image processing benchmark. radar://14351991 llvm-svn: 186188
* TargetTransformInfo: address calculation parameter for gather/scatherArnold Schwaighofer2013-07-124-8/+64
| | | | | | | | | | | Address calculation for gather/scather in vectorized code can incur a significant cost making vectorization unbeneficial. Add infrastructure to add cost. Tests and cost model for targets will be in follow-up commits. radar://14351991 llvm-svn: 186187
* R600/SI: Add support for f64 kernel argumentsTom Stellard2013-07-121-1/+1
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186182
* R600/SI: Implement select and compares for SITom Stellard2013-07-121-6/+18
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186181
* R600/SI: Add fsqrt pattern for SITom Stellard2013-07-121-2/+6
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186180
* R600/SI: Add double precision fsub pattern for SITom Stellard2013-07-122-3/+29
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186179
* R600/SI: SI support for 64bit ConstantFPTom Stellard2013-07-122-0/+19
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186178
* R600/SI: Add initial double precision support for SITom Stellard2013-07-123-1/+36
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186177
* X86: Shrink certain forms of movsx.Benjamin Kramer2013-07-121-0/+35
| | | | | | | | | | | | In particular: movsbw %al, %ax --> cbtw movswl %ax, %eax --> cwtl movslq %eax, %rax --> cltq According to Intel's manual those have the same performance characteristics but come with a smaller encoding. llvm-svn: 186174
* X86: fold SSE2/AVX2 logical shift by immediate amount into zero vector when ↵Stephen Lin2013-07-121-0/+38
| | | | | | | | possible Patch by Andrea Di Biagio llvm-svn: 186165
* Don't reject an empty archive.Rafael Espindola2013-07-121-4/+6
| | | | llvm-svn: 186159
* Revert "indvars: Improve LFTR by eliminating truncation when comparingChandler Carruth2013-07-121-23/+4
| | | | | | | | | | | | | | | | | | | against a constant." This reverts commit r186107. It didn't handle wrapping arithmetic in the loop correctly and thus caused the following C program to count from 0 to UINT64_MAX instead of from 0 to 255 as intended: #include <stdio.h> int main() { unsigned char first = 0, last = 255; do { printf("%d\n", first); } while (first++ != last); } Full test case and instructions to reproduce with just the -indvars pass sent to the original review thread rather than to r186107's commit. llvm-svn: 186152
* Add support for Mips break and syscall insructions. The corresponding test ↵Vladimir Medic2013-07-122-0/+49
| | | | | | cases are added. llvm-svn: 186151
* [SystemZ] Optimize sign-extends of vector setccsRichard Sandiford2013-07-121-0/+9
| | | | | | | | | | | | | Normal (sext (setcc ...)) sequences are optimised into (select_cc ..., -1, 0) by DAGCombiner::visitSIGN_EXTEND. However, this is deliberately not done for vectors, and after vector type legalization we have (sext_inreg (setcc ...)) instead. I wondered about trying to extend DAGCombiner to handle this case too, but it seemed to be a loss on some other targets I tried, even those for which SETCC isn't "legal" and SELECT_CC is. llvm-svn: 186149
* [SystemZ] Fix parsing of inline asm registersRichard Sandiford2013-07-124-8/+49
| | | | | | | | | | | | GPR and FPR constraints like "{r2}" and "{f2}" weren't handled correctly because the name-to-regno mapping depends on the value type and (because of that) the internal names in RegStrings are not the same as the AsmName. CC constraints like "{cc}" didn't work either because there was no associated register class. llvm-svn: 186148
* [SystemZ] Improve spilling of LGDR and LDGRRichard Sandiford2013-07-121-1/+23
| | | | | | | If the source of these instructions is spilled we should load the destination. If the destination is spilled we should store the source. llvm-svn: 186147
* Stylistic change.Shuxin Yang2013-07-121-2/+2
| | | | | | Thank Nick for figuring out these problems. llvm-svn: 186146
* SLPVectorizer: Sink and enable CSE for ExtractElements.Nadav Rotem2013-07-121-11/+25
| | | | llvm-svn: 186145
* Target/X86: Add explicit Win64 and System V/x86-64 calling conventions.Charles Davis2013-07-128-26/+55
| | | | | | | | | | | | | | | Summary: This patch adds explicit calling convention types for the Win64 and System V/x86-64 ABIs. This allows code to override the default, and use the Win64 convention on a target that wants to use SysV (and vice-versa). This is needed to implement the `ms_abi` and `sysv_abi` GNU attributes. Reviewers: CC: llvm-svn: 186144
* Windows/TimeValue.inc: Mute prefixed '0' on %d to emulate %e.NAKAMURA Takumi2013-07-121-0/+5
| | | | | | It fixes compatibility in llvm/test/Object/archive-toc.test. llvm-svn: 186142
* PEI: refactor replaceFrameIndices(MF) to call replaceFrameIndices(BB).Manman Ren2013-07-122-81/+87
| | | | | | | replaceFrameIndices(MF) will iterate over the BBs and call replaceFrameIndices(BB). No functionality change. llvm-svn: 186141
* SLPVectorize: Replace the code that checks for vectorization candidates in ↵Nadav Rotem2013-07-121-25/+22
| | | | | | | | successor blocks with code that scans PHINodes. Before we could vectorize PHINodes scanning successors was a good way of finding candidates. Now we can vectorize the phinodes which is simpler. llvm-svn: 186139
* Remove an argument that we dont use anymore.Nadav Rotem2013-07-111-15/+12
| | | | llvm-svn: 186116
* PPC: Add some missing V_SET0 patternsHal Finkel2013-07-111-2/+15
| | | | | | | | | | We had patterns to match v4i32 immAllZerosV -> V_SET0, but not patterns for v8i16 (which occurs in the test case) or v16i8. The same was true for V_SETALLONES (so I added the associated patterns for those as well). Another bug found by llvm-stress. llvm-svn: 186108
* indvars: Improve LFTR by eliminating truncation when comparing against a ↵Andrew Trick2013-07-111-4/+23
| | | | | | | | | | | | | | | | | constant. Patch by Michele Scandale! Adds a special handling of the case where, during the loop exit condition rewriting, the exit value is a constant of bitwidth lower than the type of the induction variable: instead of introducing a trunc operation in order to match correctly the operand types, it allows to convert the constant value to an equivalent constant, depending on the initial value of the induction variable and the trip count, in order have an equivalent comparison between the induction variable and the new constant. llvm-svn: 186107
* PPCDAGToDAGISel::isRunOfOnes should return false on zeroHal Finkel2013-07-111-1/+4
| | | | | | | | | | | | This fixes a bug (found by csmith) at -O0 where we attempt to create a RLWIMI with an out-of-range operand. Most uses of the isRunOfOnes function are guarded by a condition that the value is not zero. This was not true in two places, and in both places a zero input would result in an out-of-rage MB value (= 32). To fix this, isRunOfOnes returns false on a zero input (and I've remove one now-redundant guard). llvm-svn: 186101
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-119-23/+23
| | | | | | size. llvm-svn: 186098
* Add back code for supporting old mingw versions. Should bring the bots back.Rafael Espindola2013-07-111-3/+13
| | | | llvm-svn: 186096
* Don't use a potentially expensive shift if all we want is one set bit.Benjamin Kramer2013-07-114-6/+6
| | | | | | No functionality change. llvm-svn: 186095
* Looks like some versions of mingw don't have errno_t. Use int.Rafael Espindola2013-07-111-1/+1
| | | | llvm-svn: 186092
* Use move semantics if possible to construct ConstantRanges.Benjamin Kramer2013-07-111-5/+6
| | | | | | | Arithmetic on ConstantRanges creates a lot of large temporary APInts that benefit from move semantics. llvm-svn: 186091
* Fix a FIXME about the format and add a test.Rafael Espindola2013-07-112-26/+16
| | | | | | | While at it, use strftime on Unix too and use the thread safe versions of localtime. llvm-svn: 186090
* LoopVectorize: Vectorize all accesses in address space zero with unit strideArnold Schwaighofer2013-07-111-8/+16
| | | | | | | | | | | We can vectorize them because in the case where we wrap in the address space the unvectorized code would have had to access a pointer value of zero which is undefined behavior in address space zero according to the LLVM IR semantics. (Thank you Duncan, for pointing this out to me). Fixes PR16592. llvm-svn: 186088
* Reduce the number of indirections in the attributes implementation.Benjamin Kramer2013-07-112-178/+131
| | | | | | | | | | | - Coallocate entires for AttributeSetImpls and Nodes after the class itself. - Remove mutable iterators from immutable classes. - Remove unused context field from AttributeImpl. - Derive Enum/Align/String attribute implementations from AttributeImpl instead of having a whole new inheritance tree for them. - Derive AlignAttributeImpl from EnumAttributeImpl. llvm-svn: 186075
* [SystemZ] Use zeroing form of RISBG for shift-and-AND sequencesRichard Sandiford2013-07-111-5/+66
| | | | | | Extend r186072 to handle shifts and ANDs. llvm-svn: 186073
* [SystemZ] Use zeroing form of RISBG for some AND sequencesRichard Sandiford2013-07-111-1/+118
| | | | | | | | | | | | RISBG can handle some ANDs for which no AND IMMEDIATE exists. It also acts as a three-operand AND for some cases where an AND IMMEDIATE could be used instead. It might be worth adding a pass to replace RISBG with AND IMMEDIATE in cases where the register operands end up being the same and where AND IMMEDIATE is smaller. llvm-svn: 186072
* [SystemZ] Allow 8-bit operands to RISBGRichard Sandiford2013-07-111-2/+1
| | | | | | | | | | | | RISBG has three 8-bit operands (I3, I4 and I5). I'd originally restricted all three to 6 bits, since that's the only range we intended to use at the time. However, the top bit of I4 acts as a "zero" flag for RISBG, while the top bit of I3 acts as a "test" flag for RNSBG & co. This patch therefore allows them to have the full 8-bit range. I've left the fifth operand as a 6-bit value for now since the upper 2 bits have no defined meaning. llvm-svn: 186070
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