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* [AMDGPU] Remove extra semicolon. NFCKonstantin Zhuravlyov2017-01-061-1/+1
| | | | llvm-svn: 291246
* [AMDGPU] Do not emit .AMDGPU.config section for amdhsaKonstantin Zhuravlyov2017-01-061-4/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D27732 llvm-svn: 291245
* [X86][SSE] Simplify float domain requirement in unary shuffle matching.Simon Pilgrim2017-01-061-2/+1
| | | | | | The AVX1-only limit is never actually required in matchUnaryVectorShuffle llvm-svn: 291244
* Remove trailing whitespace. NFCI.Simon Pilgrim2017-01-061-3/+3
| | | | llvm-svn: 291240
* [X86] Add X86Subtarget argument. NFCI.Simon Pilgrim2017-01-061-8/+12
| | | | | | All callers of getTargetVShiftNode have access to X86Subtarget already so pass it along instead of re-extracting it. llvm-svn: 291239
* [ASan] Make ASan instrument variable-masked loads and storesFilipe Cabecinhas2017-01-061-41/+55
| | | | | | | | | | | | Summary: Previously we only supported constant-masked loads and stores. Reviewers: kcc, RKSimon, pgousseau, gbedwell, vitalybuka Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28370 llvm-svn: 291238
* [globalisel] Stop requiring -debug/-debug-only=registerbankinfo for assertions.Daniel Sanders2017-01-061-6/+7
| | | | | | | | | | | | | | | | | | | | | Summary: I've noticed that these assertions don't trigger when the condition is false. The problem is that the DEBUG(x) macro only executes x when the pass is emitting debug output via the -debug and -debug-only=registerbankinfo command line arguments. Debug builds should always execute the assertions so use '#ifndef NDEBUG' instead. Also removed an assertion that is only true the first time it's tested. <Target>RegisterBankInfo's constructor will re-use register banks causing them to be valid on subsequent tests. That assertion will fail on the first test too in the near future. Reviewers: t.p.northover, ab, rovka, qcolombet Subscribers: dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D28358 llvm-svn: 291235
* [CostModel][X86] Fix 512-bit SDIV/UDIV 'big' costs.Simon Pilgrim2017-01-061-16/+18
| | | | | | Set the costs on the lowest target that supports the type. llvm-svn: 291229
* TarWriter: Emit PAX headers only when needed.Rui Ueyama2017-01-061-23/+20
| | | | | | | | We use PAX headers to store long filenames (>= 100 bytes). It is not needed to emit PAX headers if filenames fit in the Ustar header. This patch implements that optimization. llvm-svn: 291215
* [AVX-512] Add EXTRACT_SUBVECTOR support to combineBitcastForMaskedOp.Craig Topper2017-01-061-0/+21
| | | | llvm-svn: 291214
* [SelectionDAG] Rework lowerRangeToAssertZExtDavid Majnemer2017-01-061-6/+11
| | | | | | Utilize ConstantRange to make it easier to interpret range metadata. llvm-svn: 291211
* Add a class to create a tar archive file.Rui Ueyama2017-01-062-0/+170
| | | | | | | | | | | | | | In LLD, we create cpio archive files for --reproduce command. cpio was not a bad choice because it is very easy to create, but it was sometimes hard to use because people are not familiar with cpio command. I noticed that creating a tar archive isn't as hard as I thought. So I implemented it in this patch. Differential Revision: https://reviews.llvm.org/D28091 llvm-svn: 291209
* Revert "Use _Unwind_Backtrace on Apple platforms."Bob Wilson2017-01-061-1/+1
| | | | | | | | | | | This reverts commit 63165f6ae3bac1623be36d4b3ce63afa1d51a30a. After making this change, I discovered that _Unwind_Backtrace is unable to unwind past a signal handler after an assertion failure. I filed a bug report about that issue in rdar://29866587 but even if we get a fix soon, it will be awhile before it get released. llvm-svn: 291207
* LowerTypeTests: Split the pass in two: a resolution phase and a lowering phase.Peter Collingbourne2017-01-061-110/+155
| | | | | | | | | | | | This change separates how type identifiers are resolved from how intrinsic calls are lowered. All information required to lower an intrinsic call is stored in a new TypeIdLowering data structure. The idea is that this data structure can either be initialized using the module itself during regular LTO, or using the module summary in ThinLTO backends. Differential Revision: https://reviews.llvm.org/D28341 llvm-svn: 291205
* Remove unused private fields to fix the clang -Werror build.David Blaikie2017-01-061-5/+1
| | | | llvm-svn: 291201
* [AArch64, Lanai] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-01-0618-199/+386
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 291197
* [SelectionDAG] Correctly transform range metadata to AssertZExtDavid Majnemer2017-01-061-1/+1
| | | | | | | | We used the logBase2 of the high instead of the ceilLogBase2 resulting in the wrong result for certain values. For example, it resulted in an i1 AssertZExt when the exclusive portion of the range was 3. llvm-svn: 291196
* [libFuzzer] remove dead code, NFCKostya Serebryany2017-01-061-47/+0
| | | | llvm-svn: 291195
* Add iterator support to DWARFDie to allow child DIE iteration.Greg Clayton2017-01-051-4/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D28303 llvm-svn: 291194
* Code cleanup: Remove tab indents.Logan Chien2017-01-051-3/+3
| | | | llvm-svn: 291193
* [CostModel][X86] Tidyup arithmetic costs code. NFCI.Simon Pilgrim2017-01-051-28/+15
| | | | | | Remove unnecessary braces, remove one use variables and keep LUTs to similar naming convention. llvm-svn: 291187
* [libFuzzer] improve error handling during the merge (handle various IO failures)Kostya Serebryany2017-01-059-0/+32
| | | | llvm-svn: 291182
* [AArch64] Fold some filled/spilled subreg COPYsGeoff Berry2017-01-052-10/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Extend AArch64 foldMemoryOperandImpl() to handle folding spills of subreg COPYs with read-undef defs like: %vreg0:sub_32<def,read-undef> = COPY %WZR; GPR64:%vreg0 by widening the spilled physical source reg and generating: STRXui %XZR <fi#0> as well as folding fills of similar COPYs like: %vreg0:sub_32<def,read-undef> = COPY %vreg1; GPR64:%vreg0, GPR32:%vreg1 by generating: %vreg0:sub_32<def,read-undef> = LDRWui <fi#0> Reviewers: MatzeB, qcolombet Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D27425 llvm-svn: 291180
* Fix typo. NFCXin Tong2017-01-051-1/+1
| | | | llvm-svn: 291178
* ThinLTO: add early "dead-stripping" on the IndexTeresa Johnson2017-01-056-28/+196
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Using the linker-supplied list of "preserved" symbols, we can compute the list of "dead" symbols, i.e. the one that are not reachable from a "preserved" symbol transitively on the reference graph. Right now we are using this information to mark these functions as non-eligible for import. The impact is two folds: - Reduction of compile time: we don't import these functions anywhere or import the function these symbols are calling. - The limited number of import/export leads to better internalization. Patch originally by Mehdi Amini. Reviewers: mehdi_amini, pcc Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23488 llvm-svn: 291177
* PR 31534: When emitting both DWARF unwind tables and debug information,Joerg Sonnenberger2017-01-053-3/+26
| | | | | | | do not use .cfi_sections. This requires checking if any non-declaration function in the module needs an unwind table. llvm-svn: 291172
* [LICM] Allow promotion of some stores that are not guaranteed to execute.Michael Kuperstein2017-01-051-4/+24
| | | | | | | | | | | | | Promotion is always legal when a store within the loop is guaranteed to execute. However, this is not a necessary condition - for promotion to be memory model semantics-preserving, it is enough to have a store that dominates every exit block. This is because if the store dominates every exit block, the fact the exit block was executed implies the original store was executed as well. Differential Revision: https://reviews.llvm.org/D28147 llvm-svn: 291171
* CodeGen: Assert that liveness is up to date when reading block live-ins.Matthias Braun2017-01-055-35/+47
| | | | | | | | | | | | | | | | | Add an assert that checks whether liveins are up to date before they are used. - Do not print liveins into .mir files anymore in situations where they are out of date anyway. - The assert in the RegisterScavenger is superseded by the new one in livein_begin(). - Skip parts of the liveness updating logic in IfConversion.cpp when liveness isn't tracked anymore (just enough to avoid hitting the new assert()). Differential Revision: https://reviews.llvm.org/D27562 llvm-svn: 291169
* Revert "Reapply r291025 ("AMDGPU: Remove unneccessary intermediate vector")"Evgeniy Stepanov2017-01-051-33/+19
| | | | | | | | | | | | | | | | | | | Summary: This reverts commit r291144. It breaks build bots. http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-autoconf/builds/3270, http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fuzzer/builds/2058 lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:1638:12: error: could not convert ‘(const unsigned int*)(& Variants)’ from ‘const unsigned int*’ to ‘llvm::ArrayRef<unsigned int>’ return Variants; Reviewers: eugenis, tstellarAMD Patch by Alex Shlyapnikov. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D28372 llvm-svn: 291168
* [CostModel][X86] Move vXi32 MUL costs into existing tables. NFCI.Simon Pilgrim2017-01-051-6/+5
| | | | llvm-svn: 291165
* Remove trailing whitespace. NFCI.Simon Pilgrim2017-01-051-3/+3
| | | | llvm-svn: 291163
* [CostModel][X86] Reordered SSE42 arithmetic cost LUT into descending order. ↵Simon Pilgrim2017-01-051-13/+11
| | | | | | NFCI. llvm-svn: 291162
* [CostModel][X86] Move vXi64 MUL costs into existing tables. NFCI.Simon Pilgrim2017-01-051-11/+3
| | | | | | Removes need for yet another LUT. llvm-svn: 291158
* [LICM] Small update to note changes made in hoistRegionAndrew Kaylor2017-01-051-0/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D28363 llvm-svn: 291157
* [CostModel][X86] Strip unused 256-bit vector shift costs. NFCI.Simon Pilgrim2017-01-051-8/+0
| | | | | | Remove SSE2 256-bit entries - AVX targets will have used the SSE42 costs instead. llvm-svn: 291152
* [CostModel][X86] Include the cost of 256-bit upper subvector ↵Simon Pilgrim2017-01-051-2/+2
| | | | | | | | extract/insertion in AVX1 v4i64 MUL Matches other MUL/ADD/SUB 256-bit case on AVX1 llvm-svn: 291149
* TypoJoerg Sonnenberger2017-01-051-1/+1
| | | | llvm-svn: 291147
* [CostModel][X86] Merged SK_PermuteSingleSrc/SK_PermuteTwoSrc into common ↵Simon Pilgrim2017-01-051-272/+227
| | | | | | shuffle cost LUTs. NFCI. llvm-svn: 291146
* Reapply r291025 ("AMDGPU: Remove unneccessary intermediate vector")Matt Arsenault2017-01-051-19/+33
| | | | | | Arrays are supposed to be static const llvm-svn: 291144
* Remove a unnecessary hasLoopInvariantOperands check in loop sink.Xin Tong2017-01-051-2/+1
| | | | | | | | | | | | | | | | Summary: Preheader instruction's operands will always be invariant w.r.t. the loop which its the preheader for. Memory aliases are handled in canSinkOrHoistInst. Reviewers: danielcdh, davidxl Subscribers: mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D28270 llvm-svn: 291132
* less braces; NFCSanjay Patel2017-01-051-2/+1
| | | | llvm-svn: 291126
* [CostModel][X86] Add support for broadcast shuffle costsSimon Pilgrim2017-01-051-9/+48
| | | | | | | | Currently only for broadcasts with input and output of the same width. Differential Revision: https://reviews.llvm.org/D27811 llvm-svn: 291122
* [X86] Optimize vector shifts with variable but uniform shift amountsZvi Rackover2017-01-051-16/+22
| | | | | | | | | | | | | | | Summary: For instructions such as PSLLW/PSLLD/PSLLQ a variable shift amount may be passed in an XMM register. The lower 64-bits of the register are evaluated to determine the shift amount. This patch improves the construction of the vector containing the shift amount. Reviewers: craig.topper, delena, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28353 llvm-svn: 291120
* [ThinLTO] Add parenthesis as per build warningTeresa Johnson2017-01-051-3/+2
| | | | | | Fixes a warning about "||" and "&&" due to r291108. llvm-svn: 291119
* [PowerPC] Implement missing ISA 2.06 instructions.Tony Jiang2017-01-054-1/+18
| | | | | | | Instructions: fctidu[.], fctiwu[.], ftdiv, ftsqrt are not implemented. Implement them and add corresponding test cases in this patch. llvm-svn: 291116
* [ThinLTO] Use DenseSet instead of SmallPtrSet for holding GUIDsTeresa Johnson2017-01-051-4/+4
| | | | | | | | | Should fix some more bot failures from r291108. This should have been a DenseSet, since GUID is not a pointer type. It caused some bots to fail, but for some reason I wasnt't getting a build failure. llvm-svn: 291115
* [CostModel][X86] Pulled out common type legalization codeSimon Pilgrim2017-01-051-7/+4
| | | | llvm-svn: 291109
* [ThinLTO] Subsume all importing checks into a single flagTeresa Johnson2017-01-055-117/+97
| | | | | | | | | | | | | | | | | | | Summary: This adds a new summary flag NotEligibleToImport that subsumes several existing flags (NoRename, HasInlineAsmMaybeReferencingInternal and IsNotViableToInline). It also subsumes the checking of references on the summary that was being done during the thin link by eligibleForImport() for each candidate. It is much more efficient to do that checking once during the per-module summary build and record it in the summary. Reviewers: mehdi_amini Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28169 llvm-svn: 291108
* Currently isLikelyComplexAddressComputation tries to figure out if the given ↵Mohammed Agabaria2017-01-058-55/+51
| | | | | | | | | | | | | stride seems to be 'complex' and need some extra cost for address computation handling. This code seems to be target dependent which may not be the same for all targets. Passed the decision whether the given stride is complex or not to the target by sending stride information via SCEV to getAddressComputationCost instead of 'IsComplex'. Specifically at X86 targets we dont see any significant address computation cost in case of the strided access in general. Differential Revision: https://reviews.llvm.org/D27518 llvm-svn: 291106
* [GlobalISel] Add support for address-taken basic blocksKristof Beyls2017-01-051-1/+4
| | | | | | | | | | | | | | | | | To make this work, pointers from the MachineBasicBlock to the LLVM-IR-level basic blocks need to be initialized, as the AsmPrinter uses this link to be able to print out labels for the basic blocks that are address-taken. Most of the changes in this commit are about adapting existing tests to include the basic block name that is now printed out in the MIR format, now that the name becomes available as the link to the LLVM-IR basic block is initialized. The relevant test change for the functionality added in this patch are the added "(address-taken)" strings in test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll. Differential Revision: https://reviews.llvm.org/D28123 llvm-svn: 291105
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