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* Use uniqued StringInit pointers for lookups.Jakob Stoklund Olesen2012-01-132-21/+9
| | | | | | | This avoids a gazillion StringMap and dynamic_cast calls, making TableGen run 3x faster. llvm-svn: 148091
* DAGCombine's logic for forming pre- and post- indexed loads / stores were beingEvan Cheng2012-01-131-9/+44
| | | | | | | | | | | | | | | | overly conservative. It was concerned about cases where it would prohibit folding simple [r, c] addressing modes. e.g. ldr r0, [r2] ldr r1, [r2, #4] => ldr r0, [r2], #4 ldr r1, [r2] Change the logic to look for such cases which allows it to form indexed memory ops more aggressively. rdar://10674430 llvm-svn: 148086
* Fix off-by-one error.Bill Wendling2012-01-131-1/+1
| | | | llvm-svn: 148077
* Implement proper ObjC ARC objc_retainBlock "escape" analysis, so thatDan Gohman2012-01-131-45/+63
| | | | | | | | the optimizer doesn't eliminate objc_retainBlock calls which are needed for their side effect of copying blocks onto the heap. This implements rdar://10361249. llvm-svn: 148076
* Added MVT::v2f16Pete Cooper2012-01-121-0/+2
| | | | llvm-svn: 148067
* Revert accidental commit.Bill Wendling2012-01-121-65/+0
| | | | llvm-svn: 148065
* Fix the code that was WRONG.Bill Wendling2012-01-122-13/+71
| | | | | | | The registers are placed into the saved registers list in the reverse order, which is why the original loop was written to loop backwards. llvm-svn: 148064
* Added FPOW, FEXP, FLOG to PromoteNode so that custom actions can be set to ↵Pete Cooper2012-01-121-0/+18
| | | | | | | | Promote for those operations. Sorry, no test case yet llvm-svn: 148050
* Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failureElena Demikhovsky2012-01-121-1/+5
| | | | | | | lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&& "Op 1 of shuffle should not be undef"' failed. Added a test. llvm-svn: 148044
* When hoisting common code, watch out for uses which are marked "kill". If theEvan Cheng2012-01-121-0/+5
| | | | | | | | | | | killed registers are needed below the insertion point, then unset the kill marker. Sorry I'm not able to find a reduced test case. rdar://10660944 llvm-svn: 148043
* Support segmented stacks on 64-bit FreeBSD.Rafael Espindola2012-01-121-2/+8
| | | | | | | This patch uses tcb_spare field in the tcb structure to store info. Patch by Jyun-Yan You. llvm-svn: 148041
* Support segmented stacks on win32.Rafael Espindola2012-01-121-7/+17
| | | | | | | Uses the pvArbitrary slot of the TIB, which is reserved for applications. We only support frames with a static size. llvm-svn: 148040
* Allow targets to select source order pre-RA scheduler.Evan Cheng2012-01-121-1/+2
| | | | llvm-svn: 148033
* Rename X86ATTAsmParser -> X86AsmParserDevang Patel2012-01-122-19/+18
| | | | | | We are using one parser to parse att as well as intel style syntax. llvm-svn: 148032
* Make SplitAnalysis::UseSlots private.Jakob Stoklund Olesen2012-01-122-6/+10
| | | | llvm-svn: 148031
* After Jakob's r147938 exception handling on i386 was completely broken.Benjamin Kramer2012-01-121-0/+7
| | | | | | | | | Restore the (obviously wrong) behavior from before r147938 without relying on undefined behavior. Add a fat FIXME note. This should fix nightly tester failures. llvm-svn: 148030
* Fix a bug in the AVX 256-bit shuffle code in cases where the splat element ↵Nadav Rotem2012-01-121-1/+1
| | | | | | | | is on the boundary of two 128-bit vectors. The attached testcase was stuck in an endless loop. llvm-svn: 148027
* X86: Generalize the x << (y & const) optimization to also catch masks with ↵Benjamin Kramer2012-01-121-21/+25
| | | | | | more set bits set than 31 or 63. llvm-svn: 148024
* Add predicate method check match memory operand size, if available.Devang Patel2012-01-122-17/+96
| | | | | | In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction. llvm-svn: 148006
* A DenseMap of a std::map isn't a very good idea because the "grow()" method willBill Wendling2012-01-121-2/+2
| | | | | | | need to make a deep copy of each of the std::maps. Use a std::map of the std::map instead. This improves the compile time of sqlite3 by ~2%. llvm-svn: 148003
* Add intel style operand parser skeleton. Devang Patel2012-01-121-1/+97
| | | | | | This is a work in progress. llvm-svn: 148002
* Switch all of the uses of my InsertDAGNode helper to follow the exactChandler Carruth2012-01-121-8/+22
| | | | | | | | | | | | | | | | | | | | same pattern. We already had this pattern is a few places, but others tried to make a rough approximation of an actual DAG structure. As not everywhere went to this trouble, nothing could rely on this being done. In fact, I've checked all references to these node Ids, and the ones that are using the topo-sort properties are actually satisfied with a strict-weak-ordering. The requirement appears to be that Use >= Def. I've added a big blurb of comments to this bit of the transform to clarify why the order is so important for the next reader of the code. I'm starting with this change as it is very small, and trivially reverted if something breaks or the >= above really does need to be >. If that proves the case, we can hide the problem by reverting this patch, but the problem exists elsewhere as well, and so a more comprehensive solution will be needed. llvm-svn: 148001
* Revert r147978. A DenseMap's iterators may become invalidated here.Bill Wendling2012-01-111-1/+2
| | | | llvm-svn: 147980
* Make data structures private.Jakob Stoklund Olesen2012-01-113-11/+17
| | | | llvm-svn: 147979
* Use a DenseMap.Bill Wendling2012-01-111-2/+1
| | | | | | This appears to improve sqlite3's compile time by ~2%. llvm-svn: 147978
* Sink spillInterferences into RABasic.Jakob Stoklund Olesen2012-01-113-63/+62
| | | | | | This helper method is too simplistic for RAGreedy. llvm-svn: 147976
* Cleanup.Jakob Stoklund Olesen2012-01-111-9/+0
| | | | llvm-svn: 147975
* Move RegAllocBase into its own cpp file separate from RABasic.Jakob Stoklund Olesen2012-01-113-312/+336
| | | | | | No functional change. llvm-svn: 147972
* Re-fix the issue Bill fixed in r147899 in a slightly different way, which ↵Eli Friedman2012-01-111-5/+7
| | | | | | doesn't abuse the semantics of linker_private. We don't really want to merge any string constant with a weak_odr global. llvm-svn: 147971
* Fix assert.Eric Christopher2012-01-111-2/+2
| | | | llvm-svn: 147966
* Disable the crash reporter when running lit tests.Argyrios Kyrtzidis2012-01-112-1/+21
| | | | llvm-svn: 147965
* On AVX, we can load v8i32 at a time. The bug happens when two uneven loads ↵Nadav Rotem2012-01-111-5/+23
| | | | | | | | | | are used. When we load the v12i32 type, the GenWidenVectorLoads method generates two loads: v8i32 and v4i32 and attempts to use CONCAT_VECTORS to join them. In this fix I concat undef values to widen the smaller value. The test "widen_load-2.ll" also exposes this bug on AVX. llvm-svn: 147964
* Support segmented stacks on mac.Rafael Espindola2012-01-112-18/+68
| | | | | | | | This uses TLS slot 90, which actually belongs to JavaScriptCore. We only support frames with static size Patch by Brian Anderson. llvm-svn: 147960
* Generate the segmented stack prologue for fastcc too.Rafael Espindola2012-01-111-1/+2
| | | | | | Patch by Brian Anderson. llvm-svn: 147958
* Revert r147945 which disabled an addressing mode transformation. I hadChandler Carruth2012-01-111-4/+0
| | | | | | | | | hoped this would revive one of the llvm-gcc selfhost build bots, but it didn't so it doesn't appear that my transform is the culprit. If anyone else is seeing failures, please let me know! llvm-svn: 147957
* Use unsigned comparison in segmented stack prologue.Rafael Espindola2012-01-111-1/+1
| | | | | | | | This is a comparison of two addresses, and GCC does the comparison unsigned. Patch by Brian Anderson. llvm-svn: 147954
* [asan] extend the workaround for http://llvm.org/bugs/show_bug.cgi?id=11395: ↵Kostya Serebryany2012-01-111-1/+1
| | | | | | don't instrument the function at all on x86_32 if it has a large asm blob llvm-svn: 147953
* Explicitly set the scale to 1 on some segstack prologue instrs.Rafael Espindola2012-01-112-4/+4
| | | | | | Patch by Brian Anderson. llvm-svn: 147952
* The error check for using -g with a .s file already containing dwarf .fileKevin Enderby2012-01-111-4/+4
| | | | | | | directives was in the wrong place and getting triggered incorectly with a cpp .file directive. This change fixes that and adds a test case. llvm-svn: 147951
* Add XOP Intrinsics and testsJan Sjödin2012-01-111-73/+662
| | | | llvm-svn: 147949
* Fix a bug in the lowering of BUILD_VECTOR for AVX. SCALAR_TO_VECTOR does not ↵Nadav Rotem2012-01-111-4/+2
| | | | | | zero untouched elements. Use INSERT_VECTOR_ELT instead. llvm-svn: 147948
* Don't try to create a GEP when the pointee type is unsized (such GEPsDuncan Sands2012-01-111-1/+2
| | | | | | | are invalid). Fixes a crash on array1.C from the GCC testsuite when compiled with dragonegg. llvm-svn: 147946
* Disable the transformation I added in r147936 to see if it fixes someChandler Carruth2012-01-111-0/+4
| | | | | | | | strange build bot failures that look like a miscompile into an infloop. I'll investigate this tomorrow, but I'd both like to know whether my patch is the culprit, and get the bots back to green. llvm-svn: 147945
* Hoist a really redundant code pattern into a helper function, and deleteChandler Carruth2012-01-111-80/+29
| | | | | | lots of lines of code. No functionality changed. llvm-svn: 147942
* Simplify the AND-rooted mask+shift checking code to match that of theChandler Carruth2012-01-111-8/+6
| | | | | | SRL-rooted code. llvm-svn: 147941
* Unify the interface of the three mask+shift transform helpers, andChandler Carruth2012-01-111-26/+34
| | | | | | | factor the differences that were hiding in one of them into its other caller, the SRL handling code. No change in behavior. llvm-svn: 147940
* Clarify and make explicit some of the requirements for transformingChandler Carruth2012-01-111-52/+64
| | | | | | | | | | mask+shift pairs at the beginning of the ISD::AND case block, and then hoist the final pattern into a helper function, simplifying and reflowing it appropriately. This should have no observable behavior change, but several simplifications fell out of this such as directly computing the new mask constant, etc. llvm-svn: 147939
* Fix undefined code and reenable test case.Jakob Stoklund Olesen2012-01-111-2/+2
| | | | | | | I don't think the compact encoding code is right, but at least is has defined behavior now. llvm-svn: 147938
* Hoist the logic to transform shift+mask combinations into sub-registerChandler Carruth2012-01-111-56/+68
| | | | | | | | extracts and scaled addressing modes into its own helper function. No functionality changed here, just hoisting and layout fixes falling out of that hoisting. llvm-svn: 147937
* Teach the X86 instruction selection to do some heroic transforms toChandler Carruth2012-01-112-0/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | detect a pattern which can be implemented with a small 'shl' embedded in the addressing mode scale. This happens in real code as follows: unsigned x = my_accelerator_table[input >> 11]; Here we have some lookup table that we look into using the high bits of 'input'. Each entity in the table is 4-bytes, which means this implicitly gets turned into (once lowered out of a GEP): *(unsigned*)((char*)my_accelerator_table + ((input >> 11) << 2)); The shift right followed by a shift left is canonicalized to a smaller shift right and masking off the low bits. That hides the shift right which x86 has an addressing mode designed to support. We now detect masks of this form, and produce the longer shift right followed by the proper addressing mode. In addition to saving a (rather large) instruction, this also reduces stalls in Intel chips on benchmarks I've measured. In order for all of this to work, one part of the DAG needs to be canonicalized *still further* than it currently is. This involves removing pointless 'trunc' nodes between a zextload and a zext. Without that, we end up generating spurious masks and hiding the pattern. llvm-svn: 147936
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