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* Fixed comment in loop-unswitch.Stepan Dyatkovskiy2012-01-161-1/+1
| | | | llvm-svn: 148252
* Give better scavenger errors by invoking the verifier.Jakob Stoklund Olesen2012-01-161-1/+6
| | | | llvm-svn: 148251
* Add a new kind of MachineOperand: MO_RegisterMask.Jakob Stoklund Olesen2012-01-161-0/+5
| | | | | | | | | | | | | | | | | | | | | Register masks will be used as a compact representation of large clobber lists. Currently, an x86 call instruction has some 40 operands representing call-clobbered registers. That's more than 1kB of useless operands per call site. A register mask operand references a bit mask of call-preserved registers, everything else is clobbered. The bit mask will typically come from TargetRegisterInfo::getCallPreservedMask(). By abandoning ImplicitDefs for call-clobbered registers, it also becomes possible to share call instruction descriptions between calling conventions, and we can get rid of the WINCALL* instructions. This patch introduces the new operand kind. Future patches will add RegMask support to target-independent passes before finally the fixed clobber lists can be removed from call instruction descriptions. llvm-svn: 148250
* Make sure the non-SSE lowering for fences correctly clobbers EFLAGS. PR11768.Eli Friedman2012-01-161-1/+1
| | | | llvm-svn: 148240
* Get rid of unused codegen-only instruction.Eli Friedman2012-01-162-12/+0
| | | | llvm-svn: 148239
* Give priority to AVX over SSE for 128-bit floating point unpck instructions.Craig Topper2012-01-161-34/+34
| | | | llvm-svn: 148233
* A fix for the previous commit: "integer constant is too large for ‘long’ ↵Eli Bendersky2012-01-161-2/+2
| | | | | | type" error on some 32-bit bots llvm-svn: 148232
* Adding a basic ELF dynamic loader and MC-JIT for ELF. Functionality is ↵Eli Bendersky2012-01-164-5/+373
| | | | | | | | currently basic and will be enhanced with future patches. Patch developed by Andy Kaylor and Daniel Malea. Reviewed on llvm-commits. llvm-svn: 148231
* Refactor variables unused under non-assert builds (& remove two entirely ↵David Blaikie2012-01-162-4/+2
| | | | | | unused variables). llvm-svn: 148230
* Changed intrinsic ID operand to a target constant as its not used in any ↵Pete Cooper2012-01-161-1/+1
| | | | | | arithmetic so should not be checked in legalisation llvm-svn: 148228
* [AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.Nadav Rotem2012-01-152-6/+44
| | | | | | | | | | | We know that the blend instructions only use the MSB, so if the mask is sign-extended then we can convert it into a SHL instruction. This is a common pattern because the type-legalizer sign-extends the i1 type which is used by the LLVM-IR for the condition. Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL. llvm-svn: 148225
* Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through ↵Benjamin Kramer2012-01-154-94/+55
| | | | | | CodeGen. llvm-svn: 148218
* DAGCombiner: Deduplicate code.Benjamin Kramer2012-01-151-24/+14
| | | | llvm-svn: 148217
* Cosmetic patch for r148215.Stepan Dyatkovskiy2012-01-151-13/+0
| | | | llvm-svn: 148216
* Fixup for r148132. Type replacement for LoopsProperties: from DenseMap to ↵Stepan Dyatkovskiy2012-01-151-114/+180
| | | | | | | | | std::map, since we need to keep a valid pointer to properties of current loop. Message for r148132: LoopUnswitch: All helper data that is collected during loop-unswitch iterations was moved to separated class (LUAnalysisCache). llvm-svn: 148215
* Remove SetWorkingDirectory from the Process interface. Nothing in LLVMChandler Carruth2012-01-152-8/+0
| | | | | | | | | | | | or Clang is using this, and it would be hard to use it correctly given the thread hostility of the function. Also, it never checked the return which is rather dangerous with chdir. If someone was in fact using this, please let me know, as well as what the usecase actually is so that I can add it back and make it more correct and secure to use. (That said, it's never going to be "safe" per-se, but we could at least document the risks...) llvm-svn: 148211
* Remove dead code.David Blaikie2012-01-152-140/+79
| | | | llvm-svn: 148206
* Truncate of undef is just undef of smaller size.Craig Topper2012-01-151-5/+6
| | | | llvm-svn: 148205
* Fix the memop type on a couple 256-bit AVX instructions that were using ↵Craig Topper2012-01-141-4/+4
| | | | | | f128mem instead of f256mem. llvm-svn: 148196
* Add a bunch of AVX instructions to the folding tables. Also fixed the ↵Craig Topper2012-01-141-69/+139
| | | | | | alignment on 256-bit AVX2 instructions. llvm-svn: 148194
* Speculatively revert commit 148175 (rafael), to see if this fixesDuncan Sands2012-01-141-4/+2
| | | | | | | | non-determinism in the 32 bit dragonegg buildbot. Original commit message: Only emit the Leh_func_endN symbol when needed. llvm-svn: 148191
* Fix a corner case hit by redundant phi elimination running after LSR.Andrew Trick2012-01-141-1/+11
| | | | | | Fixes PR11761: bad IR w/ redundant Phi elim llvm-svn: 148177
* Only emit the Leh_func_endN symbol when needed.Rafael Espindola2012-01-141-2/+4
| | | | llvm-svn: 148175
* misched: Initial code for building an MI level scheduling DAGAndrew Trick2012-01-144-21/+113
| | | | llvm-svn: 148174
* Move physreg dependency generation into aptly named addPhysRegDeps.Andrew Trick2012-01-142-155/+182
| | | | llvm-svn: 148173
* misched: Added ScheduleDAGInstrs::IsPostRAAndrew Trick2012-01-144-11/+17
| | | | llvm-svn: 148172
* misched: Invoke the DAG builder on each sequence of schedulable instructions.Andrew Trick2012-01-141-6/+31
| | | | llvm-svn: 148171
* Move things around to make the file navigable, even though it will probably ↵Andrew Trick2012-01-141-19/+32
| | | | | | be split up later. llvm-svn: 148170
* After r147827 and r147902, it's now possible for unallocatable registers to beEvan Cheng2012-01-142-6/+27
| | | | | | | | | | | | | | | | | | | live across BBs before register allocation. This miscompiled 197.parser when a cmp + b are optimized to a cbnz instruction even though the CPSR def is live-in a successor. cbnz r6, LBB89_12 ... LBB89_12: ble LBB89_1 The fix consists of two parts. 1) Teach LiveVariables that some unallocatable registers might be liveouts so don't mark their last use as kill if they are. 2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional branch does not kill CPSR. rdar://10676853 llvm-svn: 148168
* Fix pasto from r146196.Chad Rosier2012-01-141-2/+2
| | | | llvm-svn: 148167
* Fix an unused variable warning that Chad noticed.Dan Gohman2012-01-141-1/+1
| | | | llvm-svn: 148164
* Remove previous commit while I debug the bot failures.Rafael Espindola2012-01-131-0/+3
| | | | llvm-svn: 148156
* Use RegisterTuples to generate pseudo-registers.Jakob Stoklund Olesen2012-01-134-45/+51
| | | | | | | | | | The QQ and QQQQ registers are not 'real', they are pseudo-registers used to model some vld and vst instructions. This makes the call clobber lists longer, but I intend to get rid of those soon. llvm-svn: 148151
* Remove label that is not used anymore.Rafael Espindola2012-01-131-3/+0
| | | | llvm-svn: 148150
* Speculatively revert r148132+r148133 to try and fix a buildbot failure.Eli Friedman2012-01-131-166/+115
| | | | llvm-svn: 148149
* Remove pointless mode line in .cpp file.Andrew Trick2012-01-131-1/+1
| | | | llvm-svn: 148143
* Revert r148131, it was committed before it was ready.Devang Patel2012-01-131-46/+40
| | | | llvm-svn: 148134
* Cosmetic patch for r148132.Stepan Dyatkovskiy2012-01-131-13/+1
| | | | llvm-svn: 148133
* LoopUnswitch: All helper data that is collected during loop-unswitch ↵Stepan Dyatkovskiy2012-01-131-112/+175
| | | | | | iterations was moved to separated class (LUAnalysisCache). llvm-svn: 148132
* Refactor.Devang Patel2012-01-131-40/+46
| | | | llvm-svn: 148131
* Convert SHUFPD with the same register for both sources to PSHUFD if it would ↵Craig Topper2012-01-132-1/+20
| | | | | | prevent a register copy. Similar to SHUFPS, but requires the mask to be converted. llvm-svn: 148112
* use v8i32 as optimal mem type over v8f32 if AVX2 is enabled. Similar to SSE2 ↵Craig Topper2012-01-131-3/+6
| | | | | | vs SSE1. llvm-svn: 148109
* Make X86 instruction selection use 256-bit VPXOR for build_vector of all ↵Craig Topper2012-01-134-37/+62
| | | | | | ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32. llvm-svn: 148108
* Add patterns for v16i16 and v32i8 immAllZerosV to select VPXOR to match ↵Craig Topper2012-01-131-0/+8
| | | | | | v4i64 and v8i32. llvm-svn: 148106
* Added the MachineSchedulerPass skeleton.Andrew Trick2012-01-136-1/+251
| | | | llvm-svn: 148105
* wrong filenameAndrew Trick2012-01-131-1/+1
| | | | llvm-svn: 148103
* 80-col violationAndrew Trick2012-01-131-3/+3
| | | | llvm-svn: 148102
* Use 8i32 constant pool entry for converting AVX2_SETALLONES. Possibly fixes ↵Craig Topper2012-01-131-0/+2
| | | | | | PR11750. llvm-svn: 148101
* Fix typo in PerformAddCombine that caused any vector type to be checked for ↵Craig Topper2012-01-131-1/+1
| | | | | | horizontal add/sub if AVX2 is enabled. This caused an assert to fail for non 128/256-bit vectors when done before type legalizing. Fixes PR11749. llvm-svn: 148096
* Delete CodeInit and CodeRecTy from TableGen.Jakob Stoklund Olesen2012-01-132-33/+3
| | | | | | | The code type was always identical to a string anyway. Now it is simply a synonym. The code literal syntax [{...}] is still valid. llvm-svn: 148092
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