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* Delete an unused member variable.Jakob Stoklund Olesen2012-01-202-2/+0
| | | | llvm-svn: 148594
* Fix inverted condition.Jim Grosbach2012-01-201-1/+1
| | | | llvm-svn: 148593
* Intel syntax: Robustify register parsing.Devang Patel2012-01-201-28/+16
| | | | llvm-svn: 148591
* Support register masks in MachineLICM.Jakob Stoklund Olesen2012-01-201-23/+36
| | | | | | Only PostRA LICM is affected. llvm-svn: 148589
* Handle register masks in DeadMachineInstructionElim.Jakob Stoklund Olesen2012-01-201-0/+7
| | | | | | Don't track live physregs that are clobbered by a register mask operand. llvm-svn: 148588
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-20106-435/+177
| | | | llvm-svn: 148578
* Handle a corner case with IV chain collection with bailout instead of assert.Andrew Trick2012-01-201-2/+6
| | | | | | Fixes PR11783: bad cast to AddRecExpr. llvm-svn: 148572
* Intel syntax: Parse ... PTR [-8]Devang Patel2012-01-201-0/+5
| | | | llvm-svn: 148570
* Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.Devang Patel2012-01-201-1/+3
| | | | llvm-svn: 148569
* ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651>Bob Wilson2012-01-201-0/+3
| | | | | | | | We have patterns for vector sext and zext operations but were missing anyext. Without those patterns, codegen will fail when the selection DAG has any_extend nodes. llvm-svn: 148568
* TblGen diagnostic for mismatched template instantiation.Jim Grosbach2012-01-201-0/+4
| | | | | | | | | | | | | | | | | | Providing a template argment to a non-templatized class was crashing tblgen. Add a diagnostic. For example, $ cat bug.td class A; def B : A<0> { } $ llvm-tblgen bug.td bug.td:3:11: error: template argument provided to non-template class def B : A<0> { ^ llvm-svn: 148565
* VST2 four-register w/ update pseudos for fixed/register update.Jim Grosbach2012-01-201-6/+15
| | | | | | rdar://10724489 llvm-svn: 148560
* NEON use vmov.i32 to splat some f32 values into vectors.Jim Grosbach2012-01-202-36/+41
| | | | | | | | | | | For bit patterns that aren't representable using the 8-bit floating point representation for vmov.f32, but are representable via vmov.i32, treat the .f32 syntax as an alias. Most importantly, this covers the case 'vmov.f32 Vd, #0.0'. rdar://10616677 llvm-svn: 148556
* Extend Attributes to 64 bitsKostya Serebryany2012-01-2012-46/+58
| | | | | | | | | | | | | | | | | | | | | | | | | Problem: LLVM needs more function attributes than currently available (32 bits). One such proposed attribute is "address_safety", which shows that a function is being checked for address safety (by AddressSanitizer, SAFECode, etc). Solution: - extend the Attributes from 32 bits to 64-bits - wrap the object into a class so that unsigned is never erroneously used instead - change "unsigned" to "Attributes" throughout the code, including one place in clang. - the class has no "operator uint64 ()", but it has "uint64_t Raw() " to support packing/unpacking. - the class has "safe operator bool()" to support the common idiom: if (Attributes attr = getAttrs()) useAttrs(attr); - The CTOR from uint64_t is marked explicit, so I had to add a few explicit CTOR calls - Add the new attribute "address_safety". Doing it in the same commit to check that attributes beyond first 32 bits actually work. - Some of the functions from the Attribute namespace are worth moving inside the class, but I'd prefer to have it as a separate commit. Tested: "make check" on Linux (32-bit and 64-bit) and Mac (10.6) built/run spec CPU 2006 on Linux with clang -O2. This change will break clang build in lib/CodeGen/CGCall.cpp. The following patch will fix it. llvm-svn: 148553
* Add missing breaks to switch.Benjamin Kramer2012-01-201-13/+25
| | | | | | Found by the clang static analyzer. llvm-svn: 148543
* Remove a bunch of unused variable assignments.Benjamin Kramer2012-01-202-11/+3
| | | | | | Found by the clang static analyzer. llvm-svn: 148541
* Remove obviously invalid early exit that prevented analyzing ↵Benjamin Kramer2012-01-201-1/+0
| | | | | | | | ConstantAggregateZeros. Found by the clang static analyzer. llvm-svn: 148540
* Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. ↵Craig Topper2012-01-201-86/+86
| | | | | | As long as only a single lane of the source is used in the lane in the destination. This makes the splitting match much closer to what happens with 256-bit shuffles when AVX is disabled and only 128-bit XMM is allowed. llvm-svn: 148537
* Fix CountCodeReductionForAlloca to more accurately represent what SROA can andNick Lewycky2012-01-201-16/+60
| | | | | | | | can't handle. Also don't produce non-zero results for things which won't be transformed by SROA at all just because we saw the loads/stores before we saw the use of the address. llvm-svn: 148536
* SCEVExpander fixes. Affects LSR and indvars.Andrew Trick2012-01-203-126/+137
| | | | | | | | | | | | | | | | LSR has gradually been improved to more aggressively reuse existing code, particularly existing phi cycles. This exposed problems with the SCEVExpander's sloppy treatment of its insertion point. I applied some rigor to the insertion point problem that will hopefully avoid an endless bug cycle in this area. Changes: - Always used properlyDominates to check safe code hoisting. - The insertion point provided to SCEV is now considered a lower bound. This is usually a block terminator or the use itself. Under no cirumstance may SCEVExpander insert below this point. - LSR is reponsible for finding a "canonical" insertion point across expansion of different expressions. - Robust logic to determine whether IV increments are in "expanded" form and/or can be safely hoisted above some insertion point. Fixes PR11783: SCEVExpander assert. llvm-svn: 148535
* Add support for selecting 256-bit PALIGNR.Craig Topper2012-01-202-24/+81
| | | | llvm-svn: 148532
* When lowering the 'resume' instruction, look to see if we can eliminate theBill Wendling2012-01-201-2/+32
| | | | | | | | 'insertvalue' instructions that recreate the structure returned by the 'landingpad' instruction. Because the 'insertvalue' instruction isn't supported by FastISel, this can save a bit of time during -O0 compilation. llvm-svn: 148520
* Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff.Eli Friedman2012-01-202-3/+9
| | | | llvm-svn: 148513
* Silence warnings about mixing enums.Benjamin Kramer2012-01-191-3/+2
| | | | llvm-svn: 148495
* Add a dump() implementation for sub-instruction MCOperands.Owen Anderson2012-01-191-0/+2
| | | | llvm-svn: 148493
* Set the "tail" flag on pattern-matched objc_storeStrong calls.Dan Gohman2012-01-191-0/+32
| | | | | | rdar://10531041. llvm-svn: 148490
* Post process 'and', 'sub' instructions and select better encoding, if available.Devang Patel2012-01-191-0/+78
| | | | llvm-svn: 148489
* Actually, this code handles wrapped sets just fine. Noticed by inspection.Nick Lewycky2012-01-191-3/+1
| | | | llvm-svn: 148487
* Intel syntax: There is no need to create unary expr for simple negative ↵Devang Patel2012-01-191-1/+1
| | | | | | displacement. llvm-svn: 148486
* Post process 'xor', 'or' and 'cmp' instructions and select better encoding, ↵Devang Patel2012-01-191-0/+114
| | | | | | if available. llvm-svn: 148485
* Emit ARM EHABI unwinding instructions for 3 more Thumb instructions.Evgeniy Stepanov2012-01-191-0/+3
| | | | llvm-svn: 148473
* Folding table additions and fixes for AVX.Craig Topper2012-01-191-9/+21
| | | | llvm-svn: 148467
* Merge 128-bit and 256-bit SHUFPS/SHUFPD handling.Craig Topper2012-01-193-129/+80
| | | | llvm-svn: 148466
* More bundle related API additions.Evan Cheng2012-01-191-1/+52
| | | | llvm-svn: 148465
* Rewriter should definitly rewrite instructions inside bundles.Evan Cheng2012-01-191-2/+2
| | | | llvm-svn: 148464
* Enhance finalizeBundle to return end of bundle iterator because it makes sense.Evan Cheng2012-01-191-3/+6
| | | | llvm-svn: 148462
* ARM assembly diagnostic caret in better position for FPImm.Jim Grosbach2012-01-191-3/+4
| | | | llvm-svn: 148459
* Thumb2 relaxation for tADR to t2ADR.Jim Grosbach2012-01-191-0/+2
| | | | llvm-svn: 148456
* Add comment and fix range check in condition.Jim Grosbach2012-01-191-1/+3
| | | | llvm-svn: 148455
* - Slight change to finalizeBundle() interface. LastMI is not exclusive (pointingEvan Cheng2012-01-192-4/+20
| | | | | | | | | | | to instruction right after the last instruction in the bundle. - Add a finalizeBundle() variant that doesn't specify LastMI. Instead, the code will find the last instruction in the bundle by following the 'InsideBundle' marker. This is useful in case bundles are formed early (i.e. during MI scheduling) but finalized later (i.e. after register allocator has finished rewriting virtual registers with physical registers). llvm-svn: 148444
* Add a TargetOption for disabling tail calls.Nick Lewycky2012-01-191-1/+4
| | | | llvm-svn: 148442
* Rename Finalizebundle to finalizeBundle to conform to coding guideline.Evan Cheng2012-01-192-3/+3
| | | | llvm-svn: 148440
* Add experimental -x86-use-regmask command line option.Jakob Stoklund Olesen2012-01-181-0/+12
| | | | | | | | It adds register mask operands to x86 call instructions. Once all the backend passes support register mask operands, this will be permanently enabled. llvm-svn: 148438
* Ignore register mask operands when lowering instructions to MC.Jakob Stoklund Olesen2012-01-186-1/+17
| | | | | | | This is similar to implicit register operands. MC doesn't understand register liveness and call clobbers. llvm-svn: 148437
* Add a RegisterMaskSDNode class.Jakob Stoklund Olesen2012-01-184-2/+22
| | | | | | | | | | | This SelectionDAG node will be attached to call nodes by LowerCall(), and eventually becomes a MO_RegisterMask MachineOperand on the MachineInstr representing the call instruction. LowerCall() will attach a register mask that depends on the calling convention. llvm-svn: 148436
* Add support for the gnueabihf environment. Patch by Sylvestre Ledru.Rafael Espindola2012-01-181-0/+3
| | | | llvm-svn: 148434
* Thumb2 alternate syntax for LDR(literal) and friends.Jim Grosbach2012-01-183-0/+69
| | | | | | | | Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]". rdar://10250964 llvm-svn: 148432
* Process instructions after match to select alternative encoding which may be ↵Devang Patel2012-01-181-16/+87
| | | | | | more desirable. llvm-svn: 148431
* Replace FIXME with explanatory comment.Jim Grosbach2012-01-181-1/+2
| | | | llvm-svn: 148427
* Thumb2 relaxation for LDR(literal).Jim Grosbach2012-01-181-9/+20
| | | | | | | | | If the fixup is out of range for the Thumb1 instruction, relax it to the Thumb2 encoding instead. rdar://10711829 llvm-svn: 148424
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