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* Revert r148901 because it crashes llvm tests.Argyrios Kyrtzidis2012-01-251-55/+28
| | | | | | | | Original log: Introduce a new ConstantVector::getSplat constructor function to simplify a really common case. llvm-svn: 148906
* Introduce a new ConstantVector::getSplat constructor function to Chris Lattner2012-01-251-28/+55
| | | | | | simplify a really common case. llvm-svn: 148901
* Add class MipsAnalyzeImmediate which comes up with an instruction sequence toAkira Hatanaka2012-01-252-0/+215
| | | | | | load an immediate. llvm-svn: 148900
* Remove the Type::getNumElements() method, which is only called in 4 places,Chris Lattner2012-01-253-15/+19
| | | | | | | did something extremely surprising, and shadowed actually useful implementations that had completely different behavior. llvm-svn: 148898
* Use the right method to get the # elements in a CDS.Chris Lattner2012-01-254-7/+7
| | | | llvm-svn: 148897
* NEON VLD4(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-254-2/+215
| | | | llvm-svn: 148884
* Tidy up. Rename VLD4DUP patterns for consistency.Jim Grosbach2012-01-241-6/+6
| | | | llvm-svn: 148883
* NEON VLD3(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-244-6/+212
| | | | llvm-svn: 148882
* Set correct <def,undef> flags when lowering REG_SEQUENCE.Jakob Stoklund Olesen2012-01-241-0/+46
| | | | | | | | | | | | | | | | | | | | A REG_SEQUENCE instruction is lowered into a sequence of partial defs: %vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0 %vreg7:ssub_1<def> = COPY %vreg2 %vreg7:ssub_2<def> = COPY %vreg2 %vreg7:ssub_3<def> = COPY %vreg2 The first def needs an <undef> flag to indicate it is the beginning of the live range, while the other defs are read-modify-write. Previously, we depended on LiveIntervalAnalysis to notice and fix the missing <def,undef>, but that solution was never robust, it was causing problems with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE instructions. This fixes PR11841. llvm-svn: 148879
* Use the standard MachineFunction::print() after SlotIndexes.Jakob Stoklund Olesen2012-01-241-1/+1
| | | | llvm-svn: 148878
* Sign-extend 32-bit integer arguments when they are passed in 64-bit registers,Akira Hatanaka2012-01-241-1/+4
| | | | | | which is what N32/64 does. llvm-svn: 148875
* Pass CCState by reference.Akira Hatanaka2012-01-241-1/+1
| | | | llvm-svn: 148871
* Pattern for f32 to i64 conversion.Akira Hatanaka2012-01-241-0/+1
| | | | llvm-svn: 148869
* ARM Darwin symbol ref differences w/o subsection-via-symbols.Jim Grosbach2012-01-241-1/+2
| | | | | | | | When not using subsections via symbols, the assembler can resolve symbol differences (including pcrel references) to non-local labels at assembly time, not just those in the same atom. llvm-svn: 148865
* Intel Syntax: Extend special hand coded logic, to recognize special ↵Devang Patel2012-01-241-5/+15
| | | | | | instructions, for intel syntax. llvm-svn: 148864
* 64-bit sign extension in register instructions.Akira Hatanaka2012-01-242-5/+10
| | | | llvm-svn: 148862
* Sink assert-only variables into the assertsMatt Beaumont-Gay2012-01-241-16/+10
| | | | llvm-svn: 148849
* [asan] enable asan only for the functions that have Attribute::AddressSafetyKostya Serebryany2012-01-241-0/+1
| | | | llvm-svn: 148846
* NEON VST4(one lane) assembly parsing and encoding.Jim Grosbach2012-01-242-0/+148
| | | | llvm-svn: 148836
* Widen the instruction encoder that TblGen emits to a 64 bits, which should ↵Owen Anderson2012-01-247-7/+7
| | | | | | accomodate every target I can think of offhand. llvm-svn: 148833
* NEON VLD4(one lane) assembly parsing and encoding.Jim Grosbach2012-01-242-0/+245
| | | | llvm-svn: 148832
* Fix old doxygen comment.Jakob Stoklund Olesen2012-01-241-2/+1
| | | | llvm-svn: 148825
* NEON Two-operand assembly aliases for VSRA.Jim Grosbach2012-01-241-0/+39
| | | | llvm-svn: 148821
* NEON Two-operand assembly aliases for VSLI.Jim Grosbach2012-01-241-0/+19
| | | | llvm-svn: 148819
* NEON Two-operand assembly aliases for VSRI.Jim Grosbach2012-01-241-0/+19
| | | | llvm-svn: 148818
* NEON add correct predicates for some asm aliases.Jim Grosbach2012-01-242-18/+27
| | | | llvm-svn: 148815
* basic instcombine support for CDS.Chris Lattner2012-01-242-14/+32
| | | | llvm-svn: 148806
* C++, CBE, and TLOF support for ConstantDataSequentialChris Lattner2012-01-244-20/+125
| | | | llvm-svn: 148805
* Rearrange argument order of ::get methods so that LLVMContext comes first,Chris Lattner2012-01-241-14/+28
| | | | | | | | add a ConstantDataArray::getString method that corresponds to the (to be removed) StringRef version of ConstantArray::get, but is dramatically more efficient. llvm-svn: 148804
* ZERO_EXTEND operation is optimized for AVX.Elena Demikhovsky2012-01-241-2/+37
| | | | | | v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions. llvm-svn: 148803
* add more support for ConstantDataSequentialChris Lattner2012-01-244-34/+75
| | | | llvm-svn: 148802
* An option to selectively enable part of ARM EHABI support.Evgeniy Stepanov2012-01-241-5/+14
| | | | | | | | This change adds an new option --arm-enable-ehabi-descriptors that enables emitting unwinding descriptors. This provides a mode with a working backtrace() without the (currently broken) exception support. llvm-svn: 148800
* Bit pack DIE structures better.Benjamin Kramer2012-01-241-23/+23
| | | | | | 16 bits are sufficient to store attributes, tags and forms. llvm-svn: 148799
* Remove generation of DW_AT_sibling. Nothing as far as I can tell uses it.Eric Christopher2012-01-243-26/+0
| | | | | | | | Saves about 1.5% on debug info size. rdar://10278198 llvm-svn: 148794
* Add AsmPrinter (aka MCLowering) support for ConstantDataSequential, Chris Lattner2012-01-242-44/+97
| | | | | | | | and clean up some other misc stuff. Unlike ConstantArray, we will prefer to emit .fill directives for "String" arrays that all have the same value, since they are denser than emitting a .ascii llvm-svn: 148793
* Add various "string" methods to ConstantDataSequential, which have theChris Lattner2012-01-241-0/+27
| | | | | | | | same semantics as ConstantArray's but much more efficient because they don't have to return std::string's. The ConstantArray methods will eventually be removed. llvm-svn: 148792
* teach valuetracking about ConstantDataSequentialChris Lattner2012-01-242-31/+65
| | | | llvm-svn: 148790
* switch SCEV to use the new ConstantFoldLoadThroughGEPIndices functionChris Lattner2012-01-241-35/+3
| | | | | | | | instead of its own hard coded thing, allowing it to handle ConstantDataSequential and fixing some obscure bugs (e.g. it would previously crash on a CAZ of vector type). llvm-svn: 148788
* Split the interesting bits of ConstantFoldLoadThroughGEPConstantExprChris Lattner2012-01-241-43/+56
| | | | | | | | | | out into a new ConstantFoldLoadThroughGEPIndices (more useful) function and rewrite it to be simpler, more efficient, and to handle the new ConstantDataSequential type. Enhance ConstantFoldLoadFromConstPtr to handle ConstantDataSequential. llvm-svn: 148786
* Add some accessor methods to CAZ and UndefValue that help simplify clients.Chris Lattner2012-01-241-6/+60
| | | | | | Make some CDS methods public. llvm-svn: 148785
* Use correct register class for am2offset register operands.Anton Korobeynikov2012-01-241-2/+2
| | | | | | This pacifies machine verifier llvm-svn: 148782
* Preserve <def,undef> flags in CoalesceExtSubRegs.Jakob Stoklund Olesen2012-01-241-3/+7
| | | | | | | This won't have an effect until EliminateRegSequences() starts setting the undef flags. llvm-svn: 148779
* implement the ConstantDataSequential accessor methods.Chris Lattner2012-01-241-3/+93
| | | | | | No need for 'getOperand' :) llvm-svn: 148778
* Add comments near load pattern fragments indicating that all integer vector ↵Craig Topper2012-01-241-0/+6
| | | | | | loads are promoted to v2i64 or v4i64 so that no one tries to reintroduce pattern fragments for other types. llvm-svn: 148771
* NEON VST4(multiple 4 element structures) assembly parsing.Jim Grosbach2012-01-242-0/+157
| | | | llvm-svn: 148764
* NEON VLD4(multiple 4 element structures) assembly parsing.Jim Grosbach2012-01-244-0/+179
| | | | llvm-svn: 148762
* Tidy up. Remove some vertical space for readability.Jim Grosbach2012-01-241-344/+121
| | | | llvm-svn: 148761
* Revert r148686 (and r148694, a fix to it) due to a serious layeringChandler Carruth2012-01-243-25/+12
| | | | | | | | | | | | | | | | | | violation -- MC cannot depend on CodeGen. Specifically, the MCTargetDesc component of each target is actually a subcomponent of the MC library. As such, it cannot depend on the target-independent code generator, because MC itself cannot depend on the target-independent code generator. This change moved a flag from the ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in ARMException.cpp, leaving behind an 'extern' to refer back to it. That layering order isn't viable givin the constraints outlined above. Commandline flags are designed to be static specifically to avoid these types of bugs. Fixing this is likely going to require some non-trivial refactoring. llvm-svn: 148759
* Fix typo.Jim Grosbach2012-01-241-2/+2
| | | | llvm-svn: 148757
* NEON VST3(single element from one lane) assembly parsing.Jim Grosbach2012-01-242-0/+176
| | | | llvm-svn: 148755
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