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* R600: Consolidate sub register indices.Tom Stellard2013-02-078-93/+73
| | | | | | | | | | Use sub0-15 everywhere. Patch by: Michel Dänzerr Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 174610
* R600: Add support for SET*_DX10 instructionsTom Stellard2013-02-072-29/+131
| | | | | | | | | | | These instructions compare two floating point values and return an integer true (-1) or false (0) value. When compiling code generated by the Mesa GLSL frontend, the SET*_DX10 instructions save us four instructions for most branch decisions that use floating-point comparisons. llvm-svn: 174609
* R600: Fix assembly name for SETGT_INTTom Stellard2013-02-071-1/+1
| | | | llvm-svn: 174607
* FDE::dumpHeader(): Forgot to fix one more formatting. It affected bigendian ↵NAKAMURA Takumi2013-02-071-2/+3
| | | | | | hosts. llvm-svn: 174602
* Make sure we call externals from libraries properly when -static.Reed Kotler2013-02-071-0/+3
| | | | | | For example, when we are doing mips16 hard float or soft float. llvm-svn: 174583
* tblgen: Diagnose duplicate includes.Sean Silva2013-02-074-10/+23
| | | | | | | | | | | | | | | A double inclusion will pretty much always be an error in TableGen, so there's no point going on just to die with "def already defined" or whatnot. I'm not too thrilled about the "public: ... private: ..." to expose the DependenciesMapTy, but I really didn't see a better way to keep that type centralized. It's a smell that indicates that some refactoring is needed to make this code more loosely coupled. This should avoid all bugs of the same nature as PR15189. llvm-svn: 174582
* Moved some comments due to the recent refactoring of ObjCARC.Michael Gottesman2013-02-072-5/+4
| | | | | | | | 1. Moved a comment from ObjCARCOpts.cpp -> ObjCARCContract.cpp. 2. Removed a comment from ObjCARCOpts.cpp that was already moved to ObjCARCAliasAnalysis.h/.cpp. llvm-svn: 174581
* Enable jumps when in -static mode.Reed Kotler2013-02-071-1/+1
| | | | llvm-svn: 174580
* DWARFDebugFrame.cpp: Fix formatting on i686 hosts.NAKAMURA Takumi2013-02-071-3/+6
| | | | | FIXME: Are they really truncated to i32 from i64 unconditionally? llvm-svn: 174574
* Preserve fast-math flags after reassociation and commutation. Update test casesMichael Ilseman2013-02-071-5/+20
| | | | llvm-svn: 174571
* Conditionalize constant folding of math intrinsics on the availability of an ↵Owen Anderson2013-02-071-0/+10
| | | | | | implementation on the host. This is a little bit unfortunate, but until someone decides to implement a full libm for APFloat, we don't have a better way to get this functionality. llvm-svn: 174561
* Signficantly generalize our ability to constant fold floating point ↵Owen Anderson2013-02-061-14/+88
| | | | | | intrinsics, including ones on half types. llvm-svn: 174555
* Code Custodian (trivial whitespace cleanup)Joe Abbey2013-02-062-67/+66
| | | | llvm-svn: 174550
* Clean up multiple skeleton compile units if we have multiple compileEric Christopher2013-02-062-8/+6
| | | | | | units coming in. llvm-svn: 174548
* Remove some dead code.Eric Christopher2013-02-062-34/+0
| | | | llvm-svn: 174547
* [mips] Make NOP a pseudo instruction and expand it to "sll $zero, $zero, 0".Akira Hatanaka2013-02-063-15/+7
| | | | llvm-svn: 174546
* This is a follow-up on r174446, now taking Atom processors intoEli Bendersky2013-02-061-6/+6
| | | | | | | | | | | | account. Atoms use LEA for updating SP in prologs/epilogs, and the exact LEA opcode depends on the data model. Also reapplying the test case which was added and then reverted (because of Atom failures), this time specifying explicitly the CPU in addition to the triple. The test case now checks all variations (data mode, cpu Atom vs. Core). llvm-svn: 174542
* PPC calling convention cleanup.Bill Schmidt2013-02-062-75/+46
| | | | | | | | Most of PPCCallingConv.td is used only by the 32-bit SVR4 ABI. Rename things to clarify this. Also delete some code that's been commented out for a long time. llvm-svn: 174526
* R600: Support for indirect addressing v4Tom Stellard2013-02-0630-75/+1124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines llvm-svn: 174525
* Implement external weak (ELF) symbols on AArch64Tim Northover2013-02-062-4/+17
| | | | | | | | | Weakly defined symbols should evaluate to 0 if they're undefined at link-time. This is impossible to do with the usual address generation patterns, so we should use a literal pool entry to materlialise the address. llvm-svn: 174518
* Add some comments to new frame entriesEli Bendersky2013-02-061-0/+4
| | | | llvm-svn: 174515
* Add AArch64 CRC32 instructionsTim Northover2013-02-061-1/+19
| | | | | | | | These instructions are a late addition to the architecture, and may yet end up behind an optional attribute, but for now they're available at all times. llvm-svn: 174496
* Add icache prefetch operations to AArch64Tim Northover2013-02-062-0/+12
| | | | | | | This adds hints to the various "prfm" instructions so that they can affect the instruction cache as well as the data cache. llvm-svn: 174495
* Initial submission for the attribute group feature.Bill Wendling2013-02-065-41/+167
| | | | | | | | | | | | | | | | | Attribute groups are of the form: #0 = attributes { noinline "no-sse" "cpu"="cortex-a8" alignstack=4 } Target-dependent attributes are represented as strings. Attributes can have optional values associated with them. E.g., the "cpu" attribute has the value "cortex-a8". Target-independent attributes are listed as enums inside the attribute classes. Multiple attribute groups can be referenced by the same object. In that case, the attributes are merged together. llvm-svn: 174493
* Remove extra blank line between closing curly brace and 'else'Craig Topper2013-02-061-6/+3
| | | | llvm-svn: 174492
* Remove unused private field to suppress a build warning.Craig Topper2013-02-061-1/+0
| | | | llvm-svn: 174491
* ARM: Use MCTargetAsmParser::validateTargetOperandClass().Jim Grosbach2013-02-061-47/+19
| | | | | | | | | | | Use the validateTargetOperandClass() hook to match literal '#0' operands in InstAlias definitions. Previously this required per-instruction C++ munging of the operand list, but not is handled as a natural part of the matcher. Much better. No additional tests are required, as the pre-existing tests for these instructions exercise the new behaviour as being functionally equivalent to the old. llvm-svn: 174488
* Failing builds because a private class member is not being used afterEli Bendersky2013-02-061-0/+3
| | | | | | initialization is one of the reasons I consider -werror to be shoddy. llvm-svn: 174485
* Add virtual desctructor to FrameEntry to avoid error on delete-non-virtual-dtorEli Bendersky2013-02-061-0/+9
| | | | llvm-svn: 174483
* Tweak check to avoid integer overflow (for insanely large alignments)Evan Cheng2013-02-061-2/+2
| | | | llvm-svn: 174482
* Add a 'StringRef' version of hasAttribute.Bill Wendling2013-02-061-4/+16
| | | | | | | Fix the 'operator==' and 'hasAttributes' queries to take into account target-dependent attributes. llvm-svn: 174481
* Add methods to merge an AttrBuilder into another builder.Bill Wendling2013-02-061-0/+17
| | | | | | | | This is useful when parsing an object that references multiple attribute groups. N.B. If both builders have alignments specified, then they should match! llvm-svn: 174480
* Attempt to recover gdb bot after r174445.Manman Ren2013-02-061-0/+2
| | | | | | | | | Failure: undefined symbol 'Lline_table_start0'. Root-cause: we use a symbol subtraction to calculate at_stmt_list, but the line table entries are not dumped in the assembly. Fix: use zero instead of a symbol subtraction for Compile Unit 0. llvm-svn: 174479
* Fix some formatting & add comments, following Eric's reviewEli Bendersky2013-02-061-12/+19
| | | | llvm-svn: 174473
* Add the target-dependent (string) attributes from the AttrBuilder to the ↵Bill Wendling2013-02-051-2/+13
| | | | | | AttributeSet. llvm-svn: 174467
* Add missing file to CMake listEli Bendersky2013-02-051-0/+1
| | | | llvm-svn: 174465
* Initial support for DWARF CFI parsing and dumping in LLVMEli Bendersky2013-02-054-1/+281
| | | | llvm-svn: 174463
* Convert to storing the attribute's internals as enums, integers, and strings.Bill Wendling2013-02-052-127/+251
| | | | | | | | The stuff we're handing are all enums (Attribute::AttrKind), integers and strings. Don't convert them to Constants, which is an unnecessary step here. The rest of the changes are mostly mechanical. llvm-svn: 174456
* Make sure the correct opcodes are used to SUB and ADD the stackEli Bendersky2013-02-051-13/+18
| | | | | | | pointer in function prologs/epilogs. The opcodes should depend on the data model (LP64 vs. ILP32) rather than the architecture bit-ness. llvm-svn: 174446
* Dwarf: support for LTO where a single object file can have multiple line tablesManman Ren2013-02-053-15/+61
| | | | | | | | | We generate one line table for each compilation unit in the object file. Reviewed by Eric and Kevin. rdar://problem/13067005 llvm-svn: 174445
* [mips] Do not use function CC_MipsN_VarArg unless the function being analyzedAkira Hatanaka2013-02-051-1/+1
| | | | | | | | | | | is a vararg function. The original code was examining flag OutputArg::IsFixed to determine whether CC_MipsN_VarArg or CC_MipsN should be called. This is not correct, since this flag is often set to false when the function being analyzed is a non-variadic function. llvm-svn: 174442
* InstCombine: Fix and simplify the inttoptr side too.Benjamin Kramer2013-02-051-13/+8
| | | | llvm-svn: 174438
* Removed explicit inline as per the LLVM style guide.Michael Gottesman2013-02-051-7/+7
| | | | llvm-svn: 174432
* Reapply r174343, with a fix for a scary DAG combine bug where it failed to ↵Owen Anderson2013-02-051-2/+5
| | | | | | | | | | | | | | | | | | differentiate between the alignment of the base point of a load, and the overall alignment of the load. This caused infinite loops in DAG combine with the original application of this patch. ORIGINAL COMMIT LOG: When the target-independent DAGCombiner inferred a higher alignment for a load, it would replace the load with one with the higher alignment. However, it did not place the new load in the worklist, which prevented later DAG combines in the same phase (for example, target-specific combines) from ever seeing it. This patch corrects that oversight, and updates some tests whose output changed due to slightly different DAGCombine outputs. llvm-svn: 174431
* InstCombine: Harden code to work with vectors of pointers and simplify it a bit.Benjamin Kramer2013-02-051-11/+7
| | | | | | Found by running instcombine on a fabricated test case for the constant folder. llvm-svn: 174430
* Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handleJyotsna Verma2013-02-052-1/+214
| | | | | | zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns. llvm-svn: 174429
* ConstantFolding: Fix a crash when encoutering a truncating inttoptr.Benjamin Kramer2013-02-051-3/+7
| | | | | | This was introduced in r173293. llvm-svn: 174424
* Loop Vectorizer: Refactor code to compute vectorized memory instruction costArnold Schwaighofer2013-02-051-79/+178
| | | | | | | Introduce a helper class that computes the cost of memory access instructions. No functionality change intended. llvm-svn: 174422
* [SjLj Prepare] When demoting an invoke instructions to the stack, if the normalChad Rosier2013-02-051-5/+15
| | | | | | | edge is critical, then split it so we can insert the store. rdar://13126179 llvm-svn: 174418
* Remove liveout lists from MachineRegisterInfo.Jakob Stoklund Olesen2013-02-053-16/+2
| | | | | | | | All targets are now adding return value registers as implicit uses on return instructions, and there is no longer a need for the live out lists. llvm-svn: 174417
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