summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* Remove modifierType/Base from X86 disassembler tables as they are no longer ↵Craig Topper2014-01-011-3/+0
| | | | | | used. Removes ~11.5K from static tables. llvm-svn: 198284
* [SparcV9]: Custom lower UMULO/SMULO so that the arguments are send to ↵Venkatraman Govindaraju2014-01-011-0/+52
| | | | | | __multi3() in correct order. llvm-svn: 198281
* [SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL ↵Venkatraman Govindaraju2014-01-011-2/+2
| | | | | | does not clear top 32 bit, only SRL does. llvm-svn: 198280
* X86Disassembler.cpp: Prune stray @return on translateFPRegister(). ↵NAKAMURA Takumi2014-01-011-1/+0
| | | | | | [-Wdocumentation] llvm-svn: 198279
* Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are ↵Craig Topper2014-01-014-52/+10
| | | | | | really more like OrRegFrm so we don't need a difference since we can just mask bits. llvm-svn: 198278
* AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmpElena Demikhovsky2014-01-018-63/+273
| | | | | | | Printing rounding control. Enncoding for EVEX_RC (rounding control). llvm-svn: 198277
* Second attempt at Removing special form of AddRegFrm used by FP ↵Craig Topper2014-01-014-83/+68
| | | | | | instructions. These instructions can be handled by MRMXr instead. llvm-svn: 198276
* Fold vector selects with undef elements in the condition. Fixes PR18319.Nick Lewycky2013-12-311-6/+15
| | | | | | Patch by Ilia Filippov! llvm-svn: 198267
* Revert r198238 and add FP disassembler tests. It didn't work and I didn't ↵Craig Topper2013-12-313-63/+76
| | | | | | realized we had no FP disassembler test cases. llvm-svn: 198265
* Remove old comment referring to an argument that no longer exists.Craig Topper2013-12-311-2/+0
| | | | llvm-svn: 198263
* Fix misaligned indentation in "if" block in MipsMCCodeEmitter.cppMark Seaborn2013-12-311-92/+92
| | | | llvm-svn: 198262
* Add missing MRM_XX forms to the old JIT emitter for consistency.Craig Topper2013-12-311-26/+39
| | | | llvm-svn: 198258
* Remove MRMInitReg form now that it's last use is gone.Craig Topper2013-12-314-36/+0
| | | | llvm-svn: 198257
* Silence g++ 4.9 build issueAlp Toker2013-12-311-2/+3
| | | | | | | | | lib/Support/ThreadLocal.cpp:53:15: error: typedef 'SIZE_TOO_BIG' locally defined but not used [-Werror=unused-local-typedefs] typedef int SIZE_TOO_BIG[sizeof(pthread_key_t) <= sizeof(data) ? 1 : -1]; Done the C++11 way, switching on and using LLVM_STATIC_ASSERT() instead of LLVM_ATTRIBUTE_UNUSED. llvm-svn: 198255
* Handle MOV32r0 in expandPostRAPseudo instead of MCInst lowering. No ↵Craig Topper2013-12-313-10/+4
| | | | | | functional change intended. llvm-svn: 198254
* Merge case statements to remove redundant code.Craig Topper2013-12-301-18/+12
| | | | llvm-svn: 198241
* Remove special form of AddRegFrm used by FP instructions. These instructions ↵Craig Topper2013-12-303-76/+63
| | | | | | can be handled by MRMXr instead. llvm-svn: 198238
* ARM IAS: account for predicated pre-UAL mnemonicsSaleem Abdulrasool2013-12-301-7/+26
| | | | | | | | Checking the trailing letter of the mnemonic is insufficient. Be more thorough in the scanning of the instruction to ensure that we correctly work with the predicated mnemonics. llvm-svn: 198235
* Refactor and reduce code duplication for non-split dwarf strings.Eric Christopher2013-12-301-18/+9
| | | | llvm-svn: 198233
* Revert r198208 and reapply:Eric Christopher2013-12-304-34/+52
| | | | | | | | | | r198196: Use a pointer to keep track of the skeleton unit for each normal unit and construct it up front. r198199: Reapply r198196 with a fix to zero initialize the skeleton pointer. r198202: Fix aranges and split dwarf by ensuring that the symbol and relocation back to the compile unit from the aranges section is to the skeleton unit and not the one in the dwo. with a fix to use integer 0 for DW_AT_low_pc since the relocation to the text section symbol was causing issues with COFF. Accordingly remove addLocalLabelAddress and machinery since we're not currently using it. llvm-svn: 198222
* Revert r198199 (and r198202). It broke 3 DebugInfo tests for targeting ↵NAKAMURA Takumi2013-12-304-75/+34
| | | | | | | | | | | | | | i686-cygming. r198196: Use a pointer to keep track of the skeleton unit for each normal unit and construct it up front. r198199: Reapply r198196 with a fix to zero initialize the skeleton pointer. r198202: Fix aranges and split dwarf by ensuring that the symbol and relocation back to the compile unit from the aranges section is to the skeleton unit and not the one in the dwo. They could be reproducible with explicit target. llvm/lib/MC/WinCOFFObjectWriter.cpp:224: bool {anonymous}::COFFSymbol::should_keep() const: Assertion `Section->Number != -1 && "Sections with relocations must be real!"' failed. llvm-svn: 198208
* Fix aranges and split dwarf by ensuring that the symbol and relocationEric Christopher2013-12-303-7/+23
| | | | | | | | | | | back to the compile unit from the aranges section is to the skeleton unit and not the one in the dwo. Do this by adding a method to grab a forwarded on local sym and local section by querying the skeleton if one exists and using that. Add a few tests to verify the relocations are back to the correct section. llvm-svn: 198202
* Keep comment with 'Subtarget' ivar.Bill Wendling2013-12-301-1/+1
| | | | llvm-svn: 198201
* Reapply r198196 with a fix to zero initialize the skeleton pointer.Eric Christopher2013-12-303-27/+52
| | | | llvm-svn: 198199
* Temporarily revert "Use a pointer to keep track of the skeleton unit forEric Christopher2013-12-303-51/+26
| | | | | | each normal unit" as it seems to be causing problems in the asan tests. llvm-svn: 198197
* Use a pointer to keep track of the skeleton unit for each normal unitEric Christopher2013-12-303-26/+51
| | | | | | | | | | | and construct it up front. Add address ranges at the end and a helper routine so that we're not needlessly using an indirction in the case of split dwarf. Update testcases according to the new ordering of attributes on the compile unit. llvm-svn: 198196
* For AArch64 Neon, simplify scalar dup by lane0 for fp.Jiangning Liu2013-12-301-17/+22
| | | | llvm-svn: 198194
* [AArch64]Add code to spill/fill Q register tuples such as QPair/QTriple/QQuad.Hao Liu2013-12-302-16/+69
| | | | llvm-svn: 198193
* [AArch64]Can't select shift left 0 of type v1i64Hao Liu2013-12-301-4/+10
| | | | llvm-svn: 198192
* Fix a bug in DAGcombiner about zero-extend after setcc.Kevin Qin2013-12-301-1/+2
| | | | | | | | | | For AArch64 backend, if DAGCombiner see "sext(setcc)", it will combine them together to a single setcc with extended value type. Then if it see "zext(setcc)", it assumes setcc is Vxi1, and try to create "(and (vsetcc), (1, 1, ...)". While setcc isn't Vxi1, DAGcombiner will create wrong node and get wrong code emitted. llvm-svn: 198190
* [AArch64]Fix the problem that can't select mul of v1i64/v2i64 types.Hao Liu2013-12-301-0/+12
| | | | | | | E.g. Can't select such IR: %tmp = mul <2 x i64> %a, %b llvm-svn: 198188
* Set LLVM_EXPORTED_SYMBOL_FILE in CMakeLists whose corresponding Makefiles do so.Nico Weber2013-12-291-0/+8
| | | | | | | | (unittests/ExecutionEngine/JIT/CMakeLists.txt is still missing for now, since it handles export files in a strange way: It generates a .exports file from a .def file instead of the other way round.) llvm-svn: 198183
* ARM IAS: fix after r198172Saleem Abdulrasool2013-12-291-21/+11
| | | | | | | | | The DPR and SPR register lists are also register lists. Furthermore, the registers need not be checked individually since the register type can be checked via the list kind. Use that to simplify the logic and fix the incorrect assertion. llvm-svn: 198174
* ARM: provide VFP aliases for pre-V6 mnemonicsSaleem Abdulrasool2013-12-292-1/+57
| | | | | | | In order to provide compatibility with the GNU assembler, provide aliases for pre-UAL mnemonics for floating point operations. llvm-svn: 198172
* ARM: fix a few typos in commentsSaleem Abdulrasool2013-12-292-2/+2
| | | | llvm-svn: 198171
* ARM: fix typo in VFP instruction definitionSaleem Abdulrasool2013-12-291-1/+1
| | | | | | | The vstm family of VFP instructions belong to the VFP store itinerary class, not the VFP load itinerary class. llvm-svn: 198170
* Fix indentation alignment of a declaration in MipsMCCodeEmitter.cppMark Seaborn2013-12-291-2/+2
| | | | llvm-svn: 198162
* Store the global variable that's created so that it's reclaimed afterwards.Bill Wendling2013-12-291-1/+3
| | | | | | | | This plugs a memory leak in ARM's FastISel by storing the GV in Module so that it's reclaimed. PR17978 llvm-svn: 198160
* [SparcV9] Use separate instruction patterns for 64 bit arithmetic ↵Venkatraman Govindaraju2013-12-293-40/+83
| | | | | | | | instructions instead of reusing 32 bit instruction patterns. This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot. llvm-svn: 198157
* [SparcV9] For codegen generated library calls that return float, set inreg ↵Venkatraman Govindaraju2013-12-291-0/+6
| | | | | | | | flag manually in LowerCall(). This makes the sparc backend to generate Sparc64 ABI compliant code. llvm-svn: 198149
* Make more of the x86 lowering helper functions static.Craig Topper2013-12-292-12/+11
| | | | llvm-svn: 198146
* [SparcV9]: Implement lowering of long double (fp128) arguments in Sparc64 ABI.Venkatraman Govindaraju2013-12-291-8/+60
| | | | | | Also, pass fp128 arguments to varargs through integer registers if necessary. llvm-svn: 198145
* Switch from EVT to MVT in more of the x86 instruction lowering code.Craig Topper2013-12-291-46/+44
| | | | llvm-svn: 198144
* CodeGen: silence a C++11 feature warningSaleem Abdulrasool2013-12-281-1/+1
| | | | llvm-svn: 198133
* ARM IAS: handle errors more appropriatelySaleem Abdulrasool2013-12-281-98/+176
| | | | | | | | | | | Directive parsers must return false if the target assembler is interested in handling the directive. The Error member function returns true always. Using the 'return Error()' pattern would incorrectly indicate to the general parser that the target was not interested in the directive, when in reality it simply encountered a badly formed directive or some other error. This corrects the behaviour to ensure that the parser behaves appropriately. llvm-svn: 198132
* Uninitialized variable (in never taken path) after factoring.Andrew Trick2013-12-281-1/+1
| | | | llvm-svn: 198131
* New machine model for cortex-a9. Schedule for resources and latency.Andrew Trick2013-12-281-2/+8
| | | | | | | | | Schedule more conservatively to account for stalls on floating point resources and latency. Use the AGU resource to model latency stalls since it's shared between FP and LD/ST instructions. This might not be completely accurate but should work well in practice. llvm-svn: 198125
* Added debugging options: -misched-only-func/blockAndrew Trick2013-12-281-0/+13
| | | | llvm-svn: 198124
* The Cortex-A9 machine model is incomplete. Mark it as such.Andrew Trick2013-12-281-0/+5
| | | | | | | | | | Many vector operations never had itineraries. Since the new machine model was a mapping from existing itinerary classes, we don't have a model for these. We still want to migrate A9 even though no one has invested in a complete model, so mark it incomplete to avoid the scheduler asserting. llvm-svn: 198123
* Add a PostMachineScheduler pass with generic implementation.Andrew Trick2013-12-281-284/+522
| | | | | | | | | | | | | | | | | | | | | | | | | PostGenericScheduler uses either the new machine model or the hazard checker for top-down scheduling. Most of the infrastructure for PreRA machine scheduling is reused. With a some tuning, this should allow MachineScheduler to be default for all ARM targets, including cortex-A9, using the new machine model. Likewise, with additional tuning, it should be able to replace PostRAScheduler for all targets. The PostMachineScheduler pass does not currently run the AntiDepBreaker. There is less need for it on targets that are already running preRA MachineScheduler. I want to prove it's necessary before committing to the maintenance burden. The PostMachineScheduler also currently removes kill flags and adds them all back later. This is a bit ridiculous. I'd prefer passes to directly use a liveness utility than rely on flags. A test case that enables this scheduler will be included in a subsequent checkin that updates the A9 model. llvm-svn: 198122
OpenPOWER on IntegriCloud