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* use ArgOperand APIGabor Greif2010-06-301-10/+10
| | | | llvm-svn: 107282
* use ArgOperand APIGabor Greif2010-06-301-1/+1
| | | | llvm-svn: 107280
* use ArgOperand APIGabor Greif2010-06-301-6/+6
| | | | llvm-svn: 107279
* use ArgOperand APIGabor Greif2010-06-301-10/+12
| | | | llvm-svn: 107278
* use ArgOperand APIGabor Greif2010-06-301-2/+2
| | | | llvm-svn: 107277
* use CallSite::arg_end instead of CallInst::op_endGabor Greif2010-06-301-1/+1
| | | | llvm-svn: 107276
* use getArgOperand (corrected by CallInst::ArgOffset) instead of getOperandGabor Greif2010-06-301-3/+3
| | | | llvm-svn: 107275
* use getArgOperand (corrected by CallInst::ArgOffset) instead of getOperandGabor Greif2010-06-301-1/+2
| | | | llvm-svn: 107273
* use getNumArgOperands instead of getNumOperandsGabor Greif2010-06-301-2/+2
| | | | llvm-svn: 107272
* use getArgOperand instead of getOperandGabor Greif2010-06-301-4/+4
| | | | llvm-svn: 107271
* use getArgOperand instead of getOperandGabor Greif2010-06-301-2/+2
| | | | llvm-svn: 107270
* use getArgOperand instead of getOperandGabor Greif2010-06-301-8/+8
| | | | llvm-svn: 107269
* Improve ScalarEvolution's nsw and nuw preservation.Dan Gohman2010-06-301-31/+105
| | | | llvm-svn: 107257
* When computing a new ConservativeResult, intersect it withDan Gohman2010-06-301-1/+2
| | | | | | the old one instead of replacing it, to be more precise. llvm-svn: 107256
* Rework scev-aa's basic computation so that it doesn't dependDan Gohman2010-06-301-7/+31
| | | | | | | | on ScalarEvolution successfully folding and preserving range information for both A-B and B-A. Now, if it gets either one, it's sufficient. llvm-svn: 107249
* Simplify.Dan Gohman2010-06-301-2/+1
| | | | llvm-svn: 107248
* Add AVX SSE2 integer unpack instructionsBruno Cardoso Lopes2010-06-301-10/+57
| | | | llvm-svn: 107246
* Add AVX SSE2 packed integer shuffle instructionsBruno Cardoso Lopes2010-06-301-0/+14
| | | | llvm-svn: 107245
* Remove trailing whitespace, no functionality changes.John Mosby2010-06-301-19/+18
| | | | llvm-svn: 107244
* Small refactoring of SSE2 packed integer shuffle instructionsBruno Cardoso Lopes2010-06-301-45/+26
| | | | llvm-svn: 107243
* Add AVX SSE2 pack with saturation integer instructionsBruno Cardoso Lopes2010-06-301-0/+9
| | | | llvm-svn: 107241
* Add AVX SSE2 integer packed compare instructionsBruno Cardoso Lopes2010-06-301-0/+17
| | | | llvm-svn: 107240
* - Add AVX form of all SSE2 logical instructionsBruno Cardoso Lopes2010-06-302-22/+99
| | | | | | - Add VEX encoding bits to x86 MRM0r-MRM7r llvm-svn: 107238
* Do not construct DIE for already processed MDNode.Devang Patel2010-06-301-1/+2
| | | | llvm-svn: 107237
* Use skipInstruction() as a simpler way of iterating over instructions using ↵Jakob Stoklund Olesen2010-06-301-10/+2
| | | | | | SrcReg llvm-svn: 107234
* Use clEnumValN macro to work around keyword clashJakob Stoklund Olesen2010-06-301-1/+1
| | | | llvm-svn: 107233
* Add variables into a scope before constructing scope DIE otherwise variables ↵Devang Patel2010-06-301-2/+2
| | | | | | won't be included DIE tree. llvm-svn: 107228
* Begin implementation of an inline spiller.Jakob Stoklund Olesen2010-06-293-1/+147
| | | | | | | | | | | InlineSpiller inserts loads and spills immediately instead of deferring to VirtRegMap. This is possible now because SlotIndexes allows instructions to be inserted and renumbered. This is work in progress, and is mostly a copy of TrivialSpiller so far. It works very well for functions that don't require spilling. llvm-svn: 107227
* Add *several* AVX integer packed binop instructionsBruno Cardoso Lopes2010-06-291-35/+109
| | | | llvm-svn: 107225
* Fix ScalarEvolution's tripcount computation for chains of loopsDan Gohman2010-06-291-41/+61
| | | | | | | where each loop's induction variable's start value is the exit value of a preceding loop. llvm-svn: 107224
* Revert r107205 and r107207.Bill Wendling2010-06-2917-46/+14
| | | | llvm-svn: 107215
* Print InlinedAt location.Devang Patel2010-06-291-7/+21
| | | | llvm-svn: 107214
* Add another bswap idiom that isn't matched.Eric Christopher2010-06-291-0/+8
| | | | llvm-svn: 107213
* Move SSE2 Packed Integer instructions around, and create specific sections ↵Bruno Cardoso Lopes2010-06-291-83/+113
| | | | | | for each of them llvm-svn: 107211
* Print InlinedAt location.Devang Patel2010-06-291-12/+23
| | | | llvm-svn: 107208
* Add AVX Move Aligned/Unaligned packed integersBruno Cardoso Lopes2010-06-291-12/+53
| | | | llvm-svn: 107206
* Introducing the "linker_weak" linkage type. This will be used for Objective-CBill Wendling2010-06-2917-14/+46
| | | | | | | | | | | | | | | | | | | metadata types which should be marked as "weak", but which the linker will remove upon final linkage. For example, the "objc_msgSend_fixup_alloc" symbol is defined like this: .globl l_objc_msgSend_fixup_alloc .weak_definition l_objc_msgSend_fixup_alloc .section __DATA, __objc_msgrefs, coalesced .align 3 l_objc_msgSend_fixup_alloc: .quad _objc_msgSend_fixup .quad L_OBJC_METH_VAR_NAME_1 This is different from the "linker_private" linkage type, because it can't have the metadata defined with ".weak_definition". llvm-svn: 107205
* Add AVX ld/st XCSR register.Bruno Cardoso Lopes2010-06-292-15/+26
| | | | | | Add VEX encoding bits for MRMXm x86 form llvm-svn: 107204
* Do not hardcode DW_AT_stmt_list value.Devang Patel2010-06-292-7/+17
| | | | | | Inspired by Artur Pietrek. llvm-svn: 107202
* Add support for encoding VDUP (ARM core register) instructions.Bob Wilson2010-06-291-0/+17
| | | | llvm-svn: 107201
* Fix the handling of partial redefines in the fast register allocator.Jakob Stoklund Olesen2010-06-291-17/+39
| | | | | | | | | | | A partial redefine needs to be treated like a tied operand, and the register must be reloaded while processing use operands. This fixes a bug where partially redefined registers were processed as normal defs with a reload added. The reload could clobber another use operand if it was a kill that allowed register reuse. llvm-svn: 107193
* Fix a register scavenger crash when dealing with undefined subregs.Bob Wilson2010-06-291-0/+18
| | | | | | | The LowerSubregs pass needs to preserve implicit def operands attached to EXTRACT_SUBREG instructions when it replaces those instructions with copies. llvm-svn: 107189
* Add AVX non-temporal storesBruno Cardoso Lopes2010-06-291-10/+52
| | | | llvm-svn: 107178
* Fix whitespace style.Dan Gohman2010-06-291-2/+2
| | | | llvm-svn: 107175
* Move non-temporal movs to their own sectionBruno Cardoso Lopes2010-06-291-34/+38
| | | | llvm-svn: 107168
* Add support for encoding NEON VMOV (from core register to scalar) instructions.Bob Wilson2010-06-291-6/+19
| | | | | | | The encoding is the same as VMOV (from scalar to core register) except that the operands are in different places. llvm-svn: 107167
* Add sqrt, rsqrt and rcp AVX instructionsBruno Cardoso Lopes2010-06-291-1/+67
| | | | llvm-svn: 107166
* skip dbg_value instructionsJim Grosbach2010-06-291-0/+2
| | | | llvm-svn: 107154
* The t2MOVi16 and t2MOVTi16 instructions do not set CPSR. Trying to addBob Wilson2010-06-291-2/+2
| | | | | | | a CPSR operand to them causes an assertion failure, so apparently these instructions haven't been getting a lot of use. llvm-svn: 107147
* use ArgOperand APIGabor Greif2010-06-291-6/+6
| | | | llvm-svn: 107145
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