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* In preparation for removing getNameWithPrefix off of TargetMachine,Eric Christopher2016-10-142-8/+9
| | | | | | | sink the current behavior into the callers and sink TargetMachine::getNameWithPrefix into TargetMachine::getSymbol. llvm-svn: 284203
* Tidy the calls to getCurrentSection().first -> getCurrentSectionOnly to helpEric Christopher2016-10-1411-30/+29
| | | | | | readability a bit. llvm-svn: 284202
* [AMDGPU] Emit 32-bit lo/hi got and pc relative variant kinds for external ↵Konstantin Zhuravlyov2016-10-146-21/+79
| | | | | | | | and global address space variables Differential Revision: https://reviews.llvm.org/D25562 llvm-svn: 284196
* [AMDGPU] Add 32-bit lo/hi got and pc relative variant kinds and emit ↵Konstantin Zhuravlyov2016-10-142-0/+16
| | | | | | | | appropriate relocations Differential Revision: https://reviews.llvm.org/D25548 llvm-svn: 284195
* Timer: Fix doxygen comments, use member initializer; NFCMatthias Braun2016-10-141-16/+12
| | | | llvm-svn: 284181
* Add interface for querying physical hardware concurrencyTeresa Johnson2016-10-141-0/+8
| | | | | | | | | | | | | | | | | | | | Summary: This will be used by ThinLTO to set the amount of backend parallelism, which performs better when restricted to the number of physical cores (on X86 at least, where getHostNumPhysicalCores is currently defined). If not available this falls back to thread::hardware_concurrency. Note I didn't add to the thread class since that is a typedef to std::thread where available. Reviewers: mehdi_amini Subscribers: beanz, llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D25585 llvm-svn: 284180
* CodeGen: use MSVC division on windows itaniumSaleem Abdulrasool2016-10-131-1/+2
| | | | | | | Windows itanium is identical to MSVC when dealing with everything but C++. Lower the math routines into msvcrt rather than compiler-rt. llvm-svn: 284175
* CodeGen: adjust floating point operations in Windows itaniumSaleem Abdulrasool2016-10-131-1/+2
| | | | | | | Windows itanium is equivalent to MSVC except in C++ mode. Ensure that the promote the 32-bit floating point operations to their 64-bit equivalences. llvm-svn: 284173
* [DAG] hoist DL(N) and fix formatting; NFCSanjay Patel2016-10-131-24/+31
| | | | llvm-svn: 284170
* [libFuzzer] more detailed message for disabled leak detectionKostya Serebryany2016-10-131-2/+4
| | | | llvm-svn: 284169
* LegalizeDAG: Implement PROMOTE for ISD::BITREVERSETom Stellard2016-10-131-1/+2
| | | | | | | | | | | | | | | Summary: This operation is promoted the same way was ISD::BSWAP. This will prevent a regression in test/Target/AMDGOU/bitreverse.ll when i16 support is implemented. Reviewers: bogner, hfinkel Subscribers: hfinkel, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D25202 llvm-svn: 284163
* [safestack] Reapply r283248 after moving X86-targeted SafeStack tests intoDavid L Kreitzer2016-10-131-7/+6
| | | | | | | | | | | | the X86 subdirectory. Original commit message: Requires a valid TargetMachine to be passed to the SafeStack pass. Patch by Michael LeMay Differential revision: http://reviews.llvm.org/D24896 llvm-svn: 284161
* New llc option pie-copy-relocations to optimize access to extern globals.Sriraman Tallam2016-10-132-5/+5
| | | | | | | | | This option indicates copy relocations support is available from the linker when building as PIE and allows accesses to extern globals to avoid the GOT. Differential Revision: https://reviews.llvm.org/D24849 llvm-svn: 284160
* Revert "In visitSTORE, always use FindBetterChain, rather than only when ↵Nirav Dave2016-10-133-121/+282
| | | | | | | | | UseAA is enabled." This reverts commit r284151 which appears to be triggering a LTO failures on Hexagon llvm-svn: 284157
* [RAGreedy] Empty live-ranges always succeed in last chance recoloring.Quentin Colombet2016-10-131-1/+12
| | | | | | | | | | | Relax the constraint for empty live-ranges while doing last chance recoloring. Indeed, those live-ranges do not need an actual color to be fond for the recoloring to work. Empty live-range may happen as a result of splitting/spilling. Unfortunately no test case for in-tree targets. llvm-svn: 284152
* In visitSTORE, always use FindBetterChain, rather than only when UseAA is ↵Nirav Dave2016-10-133-282/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enabled. Retrying after upstream changes. Simplify Consecutive Merge Store Candidate Search Now that address aliasing is much less conservative, push through simplified store merging search which only checks for parallel stores through the chain subgraph. This is cleaner as the separation of non-interfering loads/stores from the store-merging logic. Whem merging stores, search up the chain through a single load, and finds all possible stores by looking down from through a load and a TokenFactor to all stores visited. This improves the quality of the output SelectionDAG and generally the output CodeGen (with some exceptions). Additional Minor Changes: 1. Finishes removing unused AliasLoad code 2. Unifies the the chain aggregation in the merged stores across code paths 3. Re-add the Store node to the worklist after calling SimplifyDemandedBits. 4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is arbitrary, but seemed sufficient to not cause regressions in tests. This finishes the change Matt Arsenault started in r246307 and jyknight's original patch. Many tests required some changes as memory operations are now reorderable. Some tests relying on the order were changed to use volatile memory operations Noteworthy tests: CodeGen/AArch64/argument-blocks.ll - It's not entirely clear what the test_varargs_stackalign test is supposed to be asserting, but the new code looks right. CodeGen/AArch64/arm64-memset-inline.lli - CodeGen/AArch64/arm64-stur.ll - CodeGen/ARM/memset-inline.ll - The backend now generates *worse* code due to store merging succeeding, as we do do a 16-byte constant-zero store efficiently. CodeGen/AArch64/merge-store.ll - Improved, but there still seems to be an extraneous vector insert from an element to itself? CodeGen/PowerPC/ppc64-align-long-double.ll - Worse code emitted in this case, due to the improved store->load forwarding. CodeGen/X86/dag-merge-fast-accesses.ll - CodeGen/X86/MergeConsecutiveStores.ll - CodeGen/X86/stores-merging.ll - CodeGen/Mips/load-store-left-right.ll - Restored correct merging of non-aligned stores CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll - Improved. Correctly merges buffer_store_dword calls CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll - Improved. Sidesteps loading a stored value and merges two stores CodeGen/X86/pr18023.ll - This test has been removed, as it was asserting incorrect behavior. Non-volatile stores *CAN* be moved past volatile loads, and now are. CodeGen/X86/vector-idiv.ll - CodeGen/X86/vector-lzcnt-128.ll - It's basically impossible to tell what these tests are actually testing. But, looks like the code got better due to the memory operations being recognized as non-aliasing. CodeGen/X86/win32-eh.ll - Both loads of the securitycookie are now merged. CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll - This test appears to work but no longer exhibits the spill behavior. Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle Subscribers: wdng, nhaehnle, nemanjai, arsenm, weimingz, niravd, RKSimon, aemerson, qcolombet, dsanders, resistor, tstellarAMD, t.p.northover, spatel Differential Revision: https://reviews.llvm.org/D14834 llvm-svn: 284151
* [libFuzzer] add -trace_malloc= flagKostya Serebryany2016-10-137-5/+70
| | | | llvm-svn: 284149
* [AArch64][RegisterBankInfo] Switch to fully static opds mapping for G_BITCAST.Quentin Colombet2016-10-131-4/+10
| | | | | | NFC. llvm-svn: 284146
* Add interface to compute number of physical cores on host systemTeresa Johnson2016-10-132-1/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: For now I have only added support for x86_64 Linux, but other systems can be added incrementally. This is to be used for setting the default parallelism for ThinLTO backends (instead of thread::hardware_concurrency which includes hyperthreading and is too aggressive). I'll send this as a follow-on patch, and it will fall back to hardware_concurrency when the new getHostNumPhysicalCores returns -1 (when not supported for a given host system). I also added an interface to MemoryBuffer to force reading a file as a stream - this is required for /proc/cpuinfo which is a special file that looks like a normal file but appears to have 0 size. The existing readers of this file in Host.cpp are reading the first 1024 or so bytes from it, because the necessary info is near the top. But for the new functionality we need to be able to read the entire file. I can go back and change the other readers to use the new getFileAsStream as a follow-on patch since it seems much more robust. Added a unittest. Reviewers: mehdi_amini Subscribers: beanz, mgorny, llvm-commits, modocache Differential Revision: https://reviews.llvm.org/D25564 llvm-svn: 284138
* Truncate long names in type recordsReid Kleckner2016-10-132-18/+29
| | | | | | | | | In the MS ABI, the frontend is supposed to MD5 such pathologically long names. LLVM should still defend itself from long names, though. Fixes part of PR29098. llvm-svn: 284136
* [X86][AVX512] Fix sext v32i1 -> v32i8 lowering.Igor Breger2016-10-131-1/+1
| | | | | | | | Fix PR30600. Differential Revision: https://reviews.llvm.org/D25554 llvm-svn: 284134
* [libFuzzer] reapply r283946: refactoring to speed things up, NFC. Now with a ↵Kostya Serebryany2016-10-132-36/+23
| | | | | | fix for gcc build llvm-svn: 284132
* Fix for PR30687. Avoid dereferencing MBB.end().Reid Kleckner2016-10-132-38/+31
| | | | | | | | | | | | | | | | | | | | We don't need to return a MachineInstr* from these stack probe insertion calls anyway. If we ever need to add it back, we can return an iterator instead. Based on a patch by David Kreitzer This bug is a consequence of r279314 | dexonsmith | 2016-08-19 13:40:12 -0700 (Fri, 19 Aug 2016) | 110 lines We hit the "Assertion `!NodePtr->isKnownSentinel()' failed" assertion, but only when inserting a stack probe call at the end of an MBB, which isn't necessarily a common situation. Differential Revision: https://reviews.llvm.org/D25566 llvm-svn: 284130
* Do not delete leading ../ in remove_dots.Eric Liu2016-10-131-6/+5
| | | | | | | | | | Reviewers: bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25561 llvm-svn: 284129
* [ARM]: Assign cost of scaling used in addressing mode for ARM coresJaved Absar2016-10-134-2/+29
| | | | | | | | | | | | | | | | | | | | | This patch assigns cost of the scaling used in addressing. On many ARM cores, a negated register offset takes longer than a non-negated register offset, in a register-offset addressing mode. For instance: LDR R0, [R1, R2 LSL #2] LDR R0, [R1, -R2 LSL #2] Above, (1) takes less cycles than (2). By assigning appropriate scaling factor cost, we enable the LLVM to make the right trade-offs in the optimization and code-selection phase. Differential Revision: http://reviews.llvm.org/D24857 Reviewers: jmolloy, rengolin llvm-svn: 284127
* [LV] Account for predicated stores in instruction costsMatthew Simpson2016-10-131-0/+6
| | | | | | | This patch ensures that we scale the estimated cost of predicated stores by block probability. This is a follow-on patch for r284123. llvm-svn: 284126
* [LV] Avoid rounding errors for predicated instruction costsMatthew Simpson2016-10-131-26/+29
| | | | | | | | | | | | This patch modifies the cost calculation of predicated instructions (div and rem) to avoid the accumulation of rounding errors due to multiple truncating integer divisions. The calculation for predicated stores will be addressed in a follow-on patch since we currently don't scale the cost of predicated stores by block probability. Differential Revision: https://reviews.llvm.org/D25333 llvm-svn: 284123
* [DAGCombiner] Add vector support to (mul (shl X, Y), Z) -> (shl (mul X, Z), ↵Simon Pilgrim2016-10-131-7/+6
| | | | | | Y) style combines llvm-svn: 284122
* AMDGPU: Assume spilling will occur at -O0Matt Arsenault2016-10-131-1/+5
| | | | | | | | Because everything live is spilled at the end of a block by fast regalloc, assume this will happen and avoid the copies of the resource descriptor. llvm-svn: 284119
* [DAGCombiner] Add vector support to C2-(A+C1) -> (C2-C1)-A foldingSimon Pilgrim2016-10-131-5/+5
| | | | llvm-svn: 284117
* AMDGPU: Fix truncate to bool warningsMatt Arsenault2016-10-131-5/+5
| | | | llvm-svn: 284116
* [mips] Add IAS support for dvp, evpSimon Dardis2016-10-134-4/+44
| | | | | | | | | | | | | These instructions were only defined for microMIPSR6 previously. Add definitions for MIPSR6, correct definitions for microMIPSR6, flag these instructions as having unmodelled side effects (they disable/enable virtual processors) and add missing disassember tests for microMIPSR6. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24291 llvm-svn: 284115
* [DAGCombiner] Add vector support to (sub -1, x) -> (xor x, -1) canonicalizationSimon Pilgrim2016-10-131-1/+12
| | | | | | Improves commutation potential llvm-svn: 284113
* [X86] Basic additions to support RegCall Calling Convention.Oren Ben Simhon2016-10-137-0/+227
| | | | | | | | | | The Register Calling Convention (RegCall) was introduced by Intel to optimize parameter transfer on function call. This calling convention ensures that as many values as possible are passed or returned in registers. This commit presents the basic additions to LLVM CodeGen in order to support RegCall in X86. Differential Revision: http://reviews.llvm.org/D25022 llvm-svn: 284108
* Silence unused warning in non-assert builds.Daniel Jasper2016-10-131-3/+3
| | | | llvm-svn: 284107
* [AVX-512] Teach shuffle lowering to recognize 512-bit zero extends.Craig Topper2016-10-131-2/+27
| | | | llvm-svn: 284105
* [X86] Simplify the lowering code for extracting and inserting subvectors.Craig Topper2016-10-131-24/+21
| | | | | | | We don't need to check if AVX is enabled. It's implied by the operation action being set to Custom. We don't need to check both the input and output type widths. We only need to check the type that's being inserted or extracted. The other type is known to be a legal type and we can assume its a different width. llvm-svn: 284102
* Memory-SSA: strengthen defClobbersUseOrDef interfaceSebastian Pop2016-10-131-19/+15
| | | | | | | As Danny pointed out, defClobbersUseOrDef should use MemoryLocOrCall to make sure fences are properly handled. llvm-svn: 284099
* commit back "GVN-hoist: fix store past load dependence analysis (PR30216, ↵Sebastian Pop2016-10-132-90/+109
| | | | | | | | | | PR30499)" This is with an extra change to avoid calling MemoryLocation::get() on a call instruction. Differential Revision: https://reviews.llvm.org/D25542 llvm-svn: 284098
* [AArch64][RegisterBankInfo] Provide alternative mappings for 64-bit loadQuentin Colombet2016-10-131-1/+30
| | | | | | | | This allows RegBankSelect in greedy mode to get rid some of the cross register bank copies when loads are involved in the chain of computation. llvm-svn: 284097
* Correct PrivateLinkage for COFFReid Kleckner2016-10-131-3/+3
| | | | | | | | | | | | | - Use storage class C_STAT for 'PrivateLinkage' The storage class for PrivateLinkage should equal to the Internal Linkage. - Set 'PrivateGlobalPrefix' from "L" to ".L" for MM_WinCOFF (includes x86_64) MM_WinCOFF has empty GlobalPrefix '\0' so PrivateGlobalPrefix "L" may conflict to the normal symbol name starting with 'L'. Based on a patch by Han Sangjin! Manually updated test cases. llvm-svn: 284096
* [AArch64][RegisterBankInfo] Provide alternative mappings for G_BITCASTs.Quentin Colombet2016-10-131-8/+45
| | | | | | | Thanks to this patch, RegBankSelect is able to get rid of some register bank copies as demonstrated in the test case. llvm-svn: 284094
* Revert "GVN-hoist: fix store past load dependence analysis (PR30216, PR30499)"Reid Kleckner2016-10-132-104/+90
| | | | | | | | | | | This CL didn't actually address the test case in PR30499, and clang still crashes. Also revert dependent change "Memory-SSA cleanup of clobbers interface, NFC" Reverts r283965 and r283967. llvm-svn: 284093
* [AArch64][RegisterBankInfo] Describe cross regbank copies statically.Quentin Colombet2016-10-132-2/+68
| | | | | | NFC. llvm-svn: 284091
* [AArch64][RegisterBankInfo] Use static mapping for same bank G_BITCAST.Quentin Colombet2016-10-131-0/+8
| | | | | | NFC. llvm-svn: 284090
* [AArch64][MachineLegalizer] Mark more G_BITCAST as legal.Quentin Colombet2016-10-131-1/+8
| | | | | | | Basically any vector types that fits in a 32-bit register is also valid as far as copies are concerned. llvm-svn: 284089
* [AArch64][RegisterBankInfo] Bump the cost of vector loads.Quentin Colombet2016-10-131-0/+10
| | | | | | | This does not change anything yet, because we do not offer any alternative mapping. llvm-svn: 284088
* [AArch64][RegisterBankInfo] Use a proper cost for cross regbank G_BITCASTs.Quentin Colombet2016-10-131-2/+11
| | | | | | | This does not change anything yet, because we do not offer any alternative mapping. llvm-svn: 284087
* [AArch64][RegisterBankInfo] Provide more realistic copy costs.Quentin Colombet2016-10-131-1/+10
| | | | llvm-svn: 284086
* Handle lane masks in LivePhysRegs when adding live-insKrzysztof Parzyszek2016-10-121-5/+12
| | | | | | Differential Revision: https://reviews.llvm.org/D25533 llvm-svn: 284076
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