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* [WebAssembly] Mark more operators as Expand.Dan Gohman2015-08-201-0/+26
| | | | llvm-svn: 245636
* [InstCombine] Transform A & (L - 1) u< L --> L != 0Sanjoy Das2015-08-201-0/+13
| | | | | | | | | | | | | | | | | | | | Summary: This transform is never a pessimization at the IR level (since it replaces an `icmp` with another), and has potentiall payoffs: 1. It may make the `icmp` fold away or become loop invariant. 2. It may make the `A & (L - 1)` computation dead. This shows up in Java, in range checks generated by array accesses of the form `a[i & (a.length - 1)]`. Reviewers: reames, majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12210 llvm-svn: 245635
* [SLP] Propagate 'nontemporal' attribute into vectorized instructions.Michael Zolotukhin2015-08-201-0/+3
| | | | llvm-svn: 245633
* [LoopVectorize] Propagate 'nontemporal' attribute into vectorized instructions.Michael Zolotukhin2015-08-201-1/+2
| | | | llvm-svn: 245632
* Rename Instruction::dropUnknownMetadata() to dropUnknownNonDebugMetadata()Adrian Prantl2015-08-208-14/+5
| | | | | | | | | | | and make it always preserve debug locations, since all callers wanted this behavior anyway. This is addressing a post-commit review feedback for r245589. NFC (inside the LLVM tree). llvm-svn: 245622
* [X86] Look for scalar through one bitcast when lowering to VBROADCAST.Ahmed Bougacha2015-08-202-0/+24
| | | | | | | | | | | | | | Fixes PR23464: one way to use the broadcast intrinsics is: _mm256_broadcastw_epi16(_mm_cvtsi32_si128(*(int*)src)); We don't currently fold this, but now that we use native IR for the intrinsics (r245605), we can look through one bitcast to find the broadcast scalar. Differential Revision: http://reviews.llvm.org/D10557 llvm-svn: 245613
* [NVPTX] truncating 64-bit to 32-bit is freeJingyue Wu2015-08-201-0/+8
| | | | | | | | | | | | | | Summary: Add an LSR test that exercises isTruncateFree. Without this change, LSR creates another indvar representing the truncated value. Reviewers: jholewinski, eliben Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D12058 llvm-svn: 245611
* [X86] Replace avx2 broadcast intrinsics with native IR.Ahmed Bougacha2015-08-202-86/+40
| | | | | | | | | | Since r245605, the clang headers don't use these anymore. r245165 updated some of the tests already; update the others, add an autoupgrade, remove the intrinsics, and cleanup the definitions. Differential Revision: http://reviews.llvm.org/D10555 llvm-svn: 245606
* [asan] Add ASAN support for AArch64 42-bit VMAAdhemerval Zanella2015-08-201-0/+14
| | | | | | | | | This patch adds support for asan on aarch64-linux with 42-bit VMA (current default config for 64K pagesize kernels). The support is enabled by defining the SANITIZER_AARCH64_VMA to 42 at build time for both clang/llvm and compiler-rt. The default VMA is 39 bits. llvm-svn: 245594
* [ValueTracking] computeOverflowForSignedAdd and isKnownNonNegativeJingyue Wu2015-08-202-29/+75
| | | | | | | | | | | | | | | | Summary: Refactor, NFC Extracts computeOverflowForSignedAdd and isKnownNonNegative from NaryReassociate to ValueTracking in case others need it. Reviewers: reames Subscribers: majnemer, llvm-commits Differential Revision: http://reviews.llvm.org/D11313 llvm-svn: 245591
* [LVI] Avoid iterator invalidation in LazyValueInfoCache::threadEdgeBruno Cardoso Lopes2015-08-201-1/+1
| | | | | | | Do that by copying out the elements to another SmallPtrSet. Follow up from r245309. llvm-svn: 245590
* Fix a bug that caused SimplifyCFG to drop DebugLocs.Adrian Prantl2015-08-207-3/+8
| | | | | | | | | | | Instruction::dropUnknownMetadata(KnownSet) is supposed to preserve all metadata in KnownSet, but the condition for DebugLocs was inverted. Most users of dropUnknownMetadata() actually worked around this by not adding LLVMContext::MD_dbg to their list of KnowIDs. This is now made explicit. llvm-svn: 245589
* Fix a debug location handling bug in GVN.Adrian Prantl2015-08-201-1/+2
| | | | | | | | | | | | | | Caught by the famous "DebugLoc describes the currect SubProgram" assertion. When GVN is removing a nonlocal load it updates the debug location of the SSA value it replaced the load with with the one of the load. In the testcase this actually overwrites a valid debug location with an empty one. In reality GVN has to make an arbitrary choice between two equally valid debug locations. This patch changes to behavior to only update the location if the value doesn't already have a debug location. llvm-svn: 245588
* [LVer] Fix FIXME: hide addPHINodes, NFCAdam Nemet2015-08-202-3/+7
| | | | | | | | | | | | | | Since Ashutosh made findDefsUsedOutsideOfLoop public, we can clean this up. Now clients that don't compute DefsUsedOutsideOfLoop can just call versionLoop() and computing DefsUsedOutsideOfLoop will happen implicitly. With that there is no reason to expose addPHINodes anymore. Ashutosh, you can now drop the calls to findDefsUsedOutsideOfLoop and addPHINodes in LVerLICM and things should just work. llvm-svn: 245579
* [ARM] Don't try and custom lower a vNi64 SETCC.James Molloy2015-08-201-0/+6
| | | | | | | | It won't go well. We've already marked 64-bit SETCCs as non-Custom, but it's just possible that a SETCC has a legal result type but an illegal operand type. If this happens, bail out before we create unselectable nodes. Fixes PR24292. I tried to create a testcase but in 99% of cases we can't trigger this - not surprising that this bug has been latent since 2009. llvm-svn: 245577
* Fix symbol value computation when part of the expression is weak.Rafael Espindola2015-08-201-1/+1
| | | | | | | This matches the behaviour of the gnu assembler and is part of fixing pr24486. llvm-svn: 245576
* [Sparc]: correct the 'set' synthetic instructionDouglas Katzman2015-08-201-5/+37
| | | | | | Differential Revision: http://reviews.llvm.org/D12194 llvm-svn: 245575
* Optimize bitwise even/odd test (-x&1 -> x&1) to not use negation.Balaram Makam2015-08-201-0/+4
| | | | | | | | | | | | Summary: We know that -x & 1 is equivalent to x & 1, avoid using negation for testing if a negative integer is even or odd. Reviewers: majnemer Subscribers: junbuml, mssimpso, gberry, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D12156 llvm-svn: 245569
* [X86] Fix FBLD and FBSTPMarina Yatsina2015-08-201-2/+2
| | | | | | | | | | FBLD and FBSTP should receive TBYTE because it is defined as FBLD m80 FBSTP m80 Differential Revision: http://reviews.llvm.org/D11748 llvm-svn: 245553
* [X86] Fix bug in COMISD and COMISS definition in td filesMarina Yatsina2015-08-202-6/+6
| | | | | | | | | | | | COMISD should receive QWORD because it is defined as (V)COMISD xmm1, xmm2/m64 COMISS should receive DWORD because it is defined as (V)COMISS xmm1, xmm2/m32 Differential Revision: http://reviews.llvm.org/D11712 llvm-svn: 245551
* Make helper functions static. NFC.Benjamin Kramer2015-08-202-2/+2
| | | | llvm-svn: 245549
* [X86] Fix the (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) foldDavid Majnemer2015-08-201-12/+28
| | | | | | | | | We didn't check for the necessary preconditions before folding a mask/shift into a single mask. This fixes PR24516. llvm-svn: 245544
* Revert "[DSE] Enable removal of lifetime intrinsics in terminating blocks"Bjorn Steinbrink2015-08-201-30/+3
| | | | llvm-svn: 245543
* [DSE] Enable removal of lifetime intrinsics in terminating blocksBjorn Steinbrink2015-08-201-3/+30
| | | | | | | | | | | | | | | | Usually DSE is not supposed to remove lifetime intrinsics, but it's actually ok to remove them for dead objects in terminating blocks, because they convey no extra information there. Until we hit a lifetime start that cannot be removed, that is. Because from that point on the lifetime intrinsics become interesting again, e.g. for stack coloring. Reviewers: reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11710 llvm-svn: 245542
* [ARC] Pull the ObjC ARC components that really serve the role ofChandler Carruth2015-08-2012-450/+41
| | | | | | | | | | | | | | analyses into LLVM's Analysis library rather than having them in a Transforms library. This is motivated by the need to have the core AliasAnalysis infrastructure be aware of the ObjCARCAliasAnalysis. However, it also seems like a nice and clean separation. Everything was very easy to move and this doesn't create much clutter in the analysis library IMO. Differential Revision: http://reviews.llvm.org/D12133 llvm-svn: 245541
* [PowerPC] Fix value type on XVCMPEQDP for v2f64 comparisonsHal Finkel2015-08-201-3/+4
| | | | | | | | | XVCMPEQDP is used for VSX v2f64 equality comparisons, but the value type needs to be v2i64 (as that's the corresponding SETCC type). Fixes PR24225. llvm-svn: 245535
* [PowerPC] Fix the int2fp(fp2int(x)) DAGCombine to ignore ppc_fp128Hal Finkel2015-08-201-0/+3
| | | | | | | | This DAGCombine was creating custom SDAG nodes with an illegal ppc_fp128 operand type because it was triggering on f64/f32 int2fp(fp2int(ppc_fp128 x)), but shouldn't (it should only apply to f32/f64 types). The result was a crash. llvm-svn: 245530
* MIR Serialization: Use the global value syntax for global value memory operands.Alex Lorenz2015-08-202-5/+15
| | | | | | | | | | | This commit modifies the serialization syntax so that the global IR values in machine memory operands use the global value '@<name>' syntax instead of the current '%ir.<name>' syntax. The unnamed global IR values are handled by this commit as well, as the existing global value parsing method can parse the unnamed globals already. llvm-svn: 245527
* MIR Serialization: Change syntax for the call entry pseudo source values.Alex Lorenz2015-08-204-14/+24
| | | | | | | | | | | | The global IR values in machine memory operands should use the global value '@<name>' syntax instead of the current '%ir.<name>' syntax. However, the global value call entry pseudo source values use the global value syntax already. Therefore, the syntax for the call entry pseudo source values has to be changed so that the global values and call entry global value PSVs can be parsed without ambiguities. llvm-svn: 245526
* Fix test failure introduced by r245521.Alex Lorenz2015-08-191-0/+6
| | | | | | | | | Machine memory operands can contain pointer values that are constants, and the 'getLocalSlot' method requires non-constant values. The constant pointer values will have to be serialized in a different patch. llvm-svn: 245523
* MIR Serialization: Serialize unnamed local IR values in memory operands.Alex Lorenz2015-08-194-7/+51
| | | | llvm-svn: 245521
* MIR Parser: parseIRValue should take in a constant pointer. NFC.Alex Lorenz2015-08-191-3/+3
| | | | llvm-svn: 245520
* MIR Printer: Extract the code that prints IR slots to a separate function. NFC.Alex Lorenz2015-08-191-4/+8
| | | | | | This code can be reused when printing references to unnamed local IR values. llvm-svn: 245519
* [x86] enable machine combiner reassociations for scalar double-precision min/maxSanjay Patel2015-08-191-0/+4
| | | | llvm-svn: 245506
* [x86] enable machine combiner reassociations for scalar single-precision ↵Sanjay Patel2015-08-191-0/+2
| | | | | | maximums llvm-svn: 245504
* [DAGCombiner] Added SMAX/SMIN/UMAX/UMIN constant foldingSimon Pilgrim2015-08-192-1/+38
| | | | | | | | | | We still need to add constant folding of vector comparisons to fold the tests for targets that don't support the respective min/max nodes I needed to update 2011-12-06-AVXVectorExtractCombine to load a vector instead of using a constant vector to prevent it folding Differential Revision: http://reviews.llvm.org/D12118 llvm-svn: 245503
* [AArch64][FastISel] Don't fold shifts with UB.Juergen Ributzka2015-08-191-13/+38
| | | | | | | | | | We are already falling back to SelectionDAG when encountering an shift with UB. This adds the same checks for shifts with UB that get folded into arithmetic or logical operations. This fixes rdar://problem/22345295. llvm-svn: 245499
* [X86] Emit more efficient >= comparisons against 0David Majnemer2015-08-191-1/+49
| | | | | | | | | | | | | | | | | | | | | | | We don't do a great job with >= 0 comparisons against zero when the result is used as an i8. Given something like: void f(long long LL, bool *B) { *B = LL >= 0; } We used to generate: shrq $63, %rdi xorb $1, %dil movb %dil, (%rsi) Now we generate: testq %rdi, %rdi setns (%rsi) Differential Revision: http://reviews.llvm.org/D12136 llvm-svn: 245498
* [WebAssembly] Use the default alignment for SIMD types.Dan Gohman2015-08-191-2/+2
| | | | | | | | | Previously WebAssembly's datalayout string had -v128:8:128. This had been an attempt to declare a certain level of support for unaligned SIMD accesses. However, clang makes its own determinations for SIMD alignment that are independent of the datalayout string, so this wasn't actually meaningful. llvm-svn: 245494
* [DAGCombiner] Fold CONCAT_VECTORS of EXTRACT_SUBVECTOR (or undef) to ↵Simon Pilgrim2015-08-191-5/+79
| | | | | | | | | | VECTOR_SHUFFLE. Check to see if this is a CONCAT_VECTORS of a bunch of EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector inputs come from at most two distinct vectors the same size as the result, attempt to turn this into a legal shuffle. Differential Revision: http://reviews.llvm.org/D12125 llvm-svn: 245490
* Replace some calls to isa<LandingPadInst> with isEHPad()David Majnemer2015-08-194-7/+7
| | | | | | No functionality change is intended. llvm-svn: 245487
* [Sparc]: asm-only support for the ldstub instruction.Douglas Katzman2015-08-191-0/+11
| | | | llvm-svn: 245485
* MIR Parser: Rename 'MachineOperandWithLocation' to 'ParsedMachineOperand'. NFC.Alex Lorenz2015-08-191-14/+13
| | | | | | | Besides storing the operand's source range, this structure now stores other attributes as well, so the name should reflect this fact. llvm-svn: 245483
* MIR Serialization: Serialize instruction's register ties.Alex Lorenz2015-08-194-19/+119
| | | | | | | | This commit serializes the machine instruction's register operand ties. The ties are printed out only when the instructon has register ties that are different from the ties that are specified in the instruction's description. llvm-svn: 245482
* Temporary fix for the self-host failures introduced by rL244921.Nemanja Ivanovic2015-08-191-1/+2
| | | | | | | | | This revision has introduced an issue that only affects bootstrapped compiler when it is printing the ASM. I am working on resolving the issue, but in the meantime, I'm disabling the legalization of scalar_to_vector operation for v2i64 and the associated testing until I can get this fixed. llvm-svn: 245481
* MIR Serialization: Serialize defined registers that require 'def' register flag.Alex Lorenz2015-08-194-6/+17
| | | | | | | | | The defined registers are already serialized - they are represented by placing them before the '=' in a machine instruction. However, certain instructions like INLINEASM can have defined register operands after the '=', so this commit introduces the 'def' register flag for such operands. llvm-svn: 245480
* [PeepholeOptimizer] Look through PHIs to find additional register sourcesBruno Cardoso Lopes2015-08-192-86/+287
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reintroduce r245442. Remove an overly conservative assertion introduced in r245442. We could replace the assertion to use `shareSameRegisterFile` instead, but in that point in `insertPHI` we already lost the original Def subreg to check against. So drop the assertion completely. Original commit message: - Teaches the ValueTracker in the PeepholeOptimizer to look through PHI instructions. - Add findNextSourceAndRewritePHI method to lookup into multiple sources returnted by the ValueTracker and rewrite PHIs with new sources. With these changes we can find more register sources and rewrite more copies to allow coaslescing of bitcast instructions. Hence, we eliminate unnecessary VR64 <-> GR64 copies in x86, but it could be extended to other archs by marking "isBitcast" on target specific instructions. The x86 example follows: A: psllq %mm1, %mm0 movd %mm0, %r9 jmp C B: por %mm1, %mm0 movd %mm0, %r9 jmp C C: movd %r9, %mm0 pshufw $238, %mm0, %mm0 Becomes: A: psllq %mm1, %mm0 jmp C B: por %mm1, %mm0 jmp C C: pshufw $238, %mm0, %mm0 Differential Revision: http://reviews.llvm.org/D11197 rdar://problem/20404526 llvm-svn: 245479
* [SPARC] Enable writing to floating-point-state register.Douglas Katzman2015-08-193-0/+27
| | | | llvm-svn: 245475
* [AArch64] Improve short-form diags on long-form Match_InvalidOperand.Ahmed Bougacha2015-08-191-10/+18
| | | | | | | | | Since r244955, we try to use the short-form ErrorInfo when both tries failed, and the long-form match failed on a suffix operand. However, this means we sometimes mix ErrorInfo and MatchResult (one manifestation of this being PR24498). Instead, restore both. llvm-svn: 245469
* [SCEV] Fix GCC 4.8.0 ICE in lambda functionHal Finkel2015-08-191-7/+3
| | | | | | | | | Rewrite some code to not use a lambda function. The non-lambda code is just about as clean as the original, and not any longer. The lambda function causes an internal compiler error in GCC 4.8.0, and it is not worth breaking support for that compiler over this. NFC. llvm-svn: 245466
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