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* [ADT] Add the scalbn function for APFloat.Chandler Carruth2014-10-101-0/+17
| | | | llvm-svn: 219473
* [LVI] Revert the remainder of "r218231 - Add two thresholds ↵Hal Finkel2014-10-101-22/+0
| | | | | | | | | lvi-overdefined-BB-threshold and lvi-overdefined-threshold" Some of r218231 was reverted with the code that used it in r218971, but not all of it. This removes the rest (which is now dead). llvm-svn: 219469
* Avoid unnecessary map lookup/insertion.David Blaikie2014-10-101-2/+2
| | | | llvm-svn: 219466
* SimplifyCFG: Don't convert phis into selects if we could remove undef behaviorArnold Schwaighofer2014-10-101-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instead We used to transform this: define void @test6(i1 %cond, i8* %ptr) { entry: br i1 %cond, label %bb1, label %bb2 bb1: br label %bb2 bb2: %ptr.2 = phi i8* [ %ptr, %entry ], [ null, %bb1 ] store i8 2, i8* %ptr.2, align 8 ret void } into this: define void @test6(i1 %cond, i8* %ptr) { %ptr.2 = select i1 %cond, i8* null, i8* %ptr store i8 2, i8* %ptr.2, align 8 ret void } because the simplifycfg transformation into selects would happen to happen before the simplifycfg transformation that removes unreachable control flow (We have 'unreachable control flow' due to the store to null which is undefined behavior). The existing transformation that removes unreachable control flow in simplifycfg is: /// If BB has an incoming value that will always trigger undefined behavior /// (eg. null pointer dereference), remove the branch leading here. static bool removeUndefIntroducingPredecessor(BasicBlock *BB) Now we generate: define void @test6(i1 %cond, i8* %ptr) { store i8 2, i8* %ptr.2, align 8 ret void } I did not see any impact on the test-suite + externals. rdar://18596215 llvm-svn: 219462
* Improve sqrt estimate algorithm (fast-math)Sanjay Patel2014-10-091-17/+16
| | | | | | | | | | | | | | | | | | | This patch changes the fast-math implementation for calculating sqrt(x) from: y = 1 / (1 / sqrt(x)) to: y = x * (1 / sqrt(x)) This has 2 benefits: less code / faster code and one less estimate instruction that may lose precision. The only target that will be affected (until http://reviews.llvm.org/D5658 is approved) is PPC. The difference in codegen for PPC is 2 less flops for a single-precision sqrtf or vector sqrtf and 4 less flops for a double-precision sqrt. We also eliminate a constant load and extra register usage. Differential Revision: http://reviews.llvm.org/D5682 llvm-svn: 219445
* delete function names from commentsSanjay Patel2014-10-091-32/+30
| | | | llvm-svn: 219444
* delete function name from commentSanjay Patel2014-10-091-2/+2
| | | | llvm-svn: 219443
* Add ApplePropertyString dump helper to Dwarf.{h|cpp}.Frederic Riss2014-10-091-0/+33
| | | | | | | | | | Reviewers: dblaikie Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5688 llvm-svn: 219442
* Fix bug in GPR to FPR moves in PPC64LE.Samuel Antao2014-10-091-4/+4
| | | | | | The current implementation of GPR->FPR register moves uses a stack slot. This mechanism writes a double word and reads a word. In big-endian the load address must be displaced by 4-bytes in order to get the right value. In little endian this is no longer required. This patch fixes the issue and adds LE regression tests to fast-isel-conversion which currently expose this problem. llvm-svn: 219441
* Remove unused parameterDavid Blaikie2014-10-092-6/+5
| | | | llvm-svn: 219440
* Sink DwarfDebug::createAndAddScopeChildren down into DwarfCompileUnit.David Blaikie2014-10-094-19/+17
| | | | llvm-svn: 219437
* Sink DwarfDebug::constructSubprogramScopeDIE down into DwarfCompileUnitDavid Blaikie2014-10-094-49/+55
| | | | llvm-svn: 219436
* [Reassociate] Don't canonicalize X - undef to X + (-undef).Chad Rosier2014-10-091-0/+4
| | | | | | | Phabricator Revision: http://reviews.llvm.org/D5674 PR21205 llvm-svn: 219434
* Remove a compiler bug workaround from 2007. The affected versions of gcc are ↵Benjamin Kramer2014-10-091-11/+1
| | | | | | | | long gone. NFC. llvm-svn: 219433
* Revert "[BasicAA] Revert "Revert r218714 - Make better use of zext and sign ↵Hal Finkel2014-10-091-41/+2
| | | | | | | | information."" This reverts commit r219135 -- still causing miscompiles in SPEC it seems... llvm-svn: 219432
* Fix typoMatt Arsenault2014-10-091-3/+3
| | | | llvm-svn: 219429
* R600/SI: Legalize CopyToReg during instruction selectionTom Stellard2014-10-093-14/+20
| | | | | | | The instruction emitter will crash if it encounters a CopyToReg node with a non-register operand like FrameIndex. llvm-svn: 219428
* [PBQP] Add missing headers from r219421.Lang Hames2014-10-091-0/+38
| | | | llvm-svn: 219425
* Sink DwarfDebug::createScopeChildrenDIE down into DwarfCompileUnit.David Blaikie2014-10-094-28/+31
| | | | llvm-svn: 219422
* [PBQP] Replace PBQPBuilder with composable constraints (PBQPRAConstraint).Lang Hames2014-10-096-455/+384
| | | | | | | | | | | | | | | | This patch removes the PBQPBuilder class and its subclasses and replaces them with a composable constraints class: PBQPRAConstraint. This allows constraints that are only required for optimisation (e.g. coalescing, soft pairing) to be mixed and matched. This patch also introduces support for target writers to supply custom constraints for their targets by overriding a TargetSubtargetInfo method: std::unique_ptr<PBQPRAConstraints> getCustomPBQPConstraints() const; This patch should have no effect on allocations. llvm-svn: 219421
* R600/SI: Legalize INSERT_SUBREG instructions during PostISelFoldingTom Stellard2014-10-091-0/+29
| | | | | | | | LLVM assumes INSERT_SUBREG will always have register operands, so we need to legalize non-register operands, like FrameIndexes, to avoid random assertion failures. llvm-svn: 219420
* Sink DwarfDebug.cpp::constructVariableDIE into DwarfCompileUnit.David Blaikie2014-10-093-12/+14
| | | | llvm-svn: 219419
* Move DwarfUnit::constructVariableDIE down to DwarfCompileUnit, since it's ↵David Blaikie2014-10-094-72/+74
| | | | | | only needed there. llvm-svn: 219418
* [PPC64] VSX indexed-form loads use wrong instruction formatBill Schmidt2014-10-091-4/+4
| | | | | | | | | | | | | | | | | | The VSX instruction definitions for lxsdx, lxvd2x, lxvdsx, and lxvw4x incorrectly use the XForm_1 instruction format, rather than the XX1Form instruction format. This is likely a pasto when creating these instructions, which were based on lvx and so forth. This patch uses the correct format. The existing reformatting test (test/MC/PowerPC/vsx.s) missed this because the two formats differ only in that XX1Form has an extension to the target register field in bit 31. The tests for these instructions used a target register of 7, so the default of 0 in bit 31 for XForm_1 didn't expose a problem. For register numbers 32-63 this would be noticeable. I've changed the test to use higher register numbers to verify my change is effective. llvm-svn: 219416
* Sink DwarfDebug::constructLexicalScopeDIE into DwarfCompileUnitDavid Blaikie2014-10-094-23/+21
| | | | llvm-svn: 219414
* Missing reformattingDavid Blaikie2014-10-091-1/+1
| | | | llvm-svn: 219413
* Sink DwarfDebug::constructInlinedScopeDIE into DwarfCompileUnitDavid Blaikie2014-10-094-44/+50
| | | | | | | | | | | This introduces access to the AbstractSPDies map from DwarfDebug so DwarfCompileUnit can access it. Eventually this'll sink down to DwarfFile, but it'll still be generically accessible - not much encapsulation to provide it. (constructInlinedScopeDIE could stay further up, in DwarfFile to avoid exposing this - but I don't think that's particularly better) llvm-svn: 219411
* [InstCombine] Fix wrong folding of constant comparisons involving ashr and ↵Andrea Di Biagio2014-10-091-1/+2
| | | | | | | | | | | | | | negative values. This patch fixes a bug in method InstCombiner::FoldCmpCstShrCst where we wrongly computed the distance between the highest bits set of two negative values. This fixes PR21222. Differential Revision: http://reviews.llvm.org/D5700 llvm-svn: 219406
* [AArch64] Enable partial & runtime unrolling on cortex-a57.Kevin Qin2014-10-092-0/+14
| | | | llvm-svn: 219401
* Object, COFF: Move the VirtualSize/SizeOfRawData logic to getSectionSizeDavid Majnemer2014-10-091-18/+23
| | | | | | | | While getSectionContents was updated to do the right thing, getSectionSize wasn't. Move the logic to getSectionSize and leverage it from getSectionContents. llvm-svn: 219391
* [AVX512] Extended avx512_binop_rm for AVX512VL subsets.Robert Khasanov2014-10-091-53/+76
| | | | | | | Added avx512_binop_rm_vl multiclass for VL subset Added encoding tests llvm-svn: 219390
* Object, COFF: Cap the section contents to min(VirtualSize, SizeOfRawData)David Majnemer2014-10-091-5/+19
| | | | | | | | | | | | | | | | It is not useful to return the data beyond VirtualSize it's less than SizeOfRawData. An implementation detail of COFF requires the section size to be rounded up to a multiple of FileAlignment; this means that SizeOfRawData is not representative of how large the section is. Instead, we should cap it to VirtualSize when this occurs as it represents the true size of the section. Note that this is only relevant in executable files because this rounding doesn't occur in object files (and VirtualSize is always zero). llvm-svn: 219388
* Remove more calls to getSubtargetImpl from the schedulers andEric Christopher2014-10-093-24/+17
| | | | | | remove cached or unnecessary TargetMachines. llvm-svn: 219387
* Use triple's isiOS() and isOSDarwin() methods.Bob Wilson2014-10-094-6/+5
| | | | | | | These methods are already used in lots of places. This makes things more consistent. NFC. llvm-svn: 219386
* Object: Add range iterators for COFF import/export tableRui Ueyama2014-10-091-0/+26
| | | | llvm-svn: 219383
* Remove unused argument to CreateTargetScheduleState and changeEric Christopher2014-10-097-20/+16
| | | | | | | the TargetMachine to a TargetSubtargetInfo since everything we wanted is off of that. llvm-svn: 219382
* Remove uses of getSubtargetImpl from ResourcePriorityQueue andEric Christopher2014-10-091-7/+5
| | | | | | replace them with calls off of the MachineFuncton. llvm-svn: 219381
* Remove the uses of getSubtargetImpl from InstrEmitter and removeEric Christopher2014-10-092-9/+6
| | | | | | the now unused TargetMachine variable. llvm-svn: 219379
* Use the subtarget on the dag to get TargetFrameLowering ratherEric Christopher2014-10-092-2/+2
| | | | | | than off the target machine. llvm-svn: 219378
* Remove uses of the TargetMachine from FunctionLoweringInfoEric Christopher2014-10-092-15/+11
| | | | | | via caching TargetLowering and using the MachineFunction. llvm-svn: 219375
* Push DwarfDebug::attachRangesOrLowHighPC down into DwarfCompileUnitDavid Blaikie2014-10-094-15/+15
| | | | llvm-svn: 219372
* Sink DwarfDebug::addScopeRangeList down into DwarfCompileUnitDavid Blaikie2014-10-094-37/+43
| | | | | | | | | | | | | (& add a few accessors/make a couple of things public for this - it's a bit of a toss-up, but I think I prefer it this way, keeping some more of the meaty code down in DwarfCompileUnit - if only to make for smaller implementation files, etc) I think we could simplify range handling a bit if we removed the range lists from each unit and just put a single range list on DwarfDebug, similar to address pooling. llvm-svn: 219370
* Remove unnecessary include.Eric Christopher2014-10-081-1/+0
| | | | llvm-svn: 219368
* Use both the cached TLI and the subtarget off of the DAG inEric Christopher2014-10-081-15/+10
| | | | | | the DAG combiner. llvm-svn: 219367
* Remove getSubtargetImpl calls from FastISel, we can get it fromEric Christopher2014-10-081-6/+5
| | | | | | the MachineFunction where it's already cached. llvm-svn: 219366
* Sink DwarfUnit::addSectionDelta into DwarfCompileUnit, the only place it's ↵David Blaikie2014-10-084-14/+12
| | | | | | needed. llvm-svn: 219364
* [AVX512] Rename AVX512_masking* to AVX512_maskable*Adam Nemet2014-10-081-69/+69
| | | | | | | | | | | | | | | | No functional change. This is the current AVX512_maskable multiclass hierarchy: maskable_custom / \ / \ maskable_common maskable_in_asm / \ / \ maskable maskable_3src llvm-svn: 219363
* [AVX512] Intrinsics for vextract*x4Adam Nemet2014-10-081-0/+23
| | | | | | | | This adds the Pat<>'s for the intrinsics. These are necessary because we don't lower these intrinsics to SDNodes but match them directly. See the rational in the previous commit. llvm-svn: 219362
* [AVX512] Add asm-only support for vextract*x4 masking variantsAdam Nemet2014-10-081-7/+19
| | | | | | | | | | | | | | | | These derive from the new asm-only masking definitions. Unfortunately I wasn't able to find a ISel pattern that we could legally generate for the masking variants. The problem is that since the destination is v4* we would need VK4 register classes and v4i1 value types to express the masking. These are however not legal types/classes in AVX512f but only in VL, so things get complicated pretty quickly. We can revisit this question later if we have a more pressing need to express something like this. So the ISel patterns are empty for the masking instructions and the next patch will add Pat<>s instead to match the intrinsics calls with instructions. llvm-svn: 219361
* [AVX512] Move DAG for all-zero node to X86VectorVTInfoAdam Nemet2014-10-081-3/+6
| | | | | | | | | | No functional change. No change in X86.td.expanded except for the appearance of the new attributes. The new attributes will be used in the subsequent patch. llvm-svn: 219360
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