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* use range-based for loop; NFCISanjay Patel2016-03-081-13/+12
| | | | llvm-svn: 262956
* fix variable name; NFCSanjay Patel2016-03-081-3/+3
| | | | llvm-svn: 262953
* use range-based loop; NFCISanjay Patel2016-03-081-3/+2
| | | | llvm-svn: 262952
* Revert r262759 and r262760.Quentin Colombet2016-03-081-9/+0
| | | | | | | | The fix consisting in using the library call for atomic compare and swap when the instruction is not safe to use may be incorrect. Indeed the library call may not exist on all platform. In other words, we need a better fix! llvm-svn: 262943
* [AArch64] Add MMOs to unscaled pairs.Chad Rosier2016-03-081-3/+2
| | | | | | | Test to be committed in follow up commit, per discussion in D17097. http://reviews.llvm.org/D17097 llvm-svn: 262942
* rangify, fix function names; NFCISanjay Patel2016-03-081-27/+22
| | | | llvm-svn: 262940
* Invoke DAG postprocessing in the post-RA schedulerKrzysztof Parzyszek2016-03-081-0/+2
| | | | | | | This was inadvertently omitted from r262774, which added the mutation interface. llvm-svn: 262939
* don't repeat function names in documentation comments; NFCSanjay Patel2016-03-081-4/+4
| | | | llvm-svn: 262937
* [ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC)Artyom Skrobov2016-03-083-107/+74
| | | | | | | | | | Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
* Revert r262599 "[X86][SSE] Improve vector ZERO_EXTEND by combining to ↵Hans Wennborg2016-03-082-42/+10
| | | | | | | | ZERO_EXTEND_VECTOR_INREG" This caused PR26870. llvm-svn: 262935
* Add DAG mutation interface to the DFA packetizerKrzysztof Parzyszek2016-03-081-0/+24
| | | | llvm-svn: 262930
* AVX512: Add extract_subvector patterns v8i1->v4i1 , v4i1->v2i1.Igor Breger2016-03-081-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D17953 llvm-svn: 262929
* Revert "[InstCombine] Combine A->B->A BitCast"Junmo Park2016-03-082-104/+0
| | | | | | This reverts commit r262670 due to compile failure. llvm-svn: 262916
* Fix evaluation order. Spotted by Alexander Riccio!Peter Collingbourne2016-03-081-1/+1
| | | | llvm-svn: 262907
* [Power9] Implement new vsx instructions: load, store instructions for vector ↵Kit Barton2016-03-087-0/+214
| | | | | | | | | | | | | | | | | | | | and scalar We follow the comments mentioned in http://reviews.llvm.org/D16842#344378 to implement this new patch. This patch implements the following vsx instructions: Vector load/store: lxv lxvx lxvb16x lxvl lxvll lxvh8x lxvwsx stxv stxvb16x stxvh8x stxvl stxvll stxvx Scalar load/store: lxsd lxssp lxsibzx lxsihzx stxsd stxssp stxsibx stxsihx 21 instructions Phabricator: http://reviews.llvm.org/D16919 llvm-svn: 262906
* [WebAssembly] Update for spec change from tableswitch to br_table.Dan Gohman2016-03-085-18/+18
| | | | | | | Also note that the operand order changed; the default label is now listed after the regular labels. llvm-svn: 262903
* Re-apply "SelectionDAG: Store SDNode operands in an ArrayRecycler"Justin Bogner2016-03-081-143/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This re-applies r262886 with a fix for 32 bit platforms that have 8 byte pointer alignment, effectively reverting r262892. Original Message: Currently some SDNode operands are malloc'd, some are stored inline in subclasses of SDNode, and some are thrown into a BumpPtrAllocator. This scheme is complex, inconsistent, and makes refactoring SDNodes fairly difficult. Instead, we can allocate all of the operands using an ArrayRecycler that wraps a BumpPtrAllocator. This keeps the cache locality when iterating operands, improves locality when iterating SDNodes without looking at operands, and vastly simplifies the ownership semantics. It also means we stop overallocating SDNodes by 2-3x and will make it simpler to fix the rampant undefined behaviour we have in how we mutate SDNodes from one kind to another (See llvm.org/pr26808). This is NFC other than the changes in memory behaviour, and I ran some LNT tests to make sure this didn't hurt compile time. Not many tests changed: there were a couple of 1-2% regressions reported, but there were more improvements (of up to 4%) than regressions. llvm-svn: 262902
* [MIR] Change the token name for '<' and '>' to be consitent with the LLVM IR ↵Quentin Colombet2016-03-082-4/+4
| | | | | | | | parser. Thanks to Ahmed Bougacha for noticing! llvm-svn: 262899
* [AArch64] Initialize GlobalISel as part of the target initialization.Quentin Colombet2016-03-081-0/+2
| | | | llvm-svn: 262897
* [GlobalISel] Introduce initializer method to support start/stop-after features.Quentin Colombet2016-03-084-25/+33
| | | | llvm-svn: 262896
* [MIR] Teach the parser/printer that generic virtual registers do not need a ↵Quentin Colombet2016-03-082-8/+20
| | | | | | register class. llvm-svn: 262893
* Revert "SelectionDAG: Store SDNode operands in an ArrayRecycler"Justin Bogner2016-03-081-118/+143
| | | | | | | | | Looks like the largest SDNode is different between 32 and 64 bit now, so this is breaking 32 bit bots. Reverting while I figure out a fix. This reverts r262886. llvm-svn: 262892
* A couple more UB fixes for C++14 sized deallocation.Richard Smith2016-03-081-0/+4
| | | | llvm-svn: 262891
* [MIR] Teach the parser how to parse complex types of generic machine ↵Quentin Colombet2016-03-083-14/+35
| | | | | | | | instructions. By complex types, I mean aggregate or vector types. llvm-svn: 262890
* SelectionDAG: Store SDNode operands in an ArrayRecyclerJustin Bogner2016-03-081-143/+118
| | | | | | | | | | | | | | | | | | | | | | | Currently some SDNode operands are malloc'd, some are stored inline in subclasses of SDNode, and some are thrown into a BumpPtrAllocator. This scheme is complex, inconsistent, and makes refactoring SDNodes fairly difficult. Instead, we can allocate all of the operands using an ArrayRecycler that wraps a BumpPtrAllocator. This keeps the cache locality when iterating operands, improves locality when iterating SDNodes without looking at operands, and vastly simplifies the ownership semantics. It also means we stop overallocating SDNodes by 2-3x and will make it simpler to fix the rampant undefined behaviour we have in how we mutate SDNodes from one kind to another (See llvm.org/pr26808). This is NFC other than the changes in memory behaviour, and I ran some LNT tests to make sure this didn't hurt compile time. Not many tests changed: there were a couple of 1-2% regressions reported, but there were more improvements (of up to 4%) than regressions. llvm-svn: 262886
* [MIR] Teach the printer how to print complex types for generic machine ↵Quentin Colombet2016-03-081-1/+2
| | | | | | | | | | | | | instructions. Before this change, we would get the type definition in the middle of the instruction. E.g., %0(48) = G_ADD %struct_alias = type { i32, i16 } %edi, %edi Now, we have just the expected type name: %0(48) = G_ADD %struct_alias %edi, %edi llvm-svn: 262885
* [AsmParser] Expose an API to parse a string starting with a type.Quentin Colombet2016-03-083-5/+27
| | | | | | | | | | | | Without actually parsing a type it is difficult to perdict where the type definition ends. In other words, instead of expecting the user of the parser API to hand over only the relevant bits of the string being parsed, take the whole string, parse the type, and get back the number of characters that have been read. This will be used by the MIR testing infrastructure. llvm-svn: 262884
* Revert revisions 262636, 262643, 262679, and 262682.Easwaran Raman2016-03-085-230/+46
| | | | llvm-svn: 262883
* [MIR] Print the type of generic machine instructions.Quentin Colombet2016-03-081-0/+4
| | | | llvm-svn: 262880
* [MIR] Teach the mir parser about types on generic machine instructions.Quentin Colombet2016-03-081-0/+33
| | | | llvm-svn: 262879
* [tsan] Add support for pointer typed atomic stores, loads, and cmpxchgAnna Zaks2016-03-071-8/+31
| | | | | | | | | | TSan instrumentation functions for atomic stores, loads, and cmpxchg work on integer value types. This patch adds casts before calling TSan instrumentation functions in cases where the value is a pointer. Differential Revision: http://reviews.llvm.org/D17833 llvm-svn: 262876
* [MachineInstr] Get rid of some GlobalISel ifdefs.Quentin Colombet2016-03-071-5/+24
| | | | | | | | Now the type API is always available, but when global-isel is not built the implementation does nothing. Note: The implementation free of ifdefs is WIP and tracked here in PR26576. llvm-svn: 262873
* [IR] Provide an API to skip the details of a structured type when printed.Quentin Colombet2016-03-071-1/+4
| | | | | | | The mir infrastructure will need this for generic instructions and currently this feature was only available through the anonymous TypePrinter class. llvm-svn: 262869
* [AsmParser] Add a function to parse a standalone type.Quentin Colombet2016-03-073-0/+26
| | | | | | | This is useful for MIR serialization. Indeed generic machine instructions must have a type and we don't want to duplicate the logic in the MIParser. llvm-svn: 262868
* [MIR] Teach the MIPrinter about size for generic virtual registers.Quentin Colombet2016-03-071-4/+12
| | | | llvm-svn: 262867
* AMDGPU: Match more med3 integer patternsMatt Arsenault2016-03-072-0/+33
| | | | llvm-svn: 262864
* [MIR] Teach the parser how to handle the size of generic virtual registers.Quentin Colombet2016-03-071-8/+36
| | | | llvm-svn: 262862
* [MachineRegisterInfo] Add a method to set the size of a virtual register a ↵Quentin Colombet2016-03-071-0/+4
| | | | | | | | posteriori. This is required for mir testing. llvm-svn: 262861
* Small formating change in Core.cpp . NFCAmaury Sechet2016-03-071-3/+1
| | | | llvm-svn: 262860
* [MachineRegisterInfo] Get rid of the global-isel ifdefs.Quentin Colombet2016-03-071-6/+3
| | | | | | | One additional pointer is not a big deal size-wise and it makes the code much nicer! llvm-svn: 262856
* AMDGPU: Remove a fixme for ptrrtoint handlingMatt Arsenault2016-03-071-1/+0
| | | | llvm-svn: 262854
* AMDGPU: Move function only used by R600Matt Arsenault2016-03-074-18/+17
| | | | llvm-svn: 262853
* DAGCombiner: Check legality before creating extract_vector_eltMatt Arsenault2016-03-071-1/+3
| | | | | | Problem not hit by any in tree target. llvm-svn: 262852
* [LoopDataPrefetch] If prefetch distance is not set, skip passAdam Nemet2016-03-071-2/+5
| | | | | | | | | | | | | | This lets select sub-targets enable this pass. The patch implements the idea from the recent llvm-dev thread: http://thread.gmane.org/gmane.comp.compilers.llvm.devel/94925 The goal is to enable the LoopDataPrefetch pass for the Cyclone sub-target only within Aarch64. Positive and negative tests will be included in an upcoming patch that enables selective prefetching of large-strided accesses on Cyclone. llvm-svn: 262844
* [ms-inline-asm][AVX512] Add ability to use k registers in MS inline asm + ↵Marina Yatsina2016-03-072-1/+37
| | | | | | | | | | | | | | | | | | | | | | fix bag with curly braces Until now curly braces could only be used in MS inline assembly to mark block start/end. All curly braces were removed completely at a very early stage. This approach caused bugs like: "m{o}v eax, ebx" turned into "mov eax, ebx" without any error. In addition, AVX-512 added special operands (e.g., k registers), which are also surrounded by curly braces that mark them as such. Now, we need to keep the curly braces and identify at a later stage if they are marking block start/end (if so, ignore them), or surrounding special AVX-512 operands (if so, parse them as such). This patch fixes the bug described above and enables the use of AVX-512 special operands. This commit is the the llvm part of the patch. The clang part of the review is: http://reviews.llvm.org/D17766 The llvm part of the review is: http://reviews.llvm.org/D17767 Differential Revision: http://reviews.llvm.org/D17767 llvm-svn: 262843
* Revert "Enable LoopLoadElimination by default"Adam Nemet2016-03-071-2/+2
| | | | | | | | | | This reverts commit r262250. It causes SPEC2006/gcc to generate wrong result (166.s) in AArch64 when running with *ref* data set. The error happens with "-Ofast -flto -fuse-ld=gold" or "-O3 -fno-strict-aliasing". llvm-svn: 262839
* [memdep] Switch to range based for loops.Chandler Carruth2016-03-071-73/+46
| | | | llvm-svn: 262831
* [DFSan] Remove an overly aggressive assert reported in PR26068.Chandler Carruth2016-03-071-4/+0
| | | | | | | | | | | | This code has been successfully used to bootstrap libc++ in a no-asserts mode for a very long time, so the code that follows cannot be completely incorrect. I've added a test that shows the current behavior for this kind of code with DFSan. If it is desirable for DFSan to do something special when processing an invoke of a variadic function, it can be added, but we shouldn't keep an assert that we've been ignoring due to release builds anyways. llvm-svn: 262829
* [memdep] Switch a function to return true on success instead of false.Chandler Carruth2016-03-071-9/+9
| | | | | | | | This is much more clear and less surprising IMO. It also makes things more consistent with the increasingly large chunk of LLVM code that assumes true-on-success. llvm-svn: 262826
* [memdep] Cleanup the implementation doxygen comments and removeChandler Carruth2016-03-071-80/+35
| | | | | | | | | | duplicated comments. In several cases these had diverged making them especially nice to canonicalize. I checked to make sure we weren't losing important information of course. llvm-svn: 262825
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