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* Make TypeBasedAliasAnalysis default to doing nothing, with a command-lineDan Gohman2010-10-181-0/+10
| | | | | | option to enable it. llvm-svn: 116722
* Use chaining in TypeBasedAliasAnalysis::pointsToConstantMemory.Dan Gohman2010-10-181-1/+4
| | | | llvm-svn: 116721
* Make BasicAliasAnalysis a normal AliasAnalysis implementation whichDan Gohman2010-10-182-11/+29
| | | | | | | | | | | | does normal initialization and normal chaining. Change the default AliasAnalysis implementation to NoAlias. Update StandardCompileOpts.h and friends to explicitly request BasicAliasAnalysis. Update tests to explicitly request -basicaa. llvm-svn: 116720
* Make the bots happy.Rafael Espindola2010-10-181-1/+3
| | | | llvm-svn: 116719
* Added a handful of x86-32 instructions that were missing so that llvm-mc wouldKevin Enderby2010-10-183-1/+51
| | | | | | | | | | be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. llvm-svn: 116716
* Produce a R_386_PLT32 when needed. Moved the default cases of switches to theRafael Espindola2010-10-181-7/+13
| | | | | | start for consistency. llvm-svn: 116715
* ARM addrmode4 instructions (ldm, stm and friends) can't encode an immediateJim Grosbach2010-10-181-1/+2
| | | | | | | | offset for stack references. Make sure we take that into account when deciding whether to reserver an emergency spill slot for the register scavenger. rdar://8559625 llvm-svn: 116714
* Grammar tweak.Jim Grosbach2010-10-181-1/+1
| | | | llvm-svn: 116712
* Handle GOTOFF correctly on i386.Rafael Espindola2010-10-181-5/+15
| | | | llvm-svn: 116711
* Trivial grammar tweak.Jim Grosbach2010-10-181-1/+1
| | | | llvm-svn: 116710
* Improve lowering of sext to i128 on SPU.Kalle Raiskila2010-10-181-2/+7
| | | | | | | | The old algorithm inserted a 'rotqmbyi' instruction which was both redundant and wrong - it made shufb select bytes from the wrong end of the input quad. llvm-svn: 116701
* Remove the check for invalid calling conventions. Testing shows that they'reEric Christopher2010-10-181-4/+1
| | | | | | working just fine. llvm-svn: 116698
* Lift arg promotion from the X86 backend. This should be unified at some point.Eric Christopher2010-10-181-3/+57
| | | | llvm-svn: 116694
* Now that we handle all allocas via a non-SP reg offset remove all of theEric Christopher2010-10-171-79/+39
| | | | | | special case handling for ARM::SP. llvm-svn: 116688
* std::string cleanup.Benjamin Kramer2010-10-171-1/+1
| | | | llvm-svn: 116686
* Fix a typo and silence unused variable warnings in -Asserts build.Benjamin Kramer2010-10-171-4/+2
| | | | llvm-svn: 116685
* Allow more load types to be materialized through the allocas.Eric Christopher2010-10-171-1/+1
| | | | llvm-svn: 116683
* Build with RTTI and exceptions disabled. Only in GCC for now.Oscar Fuentes2010-10-173-0/+10
| | | | llvm-svn: 116682
* Optimize GEP off of intermediate allocas.Eric Christopher2010-10-171-14/+46
| | | | llvm-svn: 116681
* Fix comment.Eric Christopher2010-10-171-1/+1
| | | | llvm-svn: 116680
* Turn on AddOperator folding in GEP.Eric Christopher2010-10-171-1/+1
| | | | llvm-svn: 116679
* Use the i12 immediate versions of the load instructions - they're handledEric Christopher2010-10-171-6/+6
| | | | | | more in the post-passes. llvm-svn: 116678
* Add a MCObjectFormat class so that code common to all targets that use aRafael Espindola2010-10-167-48/+108
| | | | | | | | | | | | single object format can be shared. This also adds support for mov zed+(bar-foo), %eax on ELF and COFF targets. llvm-svn: 116675
* Eliminate some calls to Value::getNameStr.Benjamin Kramer2010-10-163-5/+5
| | | | llvm-svn: 116670
* MC-COFF: Add support for default-null weak externals.Michael J. Spencer2010-10-162-48/+62
| | | | llvm-svn: 116666
* X86-Windows: Emit an undefined global __fltused symbol when targeting WindowsMichael J. Spencer2010-10-163-1/+29
| | | | | | if any floating point arguments are passed to an external function. llvm-svn: 116665
* Whitespace!Michael J. Spencer2010-10-162-69/+69
| | | | llvm-svn: 116664
* MC/AsmParser: Report .stabs directive as unsupported.Daniel Dunbar2010-10-161-0/+9
| | | | llvm-svn: 116659
* More machine LICM work. It now tracks register pressure for path from ↵Evan Cheng2010-10-161-69/+155
| | | | | | preheader to current BB and use the information determine whether hoisting is worthwhile. llvm-svn: 116654
* Fix some funky formatting that got through.Eric Christopher2010-10-161-1/+3
| | | | llvm-svn: 116653
* ARMCodeEmitter::emitMiscInstruction is dead. Long liveBill Wendling2010-10-151-45/+1
| | | | | | ARMCodeEmitter::emitMiscInstruction! llvm-svn: 116644
* Make sure offset is 0 for load/store register to the stack call.Eric Christopher2010-10-151-2/+2
| | | | llvm-svn: 116640
* Generalize MemCpyOpt's handling of call slot forwarding to function properly ↵Owen Anderson2010-10-151-18/+48
| | | | | | | | when the call slot forwarding is implemented with a load/store pair rather than a memcpy. llvm-svn: 116637
* Formatting.Eric Christopher2010-10-151-4/+4
| | | | llvm-svn: 116635
* Fix else if -> if in store machinery.Eric Christopher2010-10-151-1/+1
| | | | llvm-svn: 116628
* Reformatting. No functionalogicality changes.Bill Wendling2010-10-151-19/+15
| | | | llvm-svn: 116625
* Refactor ARM fast-isel reg + offset to be a base + offset.Eric Christopher2010-10-151-40/+45
| | | | llvm-svn: 116622
* Encoding information for the various ARM saturating add/sub instructions.Jim Grosbach2010-10-151-46/+53
| | | | llvm-svn: 116612
* ARM binary encoding information for RSB and RSC instructions.Jim Grosbach2010-10-151-44/+104
| | | | llvm-svn: 116604
* Don't mark argument value stores as immutable, as otherwise the post-RAJim Grosbach2010-10-151-1/+1
| | | | | | | scheduler may reorder loads from them before the stores and other such badness. PR8347. Patch by David Meyer llvm-svn: 116602
* Use simple RegState::Define flag instead of getDefRegState(true).Bob Wilson2010-10-151-5/+5
| | | | llvm-svn: 116601
* Refactor alias handling to AliasedSymbol.Rafael Espindola2010-10-151-13/+15
| | | | llvm-svn: 116600
* Expand GEP handling for constant offsets.Eric Christopher2010-10-151-23/+44
| | | | llvm-svn: 116594
* When expanding the MOVsr[la]_flag pseudos, the CPSR implicit def becomesJim Grosbach2010-10-151-2/+1
| | | | | | an explicit def. Make sure to capture that properly. rdar://8556556 llvm-svn: 116591
* ARM mode encoding information for UBFX and SBFX instructions.Jim Grosbach2010-10-153-6/+35
| | | | llvm-svn: 116588
* Remove unused accessor.Jakob Stoklund Olesen2010-10-151-2/+0
| | | | llvm-svn: 116580
* Refactor code a bit and avoid creating unnecessary entries in the stringRafael Espindola2010-10-151-19/+19
| | | | | | map. llvm-svn: 116579
* Remove unused ARMISD::AND selection DAG node.Bob Wilson2010-10-154-13/+0
| | | | llvm-svn: 116566
* ARM instructions that are both predicated and set the condition codesBob Wilson2010-10-151-1/+1
| | | | | | | | | | have been printed with the "S" modifier after the predicate. With ARM's unified syntax, they are supposed to go in the other order. We fixed this for Thumb when we switched to unified syntax but missed changing it for ARM. Apparently we don't generate these instructions often because no one noticed until now. Thanks to Bill Wendling for the testcase! llvm-svn: 116563
* Encoding info for extension instructions.Jim Grosbach2010-10-151-0/+8
| | | | llvm-svn: 116560
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