summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* Simplify code. No functionality change.Jakub Staszak2013-03-091-2/+2
| | | | llvm-svn: 176765
* Use the correct index variable. This is the meat of what was supposed to be inNick Lewycky2013-03-091-1/+1
| | | | | | r176751. Also, learn a lesson about applying patches by hand/eyeball. llvm-svn: 176764
* Commit the right files for r176762. Sigh.Nick Lewycky2013-03-091-3/+3
| | | | llvm-svn: 176763
* We need a shndx if the number of sections breaks SHN_LORESERVE. This conditionNick Lewycky2013-03-091-1/+1
| | | | | | for choosing to emit a shndx was simply testing the wrong variable. llvm-svn: 176762
* Fix bug introduced in r176616 when making function identifier numbers stable.Nick Lewycky2013-03-091-5/+3
| | | | | | Count the subprograms, not the compile units. llvm-svn: 176751
* Don't emit the extra checksum into the .gcda file if the user hasn't asked forNick Lewycky2013-03-091-4/+6
| | | | | | | | it. Fortunately, versions of gcov that predate the extra checksum also ignore any extra data, so this isn't a problem. There will be a matching commit in compiler-rt. llvm-svn: 176745
* Remove wrong and unnecessary assertion.Jakob Stoklund Olesen2013-03-081-1/+0
| | | | | | | PHIs are allowed to have multiple operand pairs per predecessor, and this code works just fine when it happens. llvm-svn: 176734
* Disable statistics on Release builds and move tests that depend on -stats.Jan Wen Voung2013-03-083-19/+31
| | | | | | | | | | | | | | | | | Summary: Statistics are still available in Release+Asserts (any +Asserts builds), and stats can also be turned on with LLVM_ENABLE_STATS. Move some of the FastISel stats that were moved under DEBUG() back out of DEBUG(), since stats are disabled across the board now. Many tests depend on grepping "-stats" output. Move those into a orig_dir/Stats/. so that they can be marked as unsupported when building without statistics. Differential Revision: http://llvm-reviews.chandlerc.com/D486 llvm-svn: 176733
* Clean up out-of-date comments and some stray whitespaceEli Bendersky2013-03-081-1/+1
| | | | llvm-svn: 176729
* Early exit from getAllocationData() and isFreeCall() for intrinsics.Michael Ilseman2013-03-081-1/+5
| | | | llvm-svn: 176722
* Assert to bounds check MDNode::getOperand.David Blaikie2013-03-081-0/+1
| | | | | | | | | The getOperandPtr utility already bounds checks, but allows one-off-the-end. This assert should catch the cases that could previously have been dereferencing these one-off-the-end pointer. Happily, no cases of this came up with this change. llvm-svn: 176721
* Remove trailing whitespaceMichael Ilseman2013-03-081-5/+5
| | | | llvm-svn: 176720
* Remove -print-dbginfo as it is unused & bitrotten.David Blaikie2013-03-083-226/+0
| | | | | | | | This pass hasn't been touched in two years & would fail with assertions against the current debug info metadata format (the only test case for it still uses a many-versions old debug info metadata format) llvm-svn: 176707
* Rewrite the physreg part of findLastUseBefore().Jakob Stoklund Olesen2013-03-081-24/+36
| | | | | | | | | To find the last use of a register unit, start from the bottom and scan upwards until a user is found. <rdar://problem/13353090> llvm-svn: 176706
* Remove default from fully covered switch.Benjamin Kramer2013-03-081-2/+1
| | | | llvm-svn: 176703
* Insert the reduction start value into the first bypass block to preserve ↵Benjamin Kramer2013-03-081-1/+1
| | | | | | | | domination. Fixes PR15344. llvm-svn: 176701
* R600: Optimize another selectcc caseTom Stellard2013-03-081-11/+20
| | | | | | | | fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne -> selectcc x, y, a, b, cc Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 176700
* R600: Improve custom lowering of select_ccTom Stellard2013-03-082-37/+42
| | | | | | | | | Two changes: 1. Prefer SET* instructions when possible 2. Handle the CND*_INT case with floating-point args Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 176699
* R600: Change operation action from Custom to Expand for BR_CCTom Stellard2013-03-082-43/+2
| | | | | Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 176698
* R600: Change operation action from Custom to Expand for SETCCTom Stellard2013-03-082-46/+2
| | | | | Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 176697
* R600: Set BooleanContents to ZeroOrNegativeOneBooleanContentTom Stellard2013-03-081-0/+1
| | | | | Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 176696
* LegalizeDAG: Respect the result of TLI.getBooleanContents() when expanding SETCCTom Stellard2013-03-081-1/+13
| | | | llvm-svn: 176695
* DAGCombiner: Use correct value type for checking legality of BR_CC v3Tom Stellard2013-03-087-7/+26
| | | | | | | | | | | | | LegalizeDAG.cpp uses the value of the comparison operands when checking the legality of BR_CC, so DAGCombiner should do the same. v2: - Expand more BR_CC value types for NVPTX v3: - Expand correct BR_CC value types for Hexagon, Mips, and XCore. llvm-svn: 176694
* Hexagon: Add patterns for zero extended loads from i1->i64.Jyotsna Verma2013-03-082-0/+24
| | | | llvm-svn: 176689
* AArch64: expand sincos operations, we don't support them.Tim Northover2013-03-081-0/+3
| | | | | | Patch based on Mans Rullgard's. llvm-svn: 176688
* R600/SI: Use source schedulerMichel Danzer2013-03-081-0/+2
| | | | | | | | | | | | | | | This is certainly not the last word on scheduling for this target, but right now this allows a few apps to run / finish with radeonsi, most notably UT2004 / Lightsmark. They fail to compile some shaders with the default scheduler because it ends up trying to spill registers, which we don't support yet (and which is probably a bad idea in general for performance if it can be avoided). NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176687
* Add -verify-misched option.Andrew Trick2013-03-081-0/+9
| | | | | | | | | | This verifies live intervals both before and after scheduling. It's useful for anyone hacking on live interval update. Note that we don't yet pass verification all the time. We don't yet handle updating nonallocatable live intervals perfectly. llvm-svn: 176685
* Revert r176154 in favor of a better approach.Bill Wendling2013-03-082-9/+11
| | | | | | | | | | | | | | | | | | | Code generation makes some basic assumptions about the IR it's been given. In particular, if there is only one 'invoke' in the function, then that invoke won't be going away. However, with the advent of the `llvm.donothing' intrinsic, those invokes may go away. If all of them go away, the landing pad no longer has any users. This confuses the back-end, which asserts. This happens with SjLj exceptions, because that's the model that modifies the IR based on there being invokes, etc. in the function. Remove any invokes of `llvm.donothing' during SjLj EH preparation. This will give us a CFG that the back-end won't be confused about. If all of the invokes in a function are removed, then the SjLj EH prepare pass won't insert the bogus code the relies upon the invokes being there. <rdar://problem/13228754&13316637> llvm-svn: 176677
* Add a getPassName() method.Jakob Stoklund Olesen2013-03-071-0/+1
| | | | llvm-svn: 176669
* Rename isEarlierInSameTrace to isUsefulDominator.Jakob Stoklund Olesen2013-03-071-2/+2
| | | | | | | | | | | | | | In very rare cases caused by irreducible control flow, the dominating block can have the same trace head without actually being part of the trace. As long as such a dominator still has valid instruction depths, it is OK to use it for computing instruction depths. Rename the function to avoid lying, and add a check that instruction depths are computed for the dominator. llvm-svn: 176668
* Keep coding stanard.Jakub Staszak2013-03-071-4/+3
| | | | llvm-svn: 176661
* Don't create IRBuilder if we can return from the method earlier.Jakub Staszak2013-03-071-2/+2
| | | | llvm-svn: 176660
* [fast-isel] Seriously, add support for the expect intrinsic.Chad Rosier2013-03-071-3/+3
| | | | | | rdar://13370942 llvm-svn: 176659
* Replace temporary vectors with arrays.Benjamin Kramer2013-03-071-24/+12
| | | | llvm-svn: 176651
* [fast-isel] Add support for the expect intrinsic.Chad Rosier2013-03-071-0/+5
| | | | | | rdar://13370942 llvm-svn: 176649
* ArrayRefize some code. No functionality change.Benjamin Kramer2013-03-076-41/+29
| | | | llvm-svn: 176648
* Hexagon: Handle i8, i16 and i1 Var Args.Jyotsna Verma2013-03-071-0/+10
| | | | llvm-svn: 176647
* Simplify code. No functionality change.Jakub Staszak2013-03-071-3/+3
| | | | llvm-svn: 176646
* Change NULL to 0.Jakub Staszak2013-03-071-8/+8
| | | | llvm-svn: 176642
* ArrayRef ca accept one element. Simplify code a little bit, also it matches nowJakub Staszak2013-03-071-3/+5
| | | | | | coding in the other places of the file. llvm-svn: 176641
* pre-RA-sched debug-only fixAndrew Trick2013-03-071-2/+4
| | | | llvm-svn: 176638
* Hexagon: Add support to lower block address.Jyotsna Verma2013-03-074-0/+28
| | | | llvm-svn: 176637
* pre-RA-sched assertion fix. This bug was exposed by r176037.Andrew Trick2013-03-071-3/+0
| | | | | | | | | | | | | rdar:13370002 [pre-RA-sched] assertion: released too many times I tracked this down to an earlier hack that is no longer applicable and interfered with normal scheduler logic. With the changes in r176037, it was causing an instruction to be scheduled multiple times. I have an external test case that I tried hard to reduce and failed. I can't even reproduce with llc. llvm-svn: 176636
* X86: Fold EXTRACT_SUBVECTORs of a BUILD_VECTOR into a smaller BUILD_VECTOR.Benjamin Kramer2013-03-071-0/+5
| | | | | | | | | | That can usually be lowered efficiently and is common in sandybridge code. It would be nice to do this in DAGCombiner but we can't insert arbitrary BUILD_VECTORs this late. Fixes PR15462. llvm-svn: 176634
* Fixed a crash when cloning a function into a function withPekka Jaaskelainen2013-03-071-3/+6
| | | | | | | different size argument list and without attributes in the arguments. llvm-svn: 176632
* R600/SI: rework input interpolation v2Christian Konig2013-03-0712-321/+46
| | | | | | | | v2: update CMakeLists.txt as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176626
* R600/SI: remove SI_vs_load_buffer_indexChristian Konig2013-03-072-15/+0
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176625
* R600/SI: remove SGPR address space v2Christian Konig2013-03-075-70/+21
| | | | | | | | v2: fix R600 regressions Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176624
* R600/SI: add proper formal parameter handling for SIChristian Konig2013-03-077-22/+163
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176623
* R600/SI: remove shader type intrinsicChristian Konig2013-03-076-18/+18
| | | | | | | | Just encode the type as target specific attribute. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176622
OpenPOWER on IntegriCloud