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* Compare to an unsigned literal to avoid a -Wsign-compare warning.Chandler Carruth2016-06-111-1/+1
| | | | llvm-svn: 272459
* Use const_cast to cast away constness. This silences a warning.Chandler Carruth2016-06-111-1/+1
| | | | llvm-svn: 272458
* [MCJIT] Update MCJIT and get the fibonacci example working again.Lang Hames2016-06-111-5/+9
| | | | | | | | | | MCJIT will now set the DataLayout on a module when it is added to the JIT, rather than waiting until it is codegen'd, and the runFunction method will finalize the module containing the function to be run before running it. The fibonacci example has been updated to include and link against MCJIT. llvm-svn: 272455
* [AVX512] Add support for lowering v32i16 shuffles with repeated lanes. This ↵Craig Topper2016-06-111-0/+11
| | | | | | allows us to create 512-bit PSHUFLW/PSHUFHW. llvm-svn: 272450
* [AVX512] No need to check for BWI being enabled before lowering v32i16 and ↵Craig Topper2016-06-111-9/+2
| | | | | | v64i8 shuffles. If we get this far the types are already legal which means BWI must be enabled. llvm-svn: 272449
* LiveIntervalAnalysis: findLastUseBefore() must ignore undef uses.Matthias Braun2016-06-111-1/+3
| | | | | | | | | | undef uses are no real uses of a register and must be ignored by findLastUseBefore() so that handleMove() does not produce invalid live intervals in some cases. This fixed http://llvm.org/PR28083 llvm-svn: 272446
* [esan|cfrag] Handle complex GEP instr in the cfrag toolQin Zhao2016-06-101-35/+42
| | | | | | | | | | | | | | | | Summary: Iterates all (except the first and the last) operands within each GEP instruction for instrumentation. Adds test struct_field_gep.ll. Reviewers: aizatsky Subscribers: vitalybuka, zhaoqin, kcc, eugenis, bruening, llvm-commits Differential Revision: http://reviews.llvm.org/D21242 llvm-svn: 272442
* Don't try to rotate a loop more than once - we never do this anyway.Michael Zolotukhin2016-06-101-14/+10
| | | | | | | | | | | | | | | | | | | | | Summary: I can't find a case where we can rotate a loop more than once, and it looks like we never do this. To rotate a loop following conditions should be met: 1) its header should be exiting 2) its latch shouldn't be exiting But after the first rotation the header becomes the new latch, so this condition can never be true any longer. Tested on with an assert on LNT testsuite and make check. Reviewers: hfinkel, sanjoy Subscribers: sebpop, sanjoy, llvm-commits, mzolotukhin Differential Revision: http://reviews.llvm.org/D20181 llvm-svn: 272439
* [pdb] Fix issues with pdb writing.Zachary Turner2016-06-101-1/+1
| | | | | | | | | This fixes an alignment issue by forcing all cached allocations to be 8 byte aligned, and also fixes an issue arising on big endian systems by writing ulittle32_t's instead of uint32_t's in the test. llvm-svn: 272437
* MemorySSA: fix memory access local dominance function for live on entrySebastian Pop2016-06-101-0/+15
| | | | | | | | | A memory access defined on function entry cannot be locally dominated by another memory access. The patch was split from http://reviews.llvm.org/D19338 which exposes the problem. Differential Revision: http://reviews.llvm.org/D21039 llvm-svn: 272436
* [STLExtras] Introduce and use llvm::count_if; NFCSanjoy Das2016-06-103-27/+17
| | | | | | (This is split out from was D21115) llvm-svn: 272435
* [IRTranslator] Support the translation of or.Quentin Colombet2016-06-101-0/+2
| | | | | | Now or instructions get translated into G_OR. llvm-svn: 272433
* [IRTranslator] Refactor to expose a translateBinaryOp method.Quentin Colombet2016-06-101-3/+3
| | | | | | | | This method will be used for every binary operation. NFC. llvm-svn: 272431
* [AArch64] Move comments closer to relevant check. NFC.Chad Rosier2016-06-101-6/+4
| | | | llvm-svn: 272430
* [AArch64] Refactor a check earlier. NFC.Chad Rosier2016-06-101-12/+18
| | | | llvm-svn: 272429
* [x86] enable bitcasted fabs/fneg transformsSanjay Patel2016-06-101-0/+4
| | | | | | | The vector cases don't change because we already have folds in X86ISelLowering to look through and remove bitcasts. llvm-svn: 272427
* [CodeGen] Fix PrologEpilogInserter to avoid duplicate allocation of SEH structsEtienne Bergeron2016-06-101-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When stack-protection is activated and WinEH exceptions is used, the EHRegNode (exception handling registration) is allocated twice on the stack. This was not breaking anything except loosing space on the stack. ``` D:\src\llvm\examples>llc exc2.ll -debug-only=pei alloc FI(0) at SP[-24] alloc FI(1) at SP[-48] <<-- Allocated alloc FI(1) at SP[-72] <<-- Allocated twice!? alloc FI(2) at SP[-76] alloc FI(4) at SP[-80] alloc FI(3) at SP[-84] ``` Reviewers: rnk, majnemer Subscribers: chrisha, llvm-commits Differential Revision: http://reviews.llvm.org/D21188 llvm-svn: 272426
* Remove a few gendered pronouns.Nico Weber2016-06-102-2/+2
| | | | llvm-svn: 272422
* Disable MSan-hostile loop unswitching.Evgeniy Stepanov2016-06-101-0/+18
| | | | | | | | | | | | | Loop unswitching may cause MSan false positive when the unswitch condition is not guaranteed to execute. This is very similar to ASan and TSan special case in llvm::isSafeToSpeculativelyExecute (they don't like speculative loads and stores), but for branch instructions. This is a workaround for PR28054. llvm-svn: 272421
* Move isGuaranteedToExecute out of LICM.Evgeniy Stepanov2016-06-102-59/+57
| | | | | | | Also rename LICMSafetyInfo to LoopSafetyInfo. Both will be used in LoopUnswitch in a separate change. llvm-svn: 272420
* [SystemZ] Support Compare and TrapsZhan Jun Liau2016-06-108-44/+193
| | | | | | | | | | | | Support and generate Compare and Traps like CRT, CIT, etc. Support Trap as legal DAG opcodes and generate "j .+2" for them by default. Add support for Conditional Traps and use the If Converter to convert them into the corresponding compare and trap opcodes. Differential Revision: http://reviews.llvm.org/D21155 llvm-svn: 272419
* AMDGPU/SI: Don't use fixup_si_rodata for scratch rsrc relocationsTom Stellard2016-06-102-1/+7
| | | | | | | | | | | | | | | Summary: We need to set the fixup type to FK_Data_4 for the SCRATCH_RSRC_DWORD[01] symbols, since these require absolute relocations, and fixup_si_rodata is for relative relocations. Reviewers: arsenm, kzhuravl Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: http://reviews.llvm.org/D21153 llvm-svn: 272417
* Interprocedural Register Allocation (IPRA): add a Transformation PassMehdi Amini2016-06-103-0/+135
| | | | | | | | | | | | Adds a MachineFunctionPass that scans the body to find calls, and update the register mask with the one saved by the RegUsageInfoCollector analysis in PhysicalRegisterUsageInfo. Patch by Vivek Pandya <vivekvpandya@gmail.com> Differential Revision: http://reviews.llvm.org/D21180 llvm-svn: 272414
* Add a period. NFC.Chad Rosier2016-06-101-1/+1
| | | | llvm-svn: 272410
* Fix whitespace. NFC.Chad Rosier2016-06-101-1/+1
| | | | llvm-svn: 272409
* [X86] Add costs for SSE zext/sext to v4i64 to TTIMichael Kuperstein2016-06-101-0/+14
| | | | | | | | | The costs are somewhat hand-wavy, but should be much closer to the truth than what we get from BasicTTI. Differential Revision: http://reviews.llvm.org/D21156 llvm-svn: 272406
* Interprocedural Register Allocation (IPRA) AnalysisMehdi Amini2016-06-105-0/+244
| | | | | | | | | | | | | | | | | | | | | | | Add an option to enable the analysis of MachineFunction register usage to extract the list of clobbered registers. When enabled, the CodeGen order is changed to be bottom up on the Call Graph. The analysis is split in two parts, RegUsageInfoCollector is the MachineFunction Pass that runs post-RA and collect the list of clobbered registers to produce a register mask. An immutable pass, RegisterUsageInfo, stores the RegMask produced by RegUsageInfoCollector, and keep them available. A future tranformation pass will use this information to update every call-sites after instruction selection. Patch by Vivek Pandya <vivekvpandya@gmail.com> Differential Revision: http://reviews.llvm.org/D20769 llvm-svn: 272403
* [AArch64] Add preferred alignments for Exynos M1Evandro Menezes2016-06-103-2/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D21203 llvm-svn: 272400
* [Hexagon] Remove incorrect offset scalingKrzysztof Parzyszek2016-06-101-4/+2
| | | | llvm-svn: 272399
* Test commitRoman Shirokiy2016-06-101-3/+3
| | | | llvm-svn: 272393
* [AMDGPU] AsmParser: Support for sext() modifier in SDWA. Some code cleaning ↵Sam Kolton2016-06-105-257/+348
| | | | | | | | | | | | | | | | | | in AMDGPUOperand. Summary: sext() modifier is supported in SDWA instructions only for integer operands. Spec is unclear should integer operands support abs and neg modifiers with sext - for now they are not supported. Renamed InputModsWithNoDefault to FloatInputMods. Added SextInputMods for operands that support sext() modifier. Added AMDGPUOperand::Modifier struct to handle register and immediate modifiers. Code cleaning in AMDGPUOperand class: organize method in groups (render-, predicate-methods...). Reviewers: vpykhtin, artem.tamazov, tstellarAMD Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D20968 llvm-svn: 272384
* test commit: remove trailing whitespaces in README.txtRoger Ferrer Ibanez2016-06-101-8/+8
| | | | llvm-svn: 272380
* Bug fix remove another illegal char from prof symbol nameXinliang David Li2016-06-101-1/+1
| | | | | | | | End-end test with no integrated assembly should be added at some point (not done now because some bots are not properly configured to support -no-integrated-as) llvm-svn: 272376
* [LibFuzzer] Fix some unit test crashes on OSX.Dan Liew2016-06-101-0/+4
| | | | | | | | | | | | | | | | | | | | | This fixes the following unit tests: FuzzerDictionary.ParseOneDictionaryEntry FuzzerDictionary.ParseDictionaryFile The issue appears to be mixing non-ASan-ified code (LibFuzzer) and ASan-ified code (the unittest) as the tests would pass fine if everything was built with ASan enabled. I believe the issue is that different implementations of std::vector<> are being used in LibFuzzer and outside LibFuzzer (in the unittests). For Libcxx (I've not seen the issue manifest for libstdc++) we can disable the ASanified std::vector<> by definining the ``_LIBCPP_HAS_NO_ASAN`` macro. Doing this fixes the tests on OSX. Differential Revision: http://reviews.llvm.org/D21049 llvm-svn: 272374
* [AVX512] Add shuffle comment printing for masked VPERMPD/VPERMQ.Craig Topper2016-06-101-1/+9
| | | | llvm-svn: 272371
* Make PDBFile take a StreamInterface instead of a MemBuffer.Zachary Turner2016-06-102-118/+79
| | | | | | | | | | | | | | | This is the next step towards being able to write PDBs. MemoryBuffer is immutable, and StreamInterface is our replacement which can be any combination of read-only, read-write, or write-only depending on the particular implementation. The one place where we were creating a PDBFile (in RawSession) is updated to subclass ByteStream with a simple adapter that holds a MemoryBuffer, and initializes the superclass with the buffer's array, so that all the functionality of ByteStream works transparently. llvm-svn: 272370
* Add support for writing through StreamInterface.Zachary Turner2016-06-109-17/+302
| | | | | | | | | | | This adds method and tests for writing to a PDB stream. With this, even a PDB stream which is discontiguous can be treated as a sequential stream of bytes for the purposes of writing. Reviewed By: ruiu Differential Revision: http://reviews.llvm.org/D21157 llvm-svn: 272369
* [AVX512] Fix shuffle comment printing to handle the masked versions of some ↵Craig Topper2016-06-101-30/+46
| | | | | | shuffles. Previously we were printing the mask operands as the register names. llvm-svn: 272367
* AMDGPU: Fix trailing whitespaceMatt Arsenault2016-06-1010-40/+40
| | | | llvm-svn: 272364
* [esan|cfrag] Add the struct field offset array in StructInfoQin Zhao2016-06-101-11/+29
| | | | | | | | | | | | | | | Summary: Adds the struct field offset array in struct StructInfo. Updates test struct_field_count_basic.ll. Reviewers: aizatsky Subscribers: llvm-commits, bruening, eugenis, kcc, zhaoqin, vitalybuka Differential Revision: http://reviews.llvm.org/D21192 llvm-svn: 272362
* Add null checks before using a pointer.Richard Trieu2016-06-101-0/+4
| | | | llvm-svn: 272359
* [esan|cfrag] Disable load/store instrumentation for cfragQin Zhao2016-06-101-3/+7
| | | | | | | | | | | | | | | | | | | | Summary: Adds ClInstrumentFastpath option to control fastpath instrumentation. Avoids the load/store instrumentation for the cache fragmentation tool. Renames cache_frag_basic.ll to working_set_slow.ll for slowpath instrumentation test. Adds the __esan_init check in struct_field_count_basic.ll. Reviewers: aizatsky Subscribers: llvm-commits, bruening, eugenis, kcc, zhaoqin, vitalybuka Differential Revision: http://reviews.llvm.org/D21079 llvm-svn: 272355
* AMDGPU: v_cndmask_b32 does not def vccMatt Arsenault2016-06-101-2/+2
| | | | | | Fixes verifier errors after SIShrinkInstructions. llvm-svn: 272351
* AMDGPU/SI: Make sure to emit TargetConstant nodes when matching ds_*permuteTom Stellard2016-06-101-2/+2
| | | | | | | | | | | | | | | Summary: This fixes a bug with ds_*permute instructions where if it was passed a constant address, then the offset operand would get assigned a register operand instead of an immediate. Reviewers: scchan, arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19994 llvm-svn: 272349
* AMDGPU/SI: Use common topological sort algorithm in SIScheduleDAGMITom Stellard2016-06-091-64/+3
| | | | | | | | | | Reviewers: arsenm, axeldavy Subscribers: MatzeB, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19823 llvm-svn: 272346
* AMDGPU: Fix flat atomicsMatt Arsenault2016-06-094-41/+90
| | | | | | | | The flat atomics could already be selected, but only when using flat instructions for global memory. Add patterns for flat addresses. llvm-svn: 272345
* AMDGPU: Fix i64 global cmpxchgMatt Arsenault2016-06-094-40/+82
| | | | | | | | | | This was using extract_subreg sub0 to extract the low register of the result instead of sub0_sub1, producing an invalid copy. There doesn't seem to be a way to use the compound subreg indices in tablegen since those are generated, so manually select it. llvm-svn: 272344
* Make sure that not interesting allocas are not instrumented.Vitaly Buka2016-06-091-4/+13
| | | | | | | | | | | | | | | | | | | Summary: We failed to unpoison uninteresting allocas on return as unpoisoning is part of main instrumentation which skips such allocas. Added check -asan-instrument-allocas for dynamic allocas. If instrumentation of dynamic allocas is disabled it will not will not be unpoisoned. PR27453 Reviewers: kcc, eugenis Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D21207 llvm-svn: 272341
* CodeGen: Allow verifier to run after MachineBlockPlacementMatt Arsenault2016-06-091-1/+1
| | | | | | No tests break with this enabled. llvm-svn: 272340
* Add aliases for mfvrsave/mtvrsave.Eric Christopher2016-06-091-0/+4
| | | | | | | Update a test as we're now going to emit it for easier reading of generated assembly as well. llvm-svn: 272339
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