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* AMDGPU: Run verifer after insert waits passMatt Arsenault2016-06-091-1/+1
| | | | llvm-svn: 272338
* AMDGPU: Remove incorrect assertionMatt Arsenault2016-06-091-4/+0
| | | | | | | I'm still not sure under what circumstances the offset here is non-0, but private memory is not limited to 27-bits. llvm-svn: 272337
* AMDGPU: Properly initialize SIShrinkInstructionsMatt Arsenault2016-06-093-8/+6
| | | | llvm-svn: 272336
* [CFLAA] Handle global/arg attrs more sanely.George Burgess IV2016-06-092-20/+40
| | | | | | | | | | | | | | | | Prior to this patch, we used argument/global stratified attributes in order to note that a value could have come from either dereferencing a global/arg, or from the assignment from a global/arg. Now, AttrUnknown is placed on sets when we see a dereference, instead of the global/arg attributes. This allows us to be more aggressive in the future when we see global/arg attributes without AttrUnknown. Patch by Jia Chen. Differential Revision: http://reviews.llvm.org/D21110 llvm-svn: 272335
* Unpoison stack memory in use-after-return + use-after-scope modeVitaly Buka2016-06-091-12/+21
| | | | | | | | | | | | | | | Summary: We still want to unpoison full stack even in use-after-return as it can be disabled at runtime. PR27453 Reviewers: eugenis, kcc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D21202 llvm-svn: 272334
* Reapply 272328 and 272329 as a single patch.Alina Sbirlea2016-06-091-10/+3
| | | | | | | | | | | | | | | | | | | | [cpu-detection] [amdfam10] Return barcelona, and amdfam10 for all other subtypes. Address Bug 28067. Along with the refactoring of Host.cpp, getHostCPUName() was modified to return more precise types for CPUs in amdfam10. However, callers of getHostCPUName() do string matching on type, so this cannot be modified. Currently there is support in the x86 backend for barcelona. For all other subtypes the assumed return value is amdfam10. Fix: getHostCPUName() returns barcelona subtype and amdfam10 for all others. This can be extended further when support for the other subtypes is added. Differential revision: http://reviews.llvm.org/D21193 llvm-svn: 272333
* Revert 272328 and 272329 to recommit as a single patch.Alina Sbirlea2016-06-091-3/+10
| | | | llvm-svn: 272332
* Keep barcelona subtype for amdfam10Alina Sbirlea2016-06-091-1/+3
| | | | llvm-svn: 272329
* [cpu-detection] Return amdfam10 for all subtypes. Address Bug 28067.Alina Sbirlea2016-06-091-9/+0
| | | | | | | | | | | | Summary: Remove architecture subtype from the string returned by getHostCPUName(). String matching done on type. Reviewers: llvm-commits, echristo Subscribers: mehdi_amini Differential Revision: http://reviews.llvm.org/D21193 llvm-svn: 272328
* Use ProfileSummaryInfo in inline cost analysis.Easwaran Raman2016-06-094-40/+36
| | | | | | | | Instead of directly using MaxFunctionCount and function entry count to determine callee hotness, use the isHotFunction/isColdFunction methods provided by ProfileSummaryInfo. Differential revision: http://reviews.llvm.org/D21045 llvm-svn: 272321
* [X86][AVX512] Added avx512 VPSLLDQ/VPSRLDQ instruction commentsSimon Pilgrim2016-06-091-0/+12
| | | | llvm-svn: 272319
* [LiveRangeEdit] Fix a crash in eliminateDeadDef.Quentin Colombet2016-06-091-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we delete a live-range, we check if that live-range is the origin of others to keep it around for rematerialization. For that we check that the instruction we are about to remove is the same as the definition of the VNI of the original live-range. If this is the case, we just shrink the live-range to an empty one. Now, when we try to delete one of the children of such live-range (product of splitting), we do the same check. However, now the original live-range is empty and there is no way we can access the VNI to check its definition, and we crash. When we cannot get the VNI for the original live-range, that means we are not in the presence of the original definition. Thus, this check does not need to happen in that case and the crash is sloved! This bug was introduced in r266162 | wmi | 2016-04-12 20:08:27. It affects every target that uses the greedy register allocator. To happen, we need to delete both a the original instruction and its split products, in that order. This is likely to happen when rematerialization comes into play. Trying to produce a more robust test case. Will follow in a coming commit. This fixes llvm.org/PR27983. rdar://problem/26651519 llvm-svn: 272314
* [X86][AVX512] Dropped avx512 VPSLLDQ/VPSRLDQ intrinsicsSimon Pilgrim2016-06-092-12/+14
| | | | | | Auto-upgrade to generic shuffles like sse/avx2 implementations now that we can lower to VPSLLDQ/VPSRLDQ llvm-svn: 272308
* [X86][AVX512] Fixed issue with v16i32 shuffles lowering to VPALIGNRSimon Pilgrim2016-06-091-1/+1
| | | | llvm-svn: 272307
* BitcodeReader: Use std:::piecewise_construct when upgrading type refsDuncan P. N. Exon Smith2016-06-091-3/+3
| | | | | | | | | | | | | | r267296 used std::piecewise_construct without using std::forward_as_tuple, and r267298 hacked it out (using an emplace_back followed by a couple of reset() calls) because of a problem on a bot. I'm finally circling back to call forward_as_tuple as I should have to begin with (thanks to David Blaikie for pointing out the missing piece). Note that this code uses emplace_back() instead of push_back(make_pair()) because the move constructor for TrackingMDRef is expensive (cheaper than a copy, but still expensive). llvm-svn: 272306
* [X86][AVX512] Added support for lowering 512-bit vector shuffles to bit/byte ↵Simon Pilgrim2016-06-091-19/+41
| | | | | | | | shifts 512-bit VPSLLDQ/VPSRLDQ can only be used for avx512bw targets so lowerVectorShuffleAsShift had to be adjusted to include the subtarget llvm-svn: 272300
* [NVPTX] Add intrinsics for shfl instructions.Justin Lebar2016-06-091-1/+42
| | | | | | | | | | | | | | | Summary: Currently clang emits these instructions via inline (volatile) asm in the CUDA headers. Switching to intrinsics will let the optimizer reason across calls to these intrinsics. Reviewers: tra Subscribers: llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D21160 llvm-svn: 272298
* [PM] Port LCSSA to the new PM.Easwaran Raman2016-06-098-23/+47
| | | | | | Differential Revision: http://reviews.llvm.org/D21090 llvm-svn: 272294
* AMDGPU/SI: Fix 32-bit fdiv loweringWei Ding2016-06-091-16/+53
| | | | | | | | | We were using the fast fdiv lowering for all division, implementation of IEEE754 fdiv is added. http://reviews.llvm.org/D20557 llvm-svn: 272292
* [LV] Use vector phis for some secondary induction variablesMichael Kuperstein2016-06-091-4/+6
| | | | | | | | | | | | | | Previously, we materialized secondary vector IVs from the primary scalar IV, by offseting the primary to match the correct start value, and then broadcasting it - inside the loop body. Instead, we can use a real vector IV, like we do for the primary. This enables using vector IVs for secondary integer IVs whose type matches the type of the primary. Differential Revision: http://reviews.llvm.org/D20932 llvm-svn: 272283
* SelectionDAG: Implement expansion of {S,U}MIN/MAX in integer legalizationJan Vesely2016-06-092-0/+55
| | | | | | | | | Fixes {u,}long_{min,max,clamp} opencl piglit regressions on EG. Reviewers: arsenm Differential Revision: http://reviews.llvm.org/D17898 llvm-svn: 272272
* Reapply "[MBP] Reduce code size by running tail merging in MBP.""Haicheng Wu2016-06-094-34/+121
| | | | | | | | | | | | | | | | This reapplies commit r271930, r271915, r271923. They hit a bug in Thumb which is fixed in r272258 now. The original message: The code layout that TailMerging (inside BranchFolding) works on is not the final layout optimized based on the branch probability. Generally, after BlockPlacement, many new merging opportunities emerge. This patch calls Tail Merging after MBP and calls MBP again if Tail Merging merges anything. llvm-svn: 272267
* [SystemZ] Enable long displacement constraints for inline ASM operandsUlrich Weigand2016-06-092-9/+21
| | | | | | | | | | | | | | | | | | This enables use of the 'S' constraint for inline ASM operands on SystemZ, which allows for a memory reference with a signed 20-bit immediate displacement. This patch includes corresponding documentation and test case updates. I've changed the 'T' constraint to match the new behavior for 'S', as 'T' also uses a long displacement (though index constraints are still not implemented). I also changed 'm' to match the behavior for 'S' as this will allow for a wider range of displacements for 'm', though correct me if that's not the right decision. Author: colpell Differential Revision: http://reviews.llvm.org/D21097 llvm-svn: 272266
* [CodeGen] Change getSDagStackGuard to get an internal sym.Davide Italiano2016-06-091-1/+1
| | | | | | | Fixes a crash in the backend during an LTO build of rtld(1) in FreeBSD. llvm-svn: 272262
* [mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructionsHrvoje Varga2016-06-099-13/+241
| | | | | | Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
* [Thumb] A branch is not part of an IT blockJames Molloy2016-06-091-1/+1
| | | | | | | | ReplaceTailWithBranchTo assumed that if an instruction is predicated, it must be part of an IT block. This is not correct for conditional branches. No testcase as this was triggered by the reverted patch r272017 - test coverage will occur when that patch is re-reverted and there is no known way to trigger this in the meantime. llvm-svn: 272258
* [AVX512] Remove masked_move/blendm intrinsic from back-end. Igor Breger2016-06-092-45/+1
| | | | | | | | This is complement patch to D21060. Differential Revision: http://reviews.llvm.org/D21174 llvm-svn: 272257
* [mips][microMIPS] Add CodeGen support for SEL.*, SELEQZ, SELNEZ, SELEQZ.*, ↵Zlatko Buljan2016-06-094-80/+137
| | | | | | | | SELNEZ.* and CMP.condn.fmt instructions Differential Revision: http://reviews.llvm.org/D20862 llvm-svn: 272256
* [AMDGPU] Disassembler: Support for sdwa instructionsSam Kolton2016-06-091-1/+5
| | | | | | | | | | Reviewers: vpykhtin, tstellarAMD Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D21129 llvm-svn: 272255
* [AVX512] Fix shuffle decode printing for several instructions with write ↵Craig Topper2016-06-091-3/+3
| | | | | | masks. There are still more bugs here with UNPCK and PALIGN for sure. But these were the easiest ones to fix. llvm-svn: 272252
* [Thumb] Select a BIC instead of AND if the immediate can be encoded more ↵James Molloy2016-06-091-1/+40
| | | | | | | | | | | | | | | | | | | | | | optimally negated If an immediate is only used in an AND node, it is possible that the immediate can be more optimally materialized when negated. If this is the case, we can negate the immediate and use a BIC instead; int i(int a) { return a & 0xfffffeec; } Used to produce: ldr r1, [CONSTPOOL] ands r0, r1 CONSTPOOL: 0xfffffeec And now produces: movs r1, #255 adds r1, #20 ; Less costly immediate generation bics r0, r1 llvm-svn: 272251
* [X86] Bring consistent naming to the SSE/AVX and AVX512 PALIGNR ↵Craig Topper2016-06-094-39/+35
| | | | | | instructions. Then add shuffle decode printing for the EVEX forms which is made easier by having the naming structure more similar to other instructions. llvm-svn: 272249
* [X86] Fix bad comment in assert. NFCCraig Topper2016-06-091-1/+1
| | | | llvm-svn: 272248
* Revert r272194 No need for it if loop Analysis Manager is usedXinliang David Li2016-06-096-16/+17
| | | | llvm-svn: 272243
* AArch64: support the `.arch` directive in the IASSaleem Abdulrasool2016-06-091-0/+28
| | | | | | | | | | Add support to the AArch64 IAS for the `.arch` directive. This allows the assembly input to use architectural functionality in part of a file. This is used in existing code like BoringSSL. Resolves PR26016! llvm-svn: 272241
* [libFuzzer] add one more OOM test, which we currently don't handle very wellKostya Serebryany2016-06-092-0/+30
| | | | llvm-svn: 272240
* [ThinLTO/gold] Enable summary-based internalizationTeresa Johnson2016-06-091-2/+13
| | | | | | | | | | | | Summary: Enable existing summary-based importing support in the gold-plugin. Reviewers: mehdi_amini Subscribers: llvm-commits, mehdi_amini Differential Revision: http://reviews.llvm.org/D21080 llvm-svn: 272239
* Minor clean up in loopHasNoAbnormalExits; NFCSanjoy Das2016-06-091-8/+7
| | | | llvm-svn: 272238
* Be wary of abnormal exits from loop when exploiting UBSanjoy Das2016-06-091-1/+2
| | | | | | | | | | | | | | We can safely rely on a NoWrap add recurrence causing UB down the road only if we know the loop does not have a exit expressed in a way that is opaque to ScalarEvolution (e.g. by a function call that conditionally calls exit(0)). I believe with this change PR28012 is fixed. Note: I had to change some llvm-lit tests in LoopReroll, since it looks like they were depending on this incorrect behavior. llvm-svn: 272237
* Factor out a loopHasNoAbnormalExits; NFCSanjoy Das2016-06-091-9/+8
| | | | llvm-svn: 272236
* Search for llvm-symbolizer binary in the same directory as argv[0], beforeRichard Smith2016-06-093-15/+37
| | | | | | | looking for it along $PATH. This allows installs of LLVM tools outside of $PATH to find the symbolizer and produce pretty backtraces if they crash. llvm-svn: 272232
* [codeview] Skip DIGlobalVariables with no variableReid Kleckner2016-06-091-2/+3
| | | | | | They have probably been discarded during optimization. llvm-svn: 272231
* [pdbdump] Verify part of TPI hash streams.Rui Ueyama2016-06-091-0/+28
| | | | | | | | | | | | | | | | | TPI hash table contains a parallel array for the type records. For each type record R, a hash value is calculated by `H(R) % NumBuckets` where H is a hash function, and the result is stored to a bucket element. H is TPI1::hashPrec function in microsoft-pdb repository. Our hash function does not support all type record types yet. Currently it supports only records for line number. I'll extend it in a follow up patch. The aim of verify the hash table is not only detect corrupted files. It ensures that our understanding of how the hash values are calculated is correct. llvm-svn: 272229
* [cpu-detection] Add missing break statements in outer switchesAlina Sbirlea2016-06-091-6/+9
| | | | | | | | | | | | Summary: Break on all switch cases for outer and inner switches. No functionality changed. Reviewers: llvm-commits, sanjoy Differential Revision: http://reviews.llvm.org/D21158 llvm-svn: 272228
* [MIR] Check that generic virtual registers get a size.Quentin Colombet2016-06-083-4/+11
| | | | | | | | Without that check it was possible to write test cases where the size was not specified and we ended up with weird asserts down the road, because the default value (1) would not make sense. llvm-svn: 272226
* Function names should start with lowercase letters.Rui Ueyama2016-06-082-3/+3
| | | | llvm-svn: 272225
* [LoopSimplify] Preserve LCSSA when merging exit blocks.Michael Zolotukhin2016-06-081-2/+21
| | | | | | | | | | | | | | Summary: This fixes PR26682. Also add LCSSA as a preserved pass to LoopSimplify, that looks correct to me and allows to write a test for the issue. Reviewers: chandlerc, bogner, sanjoy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D21112 llvm-svn: 272224
* [PDB] Move PDB functions to a separate file.Rui Ueyama2016-06-083-59/+79
| | | | | | | | We are going to use the hash functions from TPI streams. Differential Revision: http://reviews.llvm.org/D21142 llvm-svn: 272223
* [LoopUnroll] Check that DT is available before trying to verify it.Michael Zolotukhin2016-06-081-1/+1
| | | | llvm-svn: 272221
* [RegBankSelect] Print out the actual mapping of the operands.Quentin Colombet2016-06-081-0/+1
| | | | | | This improves the debuggability of the pass. llvm-svn: 272210
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