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* Turn on pubnames by default on linux.Eric Christopher2013-08-192-10/+22
| | | | | | | | | Until gdb supports the new accelerator tables we should add the pubnames section so that gdb_index can be generated from gold at link time. On darwin we already emit the accelerator tables and so don't need to worry about pubnames. llvm-svn: 188708
* Improve the widening of integral binary vector operationsPaul Redmond2013-08-192-10/+24
| | | | | | | | | | | | | | - split WidenVecRes_Binary into WidenVecRes_Binary and WidenVecRes_BinaryCanTrap - WidenVecRes_BinaryCanTrap preserves the original behaviour for operations that can trap - WidenVecRes_Binary simply widens the operation and improves codegen for 3-element vectors by allowing widening and promotion on x86 (matches the behaviour of unary and ternary operation widening) - use WidenVecRes_Binary for operations on integers. Reviewed by: nrotem llvm-svn: 188699
* Adding comments to document RuntimeDyld relocation handlingAndrew Kaylor2013-08-193-1/+44
| | | | llvm-svn: 188697
* [mips] Fix instruction definitions that were incorrectly marked as ↵Akira Hatanaka2013-08-191-6/+9
| | | | | | code-gen-only. llvm-svn: 188690
* Introduce SpecialCaseList::isIn overload for GlobalAliases.Peter Collingbourne2013-08-191-2/+14
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D1437 llvm-svn: 188688
* Thumb2 add immediate alias for SPMihai Popa2013-08-191-1/+2
| | | | | | | | The Thumb2 add immediate is in fact defined for SP. The manual is misleading as it points to a different section for add immediate with SP, however the encoding is the same as for add immediate with register only with the SP operand hard coded. As such add immediate with SP and add immediate with register can safely be treated as the same instruction. All the patch does is adjust a register constraint on an instruction alias. llvm-svn: 188676
* AVX-512: added arithmetic and logical operations.Elena Demikhovsky2013-08-193-27/+249
| | | | | | | ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
* [SystemZ] Add negative integer absolute (load negative)Richard Sandiford2013-08-193-6/+12
| | | | | | | | For now this matches the equivalent of (neg (abs ...)), which did hit a few times in projects/test-suite. We should probably also match cases where absolute-like selects are used with reversed arguments. llvm-svn: 188671
* [SystemZ] Add integer absolute (load positive)Richard Sandiford2013-08-192-1/+19
| | | | llvm-svn: 188670
* [SystemZ] Add support for sibling callsRichard Sandiford2013-08-196-21/+89
| | | | | | | | | | | | | | | | | | This first cut is pretty conservative. The final argument register (R6) is call-saved, so we would need to make sure that the R6 argument to a sibling call is the same as the R6 argument to the calling function, which seems worth keeping as a separate patch. Saying that integer truncations are free means that we no longer use the extending instructions LGF and LLGF for spills in int-conv-09.ll and int-conv-10.ll. Instead we treat the registers as 64 bits wide and truncate them to 32-bits where necessary. I think it's unlikely we'd use LGF and LLGF for spills in other situations for the same reason, so I'm removing the tests rather than replacing them. The associated code is generic and applies to many more instructions than just LGF and LLGF, so there is no corresponding code removal. llvm-svn: 188669
* Adds missing TLI check for library simplification ofMichael Kuperstein2013-08-191-3/+6
| | | | | | | * pow(x, 0.5) -> fabs(sqrt(x)) * pow(2.0, x) -> exp2(x) llvm-svn: 188656
* Add ExpandFloatOp_FCOPYSIGN to handle ppcf128-related expansionsHal Finkel2013-08-192-0/+13
| | | | | | | | | | We had previously been asserting when faced with a FCOPYSIGN f64, ppcf128 node because there was no way to expand the FCOPYSIGN node. Because ppcf128 is the sum of two doubles, and the first double must have the larger magnitude, we can take the sign from the first double. As a result, in addition to fixing the crash, this is also an optimization. llvm-svn: 188655
* Add the PPC fcpsgn instructionHal Finkel2013-08-195-7/+45
| | | | | | | | | Modern PPC cores support a floating-point copysign instruction, and we can use this to lower the FCOPYSIGN node (which is created from calls to the libm copysign function). A couple of extra patterns are necessary because the operand types of FCOPYSIGN need not agree. llvm-svn: 188653
* llvm-dwarfdump: Do not include address offsets for attributes, only for tagsDavid Blaikie2013-08-191-1/+1
| | | | | | | | | This reduces the noise in diffs making it more likely that, at least for LLVM revision-over-revision, diffs will actually yield usable results. This is consistent with objdump's DWARF dumping behavior. llvm-svn: 188650
* DebugInfo: don't emit zero-length names for parametersDavid Blaikie2013-08-191-1/+2
| | | | | | | | We check this in many/all other cases, just missed this one it seems. Perhaps it'd be worth unifying this so we never emit zero-length DW_AT_names. llvm-svn: 188649
* Remove SpecialCaseList::findCategory.Peter Collingbourne2013-08-191-35/+0
| | | | | | It turned out that I didn't need this for DFSan. llvm-svn: 188646
* ARM: make sure we keep inline asm operands tied.Tim Northover2013-08-181-1/+4
| | | | | | | | When patching inlineasm nodes to use GPRPair for 64-bit values, we were dropping the information that two operands were tied, which effectively broke the live-interval of vregs affected. llvm-svn: 188643
* AVX-512: Added VMOVD, VMOVQ, VMOVSS, VMOVSD instructions.Elena Demikhovsky2013-08-186-44/+335
| | | | llvm-svn: 188637
* Make more of the lowering helpers static. Also use MVT instead of EVT in a ↵Craig Topper2013-08-182-24/+17
| | | | | | couple places. llvm-svn: 188629
* Remove unused stdio.h includesDmitri Gribenko2013-08-186-8/+1
| | | | llvm-svn: 188626
* Go through the really awkward dance required to delete the memoryChandler Carruth2013-08-181-2/+12
| | | | | | | | allocated by setupterm. Without this, some folks are seeing leaked memory whenever this routine is called more than once. Thanks to Craig Topper for the report. llvm-svn: 188615
* Fix SCEVExpander creating distinct duplicate PHI entriesHal Finkel2013-08-181-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes SCEVExpander so that it does not create multiple distinct induction variables for duplicate PHI entries. Specifically, given some code like this: do.body6: ; preds = %do.body6, %do.body6, %if.then5 %end.0 = phi i8* [ undef, %if.then5 ], [ %incdec.ptr, %do.body6 ], [ %incdec.ptr, %do.body6 ] ... Note that it is legal to have multiple entries for a basic block so long as the associated value is the same. So the above input is okay, but expanding an AddRec in this loop could produce code like this: do.body6: ; preds = %do.body6, %do.body6, %if.then5 %indvar = phi i64 [ %indvar.next, %do.body6 ], [ %indvar.next1, %do.body6 ], [ 0, %if.then5 ] %end.0 = phi i8* [ undef, %if.then5 ], [ %incdec.ptr, %do.body6 ], [ %incdec.ptr, %do.body6 ] ... %indvar.next = add i64 %indvar, 1 %indvar.next1 = add i64 %indvar, 1 And this is not legal because there are two PHI entries for %do.body6 each with a distinct value. Unfortunately, I don't have an in-tree test case. llvm-svn: 188614
* PR 16899: Do not modify the basic block using the iterator, but keep theJoerg Sonnenberger2013-08-171-4/+6
| | | | | | | | next value. This avoids crashes due to invalidation. Patch by Joey Gouly. llvm-svn: 188605
* R600: Fix possible use of an uninitialized variableTom Stellard2013-08-171-0/+1
| | | | | | Spotted by Nick Lewycky! llvm-svn: 188599
* R600: Expand vector FRINT opsTom Stellard2013-08-161-0/+1
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188598
* R600: Expand vector FFLOOR opsTom Stellard2013-08-161-0/+1
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188597
* R600: Expand vector float operations for both SI and R600Tom Stellard2013-08-162-13/+18
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188596
* ARM: Properly constrain comparison fastisel register classes.Jim Grosbach2013-08-161-5/+12
| | | | | | | | Ongoing 'make the verifier happy' improvements to ARM fast-isel. rdar://12594152 llvm-svn: 188595
* ARM: Fast-isel register class constrain for extends.Jim Grosbach2013-08-161-0/+1
| | | | | | | | | | Properly constrain the operand register class for instructions used in [sz]ext expansion. Update more tests to use the verifier now that we're getting the register classes correct. rdar://12594152 llvm-svn: 188594
* ARM: Fix more fast-isel verifier failures.Jim Grosbach2013-08-162-0/+47
| | | | | | | | | | | | | Teach the generic instruction selection helper functions to constrain the register classes of their input operands. For non-physical register references, the generic code needs to be careful not to mess that up when replacing references to result registers. As the comment indicates for MachineRegisterInfo::replaceRegWith(), it's important to call constrainRegClass() first. rdar://12594152 llvm-svn: 188593
* ARM: Clean up fast-isel machine verifier errors.Jim Grosbach2013-08-161-1/+1
| | | | | | | | | | | | | Lots of machine verifier errors result from using a plain GPR regclass for incoming argument copies. A more restrictive rGPR class is more appropriate since it more accurately represents what's happening, plus it lines up better with isel later on so the verifier is happier. Reduces the number of ARM fast-isel tests not running with the verifier enabled by over half. rdar://12594152 llvm-svn: 188592
* Fix a subtle difference between running clang vs llc for mips16.Reed Kotler2013-08-161-0/+3
| | | | | | | | | | | | | | | | This regards how mips16 is viewed. It's not really a target type but there has always been a target for it in the td files. It's more properly -mcpu=mips32 -mattr=+mips16 . This is how clang treats it but we have always had the -mcpu=mips16 which I probably should delete now but it will require updating all the .ll test cases for mips16. In this case it changed how we decide if we have a count bits instruction and whether instruction lowering should then expand ctlz. Now that we have dual mode compilation, -mattr=+mips16 really just indicates the inital processor mode that we are compiling for. (It is also possible to have -mcpu=64 -mattr=+mips16 but as far as I know, nobody has even built such a processor, though there is an architecture manual for this). llvm-svn: 188586
* Actually, use GNU inline asm for cpuid with clangReid Kleckner2013-08-161-10/+10
| | | | | | | Clang doesn't support the MSVC __cpuid intrinsic yet, and fixing that is blocked on some fairly complicated issues. llvm-svn: 188584
* DebugInfo: Allow the addition of other (such as static data) members to a ↵David Blaikie2013-08-163-9/+7
| | | | | | | | record type after construction Plus a type cleanup & minor fix to enumerate members of declarations. llvm-svn: 188577
* [PowerPC] Preparatory refactoring for making prologue and epilogueBill Schmidt2013-08-161-85/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | safe on PPC32 SVR4 ABI [Patch and following text by Mark Minich; committing on his behalf.] There are FIXME's in PowerPC/PPCFrameLowering.cpp, method PPCFrameLowering::emitPrologue() related to "negative offsets of R1" on PPC32 SVR4. They're true, but the real issue is that on PPC32 SVR4 (and any ABI without a Red Zone), no spills may be made until after the stackframe is claimed, which also includes the LR spill which is at a positive offset. The same problem exists in emitEpilogue(), though there's no FIXME for it. I intend to fix this issue, making LLVM-compiled code finally safe for use on SVR4/EABI/e500 32-bit platforms (including in particular, OS-free embedded systems & kernel code, where interrupts may share the same stack as user code). In preparation for making these changes, to make the diffs for the functional changes less cluttered, I am providing the non-functional refactorings in two stages: Stage 1 does some minor fluffy refactorings to pull multiple method calls up into a single bool, creating named bools for repeated uses of obscure logic, moving some code up earlier because either stage 2 or my final version will require it earlier, and rewording/adding some comments. My stage 1 changes can be characterized as primarily fluffy cleanup, the purpose of which may be unclear until the stage 2 or final changes are made. My stage 2 refactorings combine the separate PPC32 & PPC64 logic, which is currently performed by largely duplicate code, into a single flow, with the differences handled by a group of constants initialized early in the methods. This submission is for my stage 1 changes. There should be no functional changes whatsoever; this is a pure refactoring. llvm-svn: 188573
* Fixed RuntimeDyldELF absolute relocations.Richard Mitton2013-08-161-1/+11
| | | | | | | | | If an ELF relocation is pointed at an absolute address, it will have a symbol ID of zero. RuntimeDyldELF::processRelocationRef was not previously handling this case, and was instead trying to handle it as a section-relative fixup. I think this is the right fix here, but my elf-fu is poor on some of the more exotic platforms, so I'd appreciate it if anyone with greater knowledge could verify this. llvm-svn: 188572
* Switching to using a helper function instead of manually converting the ↵Aaron Ballman2013-08-161-24/+1
| | | | | | string to UTF-8. llvm-svn: 188566
* Removing unused functionality.Aaron Ballman2013-08-162-18/+0
| | | | llvm-svn: 188565
* InstCombine: Use isAllOnesValue() instead of explicit -1.Jim Grosbach2013-08-161-1/+1
| | | | llvm-svn: 188563
* R600/SI: Add pattern for xor of i1Michel Danzer2013-08-161-1/+3
| | | | | | | Fixes two recent piglit regressions with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 188559
* R600/SI: Fix broken encoding of DS_WRITE_B32Michel Danzer2013-08-165-9/+23
| | | | | | | | | | | | | | The logic in SIInsertWaits::getHwCounts() only really made sense for SMRD instructions, and trying to shoehorn it into handling DS_WRITE_B32 caused it to corrupt the encoding of that by clobbering the first operand with the second one. Undo that damage and only apply the SMRD logic to that. Fixes some derivates related piglit regressions with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 188558
* Reverted test commit (r188556)Daniel Sanders2013-08-161-1/+0
| | | | llvm-svn: 188557
* Test commit. Just a blank lineDaniel Sanders2013-08-161-0/+1
| | | | llvm-svn: 188556
* R600: Allocate memoperand in the MachienFunction so it doesn't leak.Benjamin Kramer2013-08-161-3/+4
| | | | llvm-svn: 188555
* Updating function comments; no functional changes intended.Aaron Ballman2013-08-161-5/+12
| | | | llvm-svn: 188554
* When initializing the PIC global base register on ARM/ELF add pc to fix the ↵Benjamin Kramer2013-08-161-0/+4
| | | | | | | | | | address. This unbreaks PIC with fast isel on ELF targets (PR16717). The output matches what GCC and SDag do for PIC but may not cover all of the many flavors of PIC that exist. llvm-svn: 188551
* Add support for Thumb2 literal loads with negative zero offsetMihai Popa2013-08-162-4/+4
| | | | | | | | Thumb2 literal loads use an offset encoding which allows for negative zero. This fixes parsing and encoding so that #-0 is correctly processed. The parser represents #-0 as INT32_MIN. llvm-svn: 188549
* Fix Thumb2 aliasing complementary instructions taking modified immediatesMihai Popa2013-08-162-5/+6
| | | | | | | | | | | | | | | | | | | | | There are many Thumb instructions which take 12-bit immediates encoded in a special 8-byte value + 4-byte rotator form. Not all numbers are represented, and it's legal to transform an assembly instruction to be able to encode the immediate. For example: AND and BIC are complementary instructions; one can switch the AND to a BIC as long as the immediate is complemented. The intent is to switch one instruction into its complementary one when the immediate cannot be encoded in the form requested in the original assembly and when the complementary immediate is encodable. The patch addresses two issues: 1. definition of t2SOImmNot immediate - it has to check that the orignal value is not encoded naturally 2. t2AND and t2BIC instruction aliases which should use the Thumb2 SOImm operand rather than the ARM one. llvm-svn: 188548
* [SystemZ] Use SRST to implement strlen and strnlenRichard Sandiford2013-08-168-0/+122
| | | | | | It would also make sense to use it for memchr; I'm working on that now. llvm-svn: 188547
* [SystemZ] Use MVST to implement strcpy and stpcpyRichard Sandiford2013-08-168-0/+68
| | | | llvm-svn: 188546
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