| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 128451
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llvm-svn: 128450
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The instruction to be rematerialized may not be the one defining the register
that is being spilled. The traceSiblingValue() function sees through sibling
copies to find the remat candidate.
llvm-svn: 128449
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isel lowering to fold the zero-extend's and take advantage of no-stall
back to back vmul + vmla:
vmull q0, d4, d6
vmlal q0, d5, d6
is faster than
vaddl q0, d4, d5
vmovl q1, d6
vmul q0, q0, q1
This allows us to vmull + vmlal for:
f = vmull_u8( vget_high_u8(s), c);
f = vmlal_u8(f, vget_low_u8(s), c);
rdar://9197392
llvm-svn: 128444
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llvm-svn: 128441
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becomes reachable when before it wasn't). Check to make sure that it's not null
before trying to use it.
llvm-svn: 128434
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integrated-as.
llvm-svn: 128431
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on Darwin.
llvm-svn: 128430
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llvm-svn: 128426
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some test cases.
Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly.
llvm-svn: 128417
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otool(1), this time with the needed fix for case sensitive file systems :) .
This is a work in progress as the interface for producing symbolic operands is
not done. But a hacked prototype using information from the object file's
relocation entiries and replacing immediate operands with MCExpr's has been
shown to work with no changes to the instrucion printer. These APIs will be
moved into a dynamic library at some point.
llvm-svn: 128415
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llvm-svn: 128413
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llvm-svn: 128406
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llvm-svn: 128405
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output for those cases much clearer since without this it only showed that the original instruction was removed, not what it was replaced with.
llvm-svn: 128399
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llvm-svn: 128398
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The reassignment phase was able to move interference with a higher spill weight,
but it didn't happen very often and it was fairly expensive.
The existing interference eviction picks up the slack.
llvm-svn: 128397
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the subclass optional data.
llvm-svn: 128388
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llvm-svn: 128380
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identical to the smul.with.overflow() code.
llvm-svn: 128379
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removes one use of X which helps it pass the many hasOneUse() checks.
In my analysis, this turns up very often where X = A >>exact B and that can't be
simplified unless X has one use (except by increasing the lifetime of A which is
generally a performance loss).
llvm-svn: 128373
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llvm-svn: 128370
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The main register class may have been inflated by live range splitting, so that
register class is not necessarily valid for the snippet instructions.
Use the original register class for the stack slot interval.
llvm-svn: 128351
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It couldn't be used outside of the file because SDISelAsmOperandInfo
is local to SelectionDAGBuilder.cpp. Making it a static function avoids
a weird linkage dance.
llvm-svn: 128342
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llvm-svn: 128338
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llvm-svn: 128333
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There are two ways that a later store can comletely overlap a previous store:
1. They both start at the same offset, but the earlier store's size is <= the
later's size, or
2. The earlier store's offset is > the later's offset, but it's offset + size
doesn't extend past the later's offset + size.
llvm-svn: 128332
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llvm-svn: 128331
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Correctly terminate the range of register DBG_VALUEs when the register is
clobbered or when the basic block ends.
The code is now ready to deal with variables that are sometimes in a register
and sometimes on the stack. We just need to teach emitDebugLoc to say 'stack
slot'.
llvm-svn: 128327
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llvm-svn: 128322
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masks to match inversely for the code as is to work. For the example given
we actually want:
bfi r0, r2, #1, #1
not #0, however, given the way the pattern is written it's not possible
at the moment.
Fixes rdar://9177502
llvm-svn: 128320
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completely overlaps a previous store, thus mistakenly deleting that store. Check
for this condition.
llvm-svn: 128319
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llvm-svn: 128309
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This is a work in progress as the interface for producing symbolic operands is
not done. But a hacked prototype using information from the object file's
relocation entiries and replacing immediate operands with MCExpr's has been
shown to work with no changes to the instrucion printer. These APIs will be
moved into a dynamic library at some point.
llvm-svn: 128308
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GPRRegClassID.
Also add some test cases.
rdar://problem/9189829
llvm-svn: 128304
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RegClass. Add two test cases.
rdar://problem/9182892
llvm-svn: 128299
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recent change to
t2LDREX/t2STREX instructions. Add two test cases.
llvm-svn: 128293
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llvm-svn: 128289
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llvm-svn: 128288
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llvm-svn: 128286
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Modify the disassembler to handle that.
rdar://problem/9184053
llvm-svn: 128285
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DBG_VALUEs.
The .dot directives don't need labels, that is a leftover from when we created
line number info manually.
Instructions following a DBG_VALUE can share its label since the DBG_VALUE
doesn't produce any code.
llvm-svn: 128284
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rdar://problem/9186136
llvm-svn: 128283
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Yet another case of unchecked NULL node (for physreg copy).
May fix PR9509.
llvm-svn: 128266
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compliance.
llvm-svn: 128257
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printing a single character.
llvm-svn: 128256
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Add an assertion to linear scan to prevent it from allocating registers outside
the register class.
<rdar://problem/9183021>
llvm-svn: 128254
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register classes were changed),
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.
llvm-svn: 128252
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llvm-svn: 128244
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llvm-svn: 128243
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