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* Fix bug found by valgrind.Jakob Stoklund Olesen2011-03-311-1/+1
| | | | llvm-svn: 128634
* Add XCore intrinsics for initializing / starting / synchronizing threads.Richard Osborne2011-03-311-6/+39
| | | | llvm-svn: 128633
* Reapply r128585 without generating a lib depedency cycle. An updated log:Bruno Cardoso Lopes2011-03-319-87/+322
| | | | | | | | | | | | | - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible. - Move all instructions which use am2offset without a pattern to use addrmode2. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128632
* lib/CodeGen/LiveIntervalAnalysis.cpp: [PR9590] Don't use ↵NAKAMURA Takumi2011-03-311-1/+3
| | | | | | | | | | std::pow(float,float) here. We don't expect the real "powf()" on some hosts (and powf() would be available on other hosts). For consistency, std::pow(double,double) may be called instead. Or, precision issue might attack us, to see unstable regalloc and stack coloring. llvm-svn: 128629
* InstCombine: Fix transform to use the swapped predicate.Benjamin Kramer2011-03-311-2/+2
| | | | | | Thanks Frits! llvm-svn: 128628
* InstCombine: fold fcmp (fneg x), (fneg y) -> fcmp x, yBenjamin Kramer2011-03-311-0/+5
| | | | llvm-svn: 128627
* InstCombine: fold fcmp pred (fneg x), C -> fcmp swap(pred) x, -CBenjamin Kramer2011-03-311-0/+8
| | | | llvm-svn: 128626
* InstCombine: Shrink "fcmp (fpext x), C" to "fcmp x, C" if C can be ↵Benjamin Kramer2011-03-311-0/+34
| | | | | | | | losslessly converted to the type of x. Fixes PR9592. llvm-svn: 128625
* InstCombine: fold fcmp (fpext x), (fpext y) -> fcmp x, y.Benjamin Kramer2011-03-311-0/+7
| | | | llvm-svn: 128624
* Pick a conservative register class when creating a small live range for remat.Jakob Stoklund Olesen2011-03-311-1/+1
| | | | | | | | | | | | The rematerialized instruction may require a more constrained register class than the register being spilled. In the test case, the spilled register has been inflated to the DPR register class, but we are rematerializing a load of the ssub_0 sub-register which only exists for DPR_VFP2 registers. The register class is reinflated after spilling, so the conservative choice is only temporary. llvm-svn: 128610
* Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"Matt Beaumont-Gay2011-03-317-285/+66
| | | | | | This revision introduced a dependency cycle, as nlewycky mentioned by email. llvm-svn: 128597
* Somehow we managed to forget to encode the lane index for a large swathe of ↵Owen Anderson2011-03-302-21/+70
| | | | | | NEON instructions. With this fix, the entire test-suite passes with the Thumb integrated assembler. llvm-svn: 128587
* Don't try to create zero-sized stack objects.Evan Cheng2011-03-302-4/+6
| | | | llvm-svn: 128586
* - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT andBruno Cardoso Lopes2011-03-307-66/+285
| | | | | | | | | | | | | | | {STR,LDC}{2}_PRE. - Fixed the encoding in some places. - Some of those instructions were using am2offset and now use addrmode2. Codegen isn't affected, instructions which use SelectAddrMode2Offset were not touched. - Teach printAddrMode2Operand to check by the addressing mode which index mode to print. - This is a work in progress, more work to come. The idea is to change places which use am2offset to use addrmode2 instead, as to unify assembly parser. - Add testcases for assembly parser llvm-svn: 128585
* Add a ARM-specific SD node for VBSL so that forms with a constant first operandCameron Zwarich2011-03-304-9/+82
| | | | | | can be recognized. This fixes <rdar://problem/9183078>. llvm-svn: 128584
* * The DSE code that tested for overlapping needed to take into account the factBill Wendling2011-03-301-1/+3
| | | | | | | | | | | | that one of the numbers is signed while the other is unsigned. This could lead to a wrong result when the signed was promoted to an unsigned int. * Add the data layout line to the testcase so that it will test the appropriate thing. Patch by David Terei! llvm-svn: 128577
* fixed typoAkira Hatanaka2011-03-301-2/+2
| | | | llvm-svn: 128574
* Reset StringMap's NumTombstones on clears and rehashes.Jakob Stoklund Olesen2011-03-301-0/+3
| | | | | | | | | | | | | StringMap was not properly updating NumTombstones after a clear or rehash. This was not fatal until now because the table was growing faster than NumTombstones could, but with the previous change of preventing infinite growth of the table the invariant (NumItems + NumTombstones <= NumBuckets) stopped being observed, causing infinite loops in certain situations. Patch by José Fonseca! llvm-svn: 128567
* Prevent infinite growth of SmallPtrSet instances.Jakob Stoklund Olesen2011-03-301-6/+9
| | | | | | | | Rehash but don't grow when full of tombstones. Patch by José Fonseca! llvm-svn: 128566
* Prevent infinite growth of SmallMap instances.Jakob Stoklund Olesen2011-03-301-1/+13
| | | | | | | | Rehash but don't grow when full of tombstones. Patch by José Fonseca! llvm-svn: 128565
* Fix evil VirtRegRewriter bug.Jakob Stoklund Olesen2011-03-301-0/+28
| | | | | | | | | | | | | | | The rewriter can keep track of multiple stack slots in the same register if they happen to have the same value. When an instruction modifies a stack slot by defining a register that is mapped to a stack slot, other stack slots in that register are no longer valid. This is a very rare problem, and I don't have a simple test case. I get the impression that VirtRegRewriter knows it is about to be deleted, inventing a last opaque problem. <rdar://problem/9204040> llvm-svn: 128562
* Teach VirtRegRewriter about the new virtual register numbers. No functional ↵Jakob Stoklund Olesen2011-03-301-10/+11
| | | | | | change. llvm-svn: 128561
* Avoid turning a floating point division with a constant power of two into a ↵Benjamin Kramer2011-03-301-0/+8
| | | | | | | | | denormal multiplication. Some platforms may treat denormals as zero, on other platforms multiplication with a subnormal is slower than dividing by a normal. llvm-svn: 128555
* InstCombine: If the divisor of an fdiv has an exact inverse, turn it into an ↵Benjamin Kramer2011-03-301-0/+12
| | | | | | | | fmul. Fixes PR9587. llvm-svn: 128546
* Add APFloat::getExactInverse.Benjamin Kramer2011-03-301-0/+26
| | | | | | | | | | | | | | The idea is, that if an ieee 754 float is divided by a power of two, we can turn the division into a cheaper multiplication. This function sees if we can get an exact multiplicative inverse for a divisor and returns it if possible. This is the hard part of PR9587. I tested many inputs against llvm-gcc's frotend implementation of this optimization and didn't find any difference. However, floating point is the land of weird edge cases, so any review would be appreciated. llvm-svn: 128545
* Remove PHINode::reserveOperandSpace(). Instead, add a parameter toJay Foad2011-03-3031-78/+55
| | | | | | PHINode::Create() giving the (known or expected) number of operands. llvm-svn: 128537
* (Almost) always call reserveOperandSpace() on newly created PHINodes.Jay Foad2011-03-3021-21/+47
| | | | llvm-svn: 128535
* Treat clones the same as their origin.Jakob Stoklund Olesen2011-03-303-6/+29
| | | | | | | | | | | | When DCE clones a live range because it separates into connected components, make sure that the clones enter the same register allocator stage as the register they were cloned from. For instance, clones may be split even when they where created during spilling. Other registers created during spilling are not candidates for splitting or even (re-)spilling. llvm-svn: 128524
* Remove dead code.Bill Wendling2011-03-301-68/+0
| | | | llvm-svn: 128519
* Set the unnamed_addr only when we're creating a new GV in the dest module.Bill Wendling2011-03-291-0/+1
| | | | llvm-svn: 128507
* Revert r128501. It caused test failures.Bill Wendling2011-03-291-1/+0
| | | | llvm-svn: 128506
* Tidy up. 80 columns and trailing whitespace.Jim Grosbach2011-03-291-145/+146
| | | | llvm-svn: 128504
* Add intrinsics @llvm.arm.neon.vmulls and @llvm.arm.neon.vmullu.* back. FrontendsEvan Cheng2011-03-292-1/+7
| | | | | | | | | | | | | | | was lowering them to sext / uxt + mul instructions. Unfortunately the optimization passes may hoist the extensions out of the loop and separate them. When that happens, the long multiplication instructions can be broken into several scalar instructions, causing significant performance issue. Note the vmla and vmls intrinsics are not added back. Frontend will codegen them as intrinsics vmull* + add / sub. Also note the isel optimizations for catching mul + sext / zext are not changed either. First part of rdar://8832507, rdar://9203134 llvm-svn: 128502
* We need to copy over the unnamed_addr attribute.Bill Wendling2011-03-291-0/+1
| | | | llvm-svn: 128501
* InstCombine: Add a few missing combines for ANDs and ORs of sign bit tests.Benjamin Kramer2011-03-291-0/+24
| | | | | | | | On x86 we now compile "if (a < 0 && b < 0)" into testl %edi, %esi js IF.THEN llvm-svn: 128496
* Add Neon SINT_TO_FP and UINT_TO_FP lowering from v4i16 to v4f32. FixesCameron Zwarich2011-03-291-0/+35
| | | | | | <rdar://problem/8875309> and <rdar://problem/9057191>. llvm-svn: 128492
* Recompute register class and hint for registers created during spilling.Jakob Stoklund Olesen2011-03-296-60/+87
| | | | | | The spill weight is not recomputed for an unspillable register - it stays infinite. llvm-svn: 128490
* Added support symbolic floating point constants in the MC assembler for InfinityKevin Enderby2011-03-291-3/+11
| | | | | | and Nans with the same strings as GAS supports. rdar://8673024 llvm-svn: 128488
* Instantiate a JITMemoryManager for MCJIT DyldJim Grosbach2011-03-292-4/+8
| | | | llvm-svn: 128485
* DSE: Remove an early exit optimization that depended on the ordering of a ↵Benjamin Kramer2011-03-291-13/+0
| | | | | | | | SmallPtrSet. Fixes PR9569 and will hopefully make selfhost on ASLR-enabled systems more deterministic. llvm-svn: 128482
* Check early if this is an unsupported opcode, so that we can avoid ↵Owen Anderson2011-03-291-0/+4
| | | | | | needlessly instantiating the base register in some cases. llvm-svn: 128481
* A8.6.188 STC, STC2Johnny Chen2011-03-291-3/+3
| | | | | | | | The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}. rdar://problem/9200661 llvm-svn: 128478
* Remember to use the correct register when rematerializing for snippets.Jakob Stoklund Olesen2011-03-292-6/+7
| | | | llvm-svn: 128469
* Run dead code elimination immediately after rematerialization.Jakob Stoklund Olesen2011-03-291-9/+24
| | | | | | | This may eliminate some uses of the spilled registers, and we don't want to insert reloads for that. llvm-svn: 128468
* Add safety check that didn't show up in testing.Owen Anderson2011-03-291-0/+1
| | | | llvm-svn: 128467
* Inline check that's used only once.Bill Wendling2011-03-291-2/+1
| | | | llvm-svn: 128465
* Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't ↵Owen Anderson2011-03-296-77/+21
| | | | | | actually exist. llvm-svn: 128461
* Rework the logic (and removing the bad check for an unreachable block) so thatBill Wendling2011-03-291-8/+5
| | | | | | | the FailBB dominator is correctly calculated. Believe it or not, there isn't a functionality change here. llvm-svn: 128455
* Do some simple copy propagation through integer loads and stores when promotingCameron Zwarich2011-03-291-9/+14
| | | | | | | vector types. This helps a lot with inlined functions when using the ARM soft float ABI. Fixes <rdar://problem/9184212>. llvm-svn: 128453
* Don't try to add stack protector logic to a dead basic block. It messes upBill Wendling2011-03-291-1/+2
| | | | | | dominator information. llvm-svn: 128452
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