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* [WebAssembly] Preliminary fast-isel support.Dan Gohman2016-05-101-4/+542
| | | | llvm-svn: 269083
* WholeProgramDevirt: Move logic for finding devirtualizable call sites to ↵Peter Collingbourne2016-05-103-51/+95
| | | | | | | | | | | | | Analysis. The plan is to eventually make this logic simpler, however I expect it to be a little tricky for the foreseeable future (at least until we're rid of pointee types), so move it here so that it can be reused to build a summary index for devirtualization. Differential Revision: http://reviews.llvm.org/D20005 llvm-svn: 269081
* Simplify LLParser::ParseOptionalLinkage. NFC.Rafael Espindola2016-05-101-19/+34
| | | | llvm-svn: 269080
* [ScheduleDAG] Make sure to process all def operands before any use operandsKrzysztof Parzyszek2016-05-101-8/+25
| | | | | | | | | | | | | | | | | An example from Hexagon where things went wrong: %R0<def> = L2_loadrigp <ga:@fp04> ; load function address J2_callr %R0<kill>, ..., %R0<imp-def> ; call *R0, return value in R0 ScheduleDAGInstrs::buildSchedGraph would visit all instructions going backwards, and in each instruction it would visit all operands in their order on the operand list. In the case of this call, it visited the use of R0 first, then removed it from the set Uses after it visited the def. This caused the DAG to be missing the data dependence edge on R0 between the load and the call. Differential Revision: http://reviews.llvm.org/D20102 llvm-svn: 269076
* [PR27599] [SystemZ] [SelectionDAG] Fix extension of atomic cmpxchg result.Marcin Koscielnicki2016-05-103-6/+23
| | | | | | | | | | | | Currently, SelectionDAG assumes 8/16-bit cmpxchg returns either a sign extended result, or a zero extended result. SystemZ takes a third option by returning junk in the high bits (rotated contents of the other bytes in the memory word). In that case, don't use Assert*ext, and zero-extend the result ourselves if a comparison is needed. Differential Revision: http://reviews.llvm.org/D19800 llvm-svn: 269075
* [ThinLTO] Add option to emit imports files for distributed backendsTeresa Johnson2016-05-102-0/+39
| | | | | | | | | | | | | | | | | | | | | Summary: Add support for emission of plaintext lists of the imported files for each distributed backend compilation. Used for distributed build file staging. Invoked with new gold-plugin thinlto-emit-imports-files option, which is only valid with thinlto-index-only (i.e. for distributed builds), or from llvm-lto with new -thinlto-action=emitimports value. Depends on D19556. Reviewers: joker.eph Subscribers: llvm-commits, joker.eph Differential Revision: http://reviews.llvm.org/D19636 llvm-svn: 269067
* Restore "[ThinLTO] Emit individual index files for distributed backends"Teresa Johnson2016-05-103-71/+265
| | | | | | | | | | | | | | | | | | | This restores commit r268627: Summary: When launching ThinLTO backends in a distributed build (currently supported in gold via the thinlto-index-only plugin option), emit an individual index file for each backend process as described here: http://lists.llvm.org/pipermail/llvm-dev/2016-April/098272.html ... Differential Revision: http://reviews.llvm.org/D19556 Address msan failures by avoiding std::prev on map.end(), the theory is that this is causing issues due to some known UB problems in __tree. llvm-svn: 269059
* [LAA] Use re-written SCEV expressions when computing distancesSilviu Baranga2016-05-101-7/+2
| | | | | | | | | | | | This removes a redundant stride versioning step (we already do it in getPtrStride, so it has no effect) and uses PSE to get the SCEV expressions for the source and destination (this might have changed when getPtrStride was called). I discovered this through code inspection, and couldn't produce a regression test for it. llvm-svn: 269052
* Revert "[VectorUtils] Query number of sign bits to allow more truncations"James Molloy2016-05-101-14/+4
| | | | | | | | This was a fairly simple patch but on closer inspection was seriously flawed and caused PR27690. This reverts commit r268921. llvm-svn: 269051
* [mips][ias] Make the default path unreachable in needsRelocateWithSymbol() ↵Daniel Sanders2016-05-101-1/+114
| | | | | | | | | | | | | | | (except for N64). Following post-commit comments on r268900 from Rafael Espindola: The missing relocations are now explicitly listed in the switch statement with appropriate FIXME comments and the default path is now unreachable. The temporary exception to this is that compound relocations for N64 still have a default path that returns true. This is because fixing that case ought to be a separate patch. Also make R_MIPS_NONE return false since it has no effect on the section data. llvm-svn: 269047
* Update Debug Intrinsics in RewriteUsesOfClonedInstructions in LoopRotationChuang-Yu Cheng2016-05-101-0/+34
| | | | | | | | | | | | | | | | | | | | | | Loop rotation clones instruction from the old header into the preheader. If there were uses of values produced by these instructions that were outside the loop, we have to insert PHI nodes to merge the two values. If the values are used by DbgIntrinsics they will be used as a MetadataAsValue of a ValueAsMetadata of the original values, and iterating all of the uses of the original value will not update the DbgIntrinsics. The new code checks if the values are used by DbgIntrinsics and if so, updates them using essentially the same logic as the original code. The attached testcase demonstrates the issue. Without the fix, the DbgIntrinic outside the loop uses values computed inside the loop, even though these values do not dominate the DbgIntrinsic. Author: Thomas Jablin (tjablin) Reviewers: dblaikie aprantl kbarton hfinkel cycheng http://reviews.llvm.org/D19564 llvm-svn: 269034
* [InstCombine] Remove trivially empty va_start/va_end and va_copy/va_end ranges.Arnaud A. de Grandmaison2016-05-102-22/+59
| | | | | | | | | | | | When a va_start or va_copy is immediately followed by a va_end (ignoring debug information or other start/end in between), then it is safe to remove the pair. As this code shares some commonalities with the lifetime markers, this has been factored to helper functions. This InstCombine pattern kicks-in 3 times when running the LLVM test suite. llvm-svn: 269033
* Revert "[PGO] Fix __llvm_profile_raw_version linkage in MACHO IR ↵Renato Golin2016-05-101-1/+1
| | | | | | | | | | | | | instrumentation generates a COMDAT symbol __llvm_profile_raw_version to overwrite the same symbol in profile run-time to distinguish IR profiles from Clang generated profiles. In MACHO, LinkOnceODR linkage is used due to the lack of COMDAT support." This reverts commits r268969, r268979 and r268984. They had target specific test in generic directories without the correct specifiers and made it hard for us to come up with a good solution by rapidly committing untested changes. This test needs to be in a target specific directory or have the correct REQUIRED identifier. llvm-svn: 269027
* [foldMemoryOperand()] Pass LiveIntervals to enable liveness check.Jonas Paulsson2016-05-109-29/+52
| | | | | | | | | | | | | | | SystemZ (and probably other targets as well) can fold a memory operand by changing the opcode into a new instruction that as a side-effect also clobbers the CC-reg. In order to do this, liveness of that reg must first be checked. When LIS is passed, getRegUnit() can be called on it and the right LiveRange is computed on demand. Reviewed by Matthias Braun. http://reviews.llvm.org/D19861 llvm-svn: 269026
* [LoopVectorize] Handling induction variable with non-constant step.Elena Demikhovsky2016-05-102-49/+119
| | | | | | | | | | | | | | | | | | | | | | | Allow vectorization when the step is a loop-invariant variable. This is the loop example that is getting vectorized after the patch: int int_inc; int bar(int init, int *restrict A, int N) { int x = init; for (int i=0;i<N;i++){ A[i] = x; x += int_inc; } return x; } "x" is an induction variable with *loop-invariant* step. But it is not a primary induction. Primary induction variable with non-constant step is not handled yet. Differential Revision: http://reviews.llvm.org/D19258 llvm-svn: 269023
* [LAA] Rename "isStridedPtr" with "getPtrStride". NFC.Denis Zobnin2016-05-103-8/+8
| | | | | | | Changing misleading function name was approved in http://reviews.llvm.org/D17268. Patch by Roman Shirokiy. llvm-svn: 269021
* [X86][AVX512] Strengthen the assertions from r269001. We need VLX to use the ↵Craig Topper2016-05-101-2/+3
| | | | | | 128/256-bit move opcodes for extended registers. llvm-svn: 269019
* [X86] Add ZMM registers to the X86_INTR calling convention preserved mask ↵Craig Topper2016-05-101-0/+2
| | | | | | when AVX512 is enabled. llvm-svn: 269018
* [X86] Update X86_INTR calling convention to save ZMM registers instead of ↵Craig Topper2016-05-101-2/+3
| | | | | | YMM registers when AVX512 is enabled. llvm-svn: 269017
* LiveIntervalAnalysis: Rework constructMainRangeFromSubranges()Matthias Braun2016-05-104-246/+48
| | | | | | | | | | | | | | | | | | We now use LiveRangeCalc::extendToUses() instead of a specially designed algorithm in constructMainRangeFromSubranges(): - The original motivation for constructMainRangeFromSubranges() were differences between the main liverange and subranges because of hidden dead definitions. This case however cannot happen anymore with the DetectDeadLaneMasks pass in place. - It simplifies the code. - This fixes a longstanding bug where we did not properly create new SSA values on merging control flow (the MachineVerifier missed most of these cases). - Move constructMainRangeFromSubranges() to LiveIntervalAnalysis and LiveRangeCalc to better match the implementation/available helper functions. llvm-svn: 269016
* LiveInterval: Avoid unnecessary auto, add const; NFCMatthias Braun2016-05-101-3/+3
| | | | llvm-svn: 269015
* TargetPassConfig: Set PrintMachineCode even if addMachinePasses() does not run.Matthias Braun2016-05-101-5/+5
| | | | llvm-svn: 269013
* [WebAssembly] Move register stackification and coloring to a late phase.Dan Gohman2016-05-1015-250/+578
| | | | | | | | | | | | | | | | | | | Move the register stackification and coloring passes to run very late, after PEI, tail duplication, and most other passes. This means that all code emitted and expanded by those passes is now exposed to these passes. This also eliminates the need for prologue/epilogue code to be manually stackified, which significantly simplifies the code. This does require running LiveIntervals a second time. It's useful to think of these late passes not as late optimization passes, but as a domain-specific compression algorithm based on knowledge of liveness information. It's used to compress the code after all conventional optimizations are complete, which is why it uses LiveIntervals at a phase when actual optimization passes don't typically need it. Differential Revision: http://reviews.llvm.org/D20075 llvm-svn: 269012
* CodeGen: Move TargetPassConfig from Passes.h to an own header; NFCMatthias Braun2016-05-1022-4/+30
| | | | | | | | Many files include Passes.h but only a fraction needs to know about the TargetPassConfig class. Move it into an own header. Also rename Passes.cpp to TargetPassConfig.cpp while we are at it. llvm-svn: 269011
* PrologEpilogInserter: Remove unnecessary dependencyMatthias Braun2016-05-101-2/+0
| | | | llvm-svn: 269010
* [ValueTracking] Use guards to prove non-nullness of a valueSanjoy Das2016-05-101-9/+11
| | | | | | | | | | Reviewers: apilipenko, majnemer, reames Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D20044 llvm-svn: 269008
* [BasicAA] Guard intrinsics don't write to memorySanjoy Das2016-05-101-4/+32
| | | | | | | | | | | | | | | | Summary: The idea is very close to what we do for assume intrinsics: we mark the guard intrinsics as writing to arbitrary memory to maintain control dependence, but under the covers we teach AA that they do not mod any particular memory location. Reviewers: chandlerc, hfinkel, gbiv, reames Subscribers: george.burgess.iv, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D19575 llvm-svn: 269007
* LLVMTargetMachine: Add functions to create MIModuleInfo/MIFunction; NFCMatthias Braun2016-05-101-9/+17
| | | | | | | | | | | Add convenience function to create MachineModuleInfo and MachineFunctionAnalysis passes and add them to a pass manager. Despite factoring out some shared code in LiveIntervalTest/LLVMTargetMachine this will be used by my upcoming llc change. llvm-svn: 269002
* [X86][AVX512] Use the proper load/store for AVX512 registers.Quentin Colombet2016-05-103-10/+25
| | | | | | | | | | | | | | When loading or storing AVX512 registers we were not using the AVX512 variant of the load and store for VR128 and VR256 like registers. Thus, we ended up with the wrong encoding and actually were dropping the high bits of the instruction. The result was that we load or store the wrong register. The effect is visible only when we emit the object file directly and disassemble it. Then, the output of the disassembler does not match the assembly input. This is related to llvm.org/PR27481. llvm-svn: 269001
* [SCEVExpander] Clang format expressions; NFCSanjoy Das2016-05-101-17/+16
| | | | | | The boolean expressions are somewhat hard to read otherwise. llvm-svn: 268998
* [SCEV] Use guards to prove predicatesSanjoy Das2016-05-101-3/+44
| | | | | | | | | We can use calls to @llvm.experimental.guard to prove predicates, relying on the fact that in all locations domianted by a call to @llvm.experimental.guard the predicate it is guarding is known to be true. llvm-svn: 268997
* Minor formatting fixes in LoopUnroll.cpp.Justin Lebar2016-05-101-4/+2
| | | | llvm-svn: 268995
* [NVPTX] Change begin/end inline asm comments to "begin/end inline asm".Justin Lebar2016-05-101-2/+2
| | | | | | | Previously it was just "// inline asm", which made it tricky to read code with lots of inline assembly. llvm-svn: 268994
* [WebAssembly] Disable 128-bit shift libcallsDerek Schuff2016-05-101-0/+7
| | | | | | | | Currently the signature of the functions i128(i128, i32) aka void(i32, i64, i64, i32) doesn't match the signature of the call emitted by the default lowering, void(i32, i64, i64). llvm-svn: 268991
* SDAG: Stop relying on Select's return value in SystemZ's ↵Justin Bogner2016-05-091-14/+38
| | | | | | | | | | | | | | | splitLargeImmediate. NFC The call to Select on Upper here happens in an unusual order in order to defeat the constant folding that getNode() does. Add a comment explaining why we can't just move the Select to later to avoid a Handle, and wrap the call to SelectCode in a handle so we don't need its return value. This is part of the work to have Select return void instead of an SDNode *, which is in turn part of llvm.org/pr26808. llvm-svn: 268990
* Fix some Clang-tidy modernize-deprecated-headers and Include What You Use ↵Eugene Zelenko2016-05-092-4/+16
| | | | | | | | warnings; other minor fixes. Differential revision: http://reviews.llvm.org/D20042 llvm-svn: 268989
* [LV] Hint at the new loop distribution pragma in optimization remarkAdam Nemet2016-05-091-2/+6
| | | | | | | | | | When we encounter unsafe memory dependencies, loop distribution could help. Even though, the diagnostics is in LAA, it's only currently emitted in the vectorizer. llvm-svn: 268987
* [IndirectCallPromotion] Remove duplicate comment. NFCAdam Nemet2016-05-091-1/+0
| | | | llvm-svn: 268986
* [X86] Fix the AllRegs AVX calling convention.Quentin Colombet2016-05-091-1/+1
| | | | | | | | | | We used to list registers that were not in the AVX space. In other words, we were pushing registers that the ISA cannot encode (YMM16-YMM31). This is part of llvm.org/PR27481. llvm-svn: 268983
* [Inliner] don't assume that a Constant alloca size is a ConstantInt (PR27277)Sanjay Patel2016-05-091-4/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D20077 llvm-svn: 268980
* Typo. NFC.Chad Rosier2016-05-091-1/+1
| | | | llvm-svn: 268975
* Cleanup followup of r268710 - [PM] port IR based PGO prof-gen pass to new ↵Xinliang David Li2016-05-091-26/+25
| | | | | | pass manager llvm-svn: 268974
* [X86] Strengthen the setting of inline asm constraints for fp regclasses.Quentin Colombet2016-05-091-5/+22
| | | | | | | | | | | | | This is similar to r268953, but for floating point and vector register classes. Explanations: The setting of the inline asm constraints was implicitly relying on the order of the register classes in the file generated by tablegen. Since, we do not have any control on that order, make sure we do not depend on it anymore. llvm-svn: 268973
* [X86][SSE] Improve cost model for i64 vector comparisons on pre-SSE42 targetsSimon Pilgrim2016-05-091-3/+11
| | | | | | | | | | | | As discussed on PR24888, until SSE42 we don't have access to PCMPGTQ for v2i64 comparisons, but the cost models don't reflect this, resulting in over-optimistic vectorizaton. This patch adds SSE2 'base level' costs that match what a typical target is capable of and only reduces the v2i64 costs at SSE42. Technically SSE41 provides a PCMPEQQ v2i64 equality test, but as getCmpSelInstrCost doesn't give us a way to discriminate between comparison test types we can't easily make use of this, otherwise we could split the cost of integer equality and greater-than tests to give better costings of each. Differential Revision: http://reviews.llvm.org/D20057 llvm-svn: 268972
* [PGO] Fix __llvm_profile_raw_version linkage in MACHORong Xu2016-05-091-1/+1
| | | | | | | | | | | | | | | | | | | IR instrumentation generates a COMDAT symbol __llvm_profile_raw_version to overwrite the same symbol in profile run-time to distinguish IR profiles from Clang generated profiles. In MACHO, LinkOnceODR linkage is used due to the lack of COMDAT support. But LinkOnceODR linkage might have .weak_def_can_be_hidden assembly directive, while the weak variable in run-time has a .weak_definition directive. Linker will not merge these two symbols even they have the same name. The end result is IR profiles are not properly flagged in MACHO. This patch changes the linkage for __llvm_profile_raw_version in each module to LinkOnceAny so that it has same .weak_definition directive as in the run-time. Differential Revision: http://reviews.llvm.org/D20078 llvm-svn: 268969
* [libFuzzer] add a test for libFuzzer+ubsan, extend the docs on using ↵Kostya Serebryany2016-05-094-0/+56
| | | | | | libFuzzer+ubsan llvm-svn: 268968
* [MSan] [AArch64] Fix vararg helper for >1 or non-int fixed arguments.Marcin Koscielnicki2016-05-091-3/+13
| | | | | | | | | | | | | | | | | | This fixes http://llvm.org/PR27646 on AArch64. There are three issues here: - The GR save area is 7 words in size, instead of 8. This is not enough if none of the fixed arguments is passed in GRs (they're all floats or aggregates). - The first argument is ignored (which counteracts the above if it's passed in GR). - Like x86_64, fixed arguments landing in the overflow area are wrongly counted towards the overflow offset. Differential Revision: http://reviews.llvm.org/D20023 llvm-svn: 268967
* Separate the Verifier into an analysis and a transformation pass andAdrian Prantl2016-05-093-5/+36
| | | | | | | | | | | | | | | | | | | | | | | | allow the transformation to strip invalid debug info. This patch separates the Verifier into an analysis and a transformation pass, with the transformation pass optionally stripping malformed debug info. The problem I'm trying to solve with this sequence of patches is that historically we've done a really bad job at verifying debug info. We want to be able to make the verifier stricter without having to worry about breaking bitcode compatibility with existing producers. For example, we don't necessarily want IR produced by an older version of clang to be rejected by an LTO link just because of malformed debug info, and rather provide an option to strip it. Note that merely outdated (but well-formed) debug info would continue to be auto-upgraded in this scenario. http://reviews.llvm.org/D19988 rdar://problem/25818489 This reapplies r268937 without modifications. llvm-svn: 268966
* Allow the LTO code generator to strip invalid debug info from the input.Adrian Prantl2016-05-092-3/+27
| | | | | | | | | | | | | | | | | | | | | This patch introduces a new option -lto-strip-invalid-debug-info, which drops malformed debug info from the input. The problem I'm trying to solve with this sequence of patches is that historically we've done a really bad job at verifying debug info. We want to be able to make the verifier stricter without having to worry about breaking bitcode compatibility with existing producers. For example, we don't necessarily want IR produced by an older version of clang to be rejected by an LTO link just because of malformed debug info, and rather provide an option to strip it. Note that merely outdated (but well-formed) debug info would continue to be auto-upgraded in this scenario. rdar://problem/25818489 http://reviews.llvm.org/D19987 This reapplies 268936 with a test case fix for Linux (-exported-symbol foo) llvm-svn: 268965
* [X86] Drop the 64-bit alignment for LOW32_ADDR_ACCESS register class.Quentin Colombet2016-05-091-2/+3
| | | | | | | The only 64-bit register in that register class is RIP and it will not get spilled in the current ABIs. llvm-svn: 268963
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