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* Remove TimeValue usage from llvm/SupportPavel Labath2016-10-249-93/+125
| | | | | | | | | | | | | | | | | Summary: This is a follow-up to D25416. It removes all usages of TimeValue from llvm/Support library (except for the actual TimeValue declaration), and replaces them with appropriate usages of std::chrono. To facilitate this, I have added small utility functions for converting time points and durations into appropriate OS-specific types (FILETIME, struct timespec, ...). Reviewers: zturner, mehdi_amini Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25730 llvm-svn: 284966
* [mips] synci microMIPS instruction definition.Simon Dardis2016-10-243-3/+15
| | | | | | | | | | | | | Add synci to the microMIPS instruction definitions, mark the MIPS sync & synci as not being part of microMIPS. This does not cover the sync instruction alias, as that will be handled with a different patch. Add sync to the valid tests for microMIPS. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D25795 llvm-svn: 284962
* [AVX-512] Remove masked pmin/pmax intrinsics and autoupgrade to native IR.Craig Topper2016-10-242-53/+16
| | | | | | Clang patch to replace 512-bit vector and 64-bit element versions with native IR will follow. llvm-svn: 284955
* [DAG] enhance computeKnownBits to handle SRL/SRA with vector splat constantSanjay Patel2016-10-231-43/+32
| | | | llvm-svn: 284953
* Use SDValue::getConstantOperandVal() helper. NFCI.Simon Pilgrim2016-10-231-4/+1
| | | | llvm-svn: 284949
* Remove LLVM_CONSTEXPR.Justin Lebar2016-10-231-2/+1
| | | | | | | | | | | | Summary: With MSVC 2013 and GCC < 4.8 gone, we can use the "constexpr" keyword. Reviewers: bkramer, mehdi_amini Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25901 llvm-svn: 284947
* [X86][SSE] Add SSE41/AVX1 costs for vector shifts.Simon Pilgrim2016-10-231-0/+26
| | | | | | We were defaulting to SSE2 costs which weren't taking into account the availability of PBLENDW/PBLENDVB to improve merging of per-element shift results. llvm-svn: 284939
* Use APInt::isAllOnesValue instead of popcnt. NFCI.Simon Pilgrim2016-10-231-1/+1
| | | | | | More obvious implementation and faster too. llvm-svn: 284937
* [AVR] Add the machine code disassemblerDylan McKay2016-10-225-1/+190
| | | | | | | | This adds a super basic implementation of a machine code disassembler. It doesn't support any operands with custom encoding. llvm-svn: 284930
* [X86][AVX512VL] Added support for combining target 256-bit shuffles to ↵Simon Pilgrim2016-10-221-0/+3
| | | | | | AVX512VL VPERMV3 llvm-svn: 284922
* [X86][AVX512] Added support for combining target shuffles to AVX512 VPERMV3Simon Pilgrim2016-10-221-0/+22
| | | | llvm-svn: 284921
* [ARM] Fix crash in ConstantIslandsJames Molloy2016-10-221-1/+3
| | | | | | tPCRelJT may not be the first instruction in a block. Check that instead of dereferencing a broken iterator. llvm-svn: 284917
* [X86] Add support for printing shuffle comments for VALIGN instructions.Craig Topper2016-10-223-0/+56
| | | | llvm-svn: 284915
* [X86] Add support for lowering v4i64 and v8i64 shuffles directly to PALIGNR. ↵Craig Topper2016-10-221-0/+8
| | | | | | I think shuffle combine can figure it out later, but we should try to get it right up front. llvm-svn: 284914
* [X86] Remove unnecessary AVX2 check that was already covered by an assertion ↵Craig Topper2016-10-221-2/+2
| | | | | | earlier in the function. NFC llvm-svn: 284913
* [X86] Remove 128-bit lane handling from the main loop of ↵Craig Topper2016-10-221-54/+49
| | | | | | | | matchVectorShuffleAsByteRotate. Instead check for is128LaneRepeatedSuffleMask before the loop and just loop over the repeated mask. I plan to use the loop to support VALIGND/Q shuffles so this makes it easier to reuse. llvm-svn: 284912
* [X86][SSE] Use getConstVector helper for VPERMV mask generation. NFCI.Simon Pilgrim2016-10-221-14/+5
| | | | llvm-svn: 284911
* Now that VS2013 is gone, make a memoryssa structure an anonymous union againDaniel Berlin2016-10-221-4/+4
| | | | llvm-svn: 284910
* [libFuzzer] mutation: insert the size of the input in bytes as one of the ↵Kostya Serebryany2016-10-222-11/+21
| | | | | | ways to mutate a binary integer llvm-svn: 284909
* [BasicAA] Fix - missed alias in GEP expressionsGerolf Hoflehner2016-10-221-5/+11
| | | | | | | | | | | | In BasicAA GEP operand values get adjusted ("wrap-around") based on the pointersize. Otherwise, in non-64b modes, AA could report false negatives. However, a wrap-around is valid only for a fully evaluated expression. It had been introduced to fix an alias problem in http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20160118/326163.html. This commit restricts the wrap-around to constant gep operands only where the value is known at compile-time. llvm-svn: 284908
* [CtorUtils] Modernize. No functional changes intended.Davide Italiano2016-10-221-5/+5
| | | | llvm-svn: 284904
* [libFuzzer] typo in a testKostya Serebryany2016-10-221-1/+1
| | | | llvm-svn: 284903
* [libFuzzer] add a test for asan's strict_string_checks=1Kostya Serebryany2016-10-223-0/+26
| | | | llvm-svn: 284902
* [AMDGPU] Perform uchar to float combine for ISD::SINT_TO_FPKonstantin Zhuravlyov2016-10-211-4/+13
| | | | | | | | | This will prevent following regression when enabling i16 support (D18049): test/CodeGen/AMDGPU/cvt_f32_ubyte.ll Differential Revision: https://reviews.llvm.org/D25805 llvm-svn: 284891
* AMDGPU/SI: Fix crash caused by r284267Tom Stellard2016-10-211-2/+3
| | | | | | | | | | Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D25782 llvm-svn: 284875
* [DAG] enhance computeKnownBits to handle SHL with vector splat constantSanjay Patel2016-10-211-10/+9
| | | | | | Also, use APInt to avoid crashing on types larger than vNi64. llvm-svn: 284874
* Analysis: Move llvm::getConstantRangeFromMetadata to IR library.Peter Collingbourne2016-10-214-22/+24
| | | | | | | | We're about to start using it there. Differential Revision: https://reviews.llvm.org/D25877 llvm-svn: 284865
* X86: Improve BT instruction selection for 64-bit values.Peter Collingbourne2016-10-211-0/+8
| | | | | | | | | | If a 64-bit value is tested against a bit which is known to be in the range [0..31) (modulo 64), we can use the 32-bit BT instruction, which has a slightly shorter encoding. Differential Revision: https://reviews.llvm.org/D25862 llvm-svn: 284864
* [X86][AVX512BWVL] Added support for lowering v16i16 shuffles to AVX512BWVL ↵Simon Pilgrim2016-10-211-16/+20
| | | | | | vpermw llvm-svn: 284863
* [pdb] added support for dumping globals streamBob Haarman2016-10-216-46/+236
| | | | | | | | | | | | Summary: This adds support for dumping the globals stream from PDB files using llvm-pdbdump, similar to the support we have for the publics stream. Reviewers: ruiu, zturner Subscribers: beanz, mgorny, modocache Differential Revision: https://reviews.llvm.org/D25801 llvm-svn: 284861
* [X86][AVX512BWVL] Added support for combining target v16i16 shuffles to ↵Simon Pilgrim2016-10-211-2/+2
| | | | | | AVX512BWVL vpermw llvm-svn: 284860
* [X86][AVX512] Added support for combining target shuffles to AVX512 ↵Simon Pilgrim2016-10-211-7/+11
| | | | | | vpermpd/vpermq/vpermps/vpermd/vpermw llvm-svn: 284858
* [RDF] Use RegisterId typedef more consistently, NFCKrzysztof Parzyszek2016-10-213-11/+12
| | | | llvm-svn: 284857
* [StripGCRelocates] New pass to remove gc.relocates added by RS4GCAnna Thomas2016-10-213-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Utility pass to remove gc.relocates created by rewrite statepoints for GC. With respect to safepoint verification, the IR generated would be incorrect, and cannot run as such. This would be a single transformation on the final optimized IR. The benefit of the pass is for easy analysis when the IRs are 'polluted' by too many gc.relocates. Added tests. test run: All RS4GC tests with -verify option. Local downstream tests on large IR files. This also works when the pointer being gc.relocated is another gc.relocate. Reviewers: sanjoy, reames Subscribers: beanz, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D25096 llvm-svn: 284855
* [DAG] fold negation of sign-bitSanjay Patel2016-10-211-11/+27
| | | | | | | | | | | | | | | | 0 - X --> 0, if the sub is NUW 0 - X --> 0, if X is 0 or the minimum signed value and the sub is NSW 0 - X --> X, if X is 0 or the minimum signed value This is the DAG equivalent of: https://reviews.llvm.org/rL284649 plus the fold for the NUW case which already existed in InstSimplify. Note that we miss a vector fold because of a deficiency in the DAG version of computeKnownBits(). llvm-svn: 284844
* [Hexagon] Handle spills of partially defined double vector registersKrzysztof Parzyszek2016-10-211-21/+36
| | | | | | | | | | | | After register allocation it is possible to have a spill of a register that is only partially defined. That in itself it fine, but creates a problem for double vector registers. Stores of such registers are pseudo instructions that are expanded into pairs of individual vector stores, and in case of a partially defined source, one of the stores may use an entirely undefined register. To avoid this, track the defined parts and only generate actual stores for those. llvm-svn: 284841
* [WebAssembly] Fix for 0xc call_indirect changesDerek Schuff2016-10-216-20/+159
| | | | | | | | | | | | | | | | | Summary: Need to reorder the operands to have the callee as the last argument. Adds a pseudo-instruction, and a pass to lower it into a real call_indirect. This is the first of two options for how to fix the problem. Reviewers: dschuff, sunfish Subscribers: jfb, beanz, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D25708 llvm-svn: 284840
* Set the vectorizer MaxInterleaveFactor for Exynos.Abderrazek Zaafrani2016-10-211-0/+1
| | | | llvm-svn: 284839
* Fix -Wunused-variable warning in libFuzzerReid Kleckner2016-10-211-1/+1
| | | | llvm-svn: 284838
* [X86] Use DAG::getBuildVector helper wrapper where possible. NFCI.Simon Pilgrim2016-10-211-4/+4
| | | | llvm-svn: 284835
* Test commitAbderrazek Zaafrani2016-10-211-1/+0
| | | | llvm-svn: 284832
* [LVI] Fix a bug with a guard being the very first instruction in a BB not ↵Artur Pilipenko2016-10-211-5/+4
| | | | | | | | taken into account While looking for guards use reverse iterator and scan up to rend() not to begin() llvm-svn: 284827
* fix variable names; NFCISanjay Patel2016-10-211-2/+2
| | | | | | | | Because we're just 'or-ing' these 2 variables later in the code, I don't think there's a logical bug here, but of course the string with "no size" is the one that should have the size suffix stripped off. llvm-svn: 284826
* [AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed.Artem Tamazov2016-10-211-4/+4
| | | | | | | | Fixes Bug 28215. Lit tests updated. Differential Revision: https://reviews.llvm.org/D25837 llvm-svn: 284825
* [DAG] use SDNode flags 'nsz' to enable fadd/fsub with zero foldsSanjay Patel2016-10-211-16/+20
| | | | | | | | | | | | | | | | | | | | | As discussed in D24815, let's start the process of killing off the broken fast-math global state housed in TargetOptions and eliminate the need for function-level fast-math attributes. Here we enable two similar folds that are possible when we don't care about signed-zero: fadd nsz x, 0 --> x fsub nsz 0, x --> -x Note that although the test cases include a 'sin' function call, I'm side-stepping the FMF-on-calls question (and lack of support in the DAG) for now. It's not needed for these tests - isNegatibleForFree/GetNegatedExpression just look through a ISD::FSIN node. Also, when we create an FNEG node and propagate the Flags of the FSUB to it, this doesn't actually do anything today because Flags are silently dropped for any node that is not a binary operator. Differential Revision: https://reviews.llvm.org/D25297 llvm-svn: 284824
* [X86][AVX2] Begun generalizing lowering to VPERMD/VPERMPS in preparation for ↵Simon Pilgrim2016-10-211-8/+9
| | | | | | AVX512 support. llvm-svn: 284823
* [X86][AVX512] Add mask/maskz writemask support to subvector broadcast ↵Simon Pilgrim2016-10-211-0/+40
| | | | | | shuffle decode comments llvm-svn: 284821
* [LoopUnroll] Keep the loop test only on the first iteration of max-or-zero loopsJohn Brawn2016-10-213-33/+65
| | | | | | | | | | | | | | | | When we have a loop with a known upper bound on the number of iterations, and furthermore know that either the number of iterations will be either exactly that upper bound or zero, then we can fully unroll up to that upper bound keeping only the first loop test to check for the zero iteration case. Most of the work here is in plumbing this 'max-or-zero' information from the part of scalar evolution where it's detected through to loop unrolling. I've also gone for the safe default of 'false' everywhere but howManyLessThans which could probably be improved. Differential Revision: https://reviews.llvm.org/D25682 llvm-svn: 284818
* [AArch64] Corrected spill size for DDD register class. NFCIBjorn Pettersson2016-10-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Summary: The spill size was incorrectly set to 196 bits, which isn't a multiple of 8. This problem was detected when experimenting with asserts that the spill size should be a multiple of the byte size. New corrected value for the spill size is set to 192 bits. Note that tablegen (RegisterInfoEmitter) will divide the size set in the RegisterClass definition by 8. So this change should not have any impact on the tablegen output (trunc(192/8) == trunc(196/8) == 24 bytes). Reviewers: t.p.northover Subscribers: llvm-commits, aemerson, rengolin Differential Revision: https://reviews.llvm.org/D25818 llvm-svn: 284814
* Revert "[GVN/PRE] Hoist global values outside of loops."Davide Italiano2016-10-211-58/+26
| | | | | | | | | There's no agreement about this patch. I personally find the PRE machinery of the current GVN hard enough to reason about that I'm not sure I'll try to land this again, instead of working on the rewrite). llvm-svn: 284796
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