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* Revert "[Thumb/Thumb2] Added restrictions on PC, LR, SP in the register list ↵Rafael Espindola2014-12-041-145/+89
| | | | | | | | | | for PUSH/POP/LDM/STM. <Differential Revision: http://reviews.llvm.org/D6090>" This reverts commit r223356. It was failing check-all (MC/ARM/thumb.s in particular). llvm-svn: 223363
* [X86] Improve a dag-combine that handles a vector extract -> zext sequence.Michael Kuperstein2014-12-041-24/+51
| | | | | | | | | The current DAG combine turns a sequence of extracts from <4 x i32> followed by zexts into a store followed by scalar loads. According to measurements by Martin Krastev (see PR 21269) for x86-64, a sequence of an extract, movs and shifts gives better performance. However, for 32-bit x86, the previous sequence still seems better. Differential Revision: http://reviews.llvm.org/D6501 llvm-svn: 223360
* [Thumb/Thumb2] Added restrictions on PC, LR, SP in the register list for ↵Jyoti Allur2014-12-041-89/+145
| | | | | | PUSH/POP/LDM/STM. <Differential Revision: http://reviews.llvm.org/D6090> llvm-svn: 223356
* [X86] Simplify code. NFC.Andrea Di Biagio2014-12-041-16/+6
| | | | | | | | Replaced some logic that checked if a build_vector node is doing a splat of a non-undef value with a call to method BuildVectorSDNode::getSplatValue(). No functional change intended. llvm-svn: 223354
* Use DomTree in MachineSink to sink over diamonds.Patrik Hagglund2014-12-041-15/+19
| | | | | | | | | | | | | | | | | | | | | According to a previous FIXME comment we now not only look at MBB successors, but also handle code sinking past them: x = computation if () {} else {} use x The instruction could be sunk over the whole diamond for the if/then/else (or loop, etc), allowing it to be sunk into other blocks after that. Modified test added in r204522, due to one spill less present. Minor fixes in comments. Patch provided by Jonas Paulsson. Reviewed by Hal Finkel. llvm-svn: 223350
* [InstCombine] Minor optimization for bswap with binary opsSimon Pilgrim2014-12-043-0/+67
| | | | | | | | | | | | | | | | | Added instcombine optimizations for BSWAP with AND/OR/XOR ops: OP( BSWAP(x), BSWAP(y) ) -> BSWAP( OP(x, y) ) OP( BSWAP(x), CONSTANT ) -> BSWAP( OP(x, BSWAP(CONSTANT) ) ) Since its just a one liner, I've also added BSWAP to the DAGCombiner equivalent as well: fold (OP (bswap x), (bswap y)) -> (bswap (OP x, y)) Refactored bswap-fold tests to use FileCheck instead of just checking that the bswaps had gone. Differential Revision: http://reviews.llvm.org/D6407 llvm-svn: 223349
* Masked Load / Store Intrinsics - the CodeGen part.Elena Demikhovsky2014-12-0416-6/+661
| | | | | | | | | | | | | | | | | | I'm recommiting the codegen part of the patch. The vectorizer part will be send to review again. Masked Vector Load and Store Intrinsics. Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores. Added SDNodes for masked operations and lowering patterns for X86 code generator. Examples: <16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask) declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask) Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch. http://reviews.llvm.org/D6191 llvm-svn: 223348
* Restrict somewhat the memory-allocation pointer cmp opt from r223093Hal Finkel2014-12-041-3/+13
| | | | | | | | | | Based on review comments from Richard Smith, restrict this optimization from applying to globals that might resolve lazily to other dynamically-loaded modules, and also from dynamic allocas (which might be transformed into malloc calls). In short, take extra care that the compared-to pointer is really simultaneously live with the memory allocation. llvm-svn: 223347
* clang-formatted ranged loops and assignment, NFC.Yaron Keren2014-12-041-12/+12
| | | | llvm-svn: 223344
* Add mach-o LC_RPATH support to llvm-objdumpJean-Daniel Dupas2014-12-041-0/+5
| | | | | | | | | | Summary: Add rpath load command support in Mach-O object and update llvm-objdump to use it. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6512 llvm-svn: 223343
* [X86] Clean up whitespace as well as minor coding styleMichael Liao2014-12-0433-409/+403
| | | | llvm-svn: 223339
* [Hexagon] Marking some instructions as CodeGenOnly=0 and adding disassembly ↵Colin LeMahieu2014-12-043-3/+9
| | | | | | tests. llvm-svn: 223334
* [X86] Restore X86 base pointer after call to llvm.eh.sjlj.setjmpMichael Liao2014-12-044-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit on - This patch fixes the bug described in http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-May/062343.html The fix allocates an extra slot just below the GPRs and stores the base pointer there. This is done only for functions containing llvm.eh.sjlj.setjmp that also need a base pointer. Because code containing llvm.eh.sjlj.setjmp saves all of the callee-save GPRs in the prologue, the offset to the extra slot can be computed before prologue generation runs. Impact at run-time on affected functions is:: - One extra store in the prologue, The store saves the base pointer. - One extra load after a llvm.eh.sjlj.setjmp. The load restores the base pointer. Because the extra slot is just above a gap between frame-pointer-relative and base-pointer-relative chunks of memory, there is no impact on other offset calculations other than ensuring there is room for the extra slot. http://reviews.llvm.org/D6388 Patch by Arch Robison <arch.robison@intel.com> llvm-svn: 223329
* [PowerPC] 'cc' should be an alias only to 'cr0'Hal Finkel2014-12-041-4/+2
| | | | | | | | | | | We had mistakenly believed that GCC's 'cc' referred to the entire condition-code register (cr0 through cr7) -- and implemented this in r205630 to fix PR19326, but 'cc' is actually an alias only to 'cr0'. This is causing LLVM to clobber too much with legacy code with inline asm using the 'cc' clobber. Fixes PR21451. llvm-svn: 223328
* HexagonMCInst.h: Qualify constants explicitly to appease msc17.NAKAMURA Takumi2014-12-041-2/+2
| | | | llvm-svn: 223325
* Allow target to specify prefix for labelsMatt Arsenault2014-12-049-4/+13
| | | | | | | | Use the MCAsmInfo instead of the DataLayout, and allow specifying a custom prefix for labels specifically. HSAIL requires that labels begin with @, but global symbols with &. llvm-svn: 223323
* A few more checks for gc.statepoints in the VerifierPhilip Reames2014-12-041-0/+11
| | | | | | | | | This is simply a grab bag of unrelated checks: - A statepoint call can't be marked readonly or readnone - We don't currently support inline asm or varadic target functions. Both could be supported, but don't currently work. - I forgot to check that the number of call arguments actually matched the wrapped callee in my previous change. Included here. llvm-svn: 223322
* [PowerPC] Fix inline asm memory operands not to use r0Hal Finkel2014-12-031-2/+12
| | | | | | | | | | | | | | | On PowerPC, inline asm memory operands might be expanded as 0($r), where $r is a register containing the address. As a result, this register cannot be r0, and we need to enforce this register subclass constraint to prevent miscompiling the code (we'd get this constraint for free with the usual instruction definitions, but that scheme has no knowledge of how we end up printing inline asm memory operands, and so here we need to do it 'by hand'). We can accomplish this within the current address-mode selection framework by introducing an explicit COPY_TO_REGCLASS node. Fixes PR21443. llvm-svn: 223318
* [RegAllocFast] Handle implicit definitions conservatively.Quentin Colombet2014-12-031-7/+14
| | | | | | | | | | | | | | | | | Prior to this commit, physical registers defined implicitly were considered free right after their definition, i.e.. like dead definitions. Therefore, their uses had to immediately follow their definitions, otherwise the related register may be reused to allocate a virtual register. This commit fixes this assumption by keeping implicit definitions alive until they are actually used. The downside is that if the implicit definition was dead (and not marked at such), we block an otherwise available register. This is however conservatively correct and makes the fast register allocator much more robust in particular regarding the scheduling of the instructions. Fixes PR21700. llvm-svn: 223317
* [msan] allow -fsanitize-coverage=N together with -fsanitize=memory, llvm partKostya Serebryany2014-12-032-2/+5
| | | | llvm-svn: 223312
* Test commit.Jacques Pienaar2014-12-031-2/+2
| | | | llvm-svn: 223310
* Split the set of identified struct types into opaque and non-opaque ones.Rafael Espindola2014-12-031-106/+201
| | | | | | | | | | | | | | | | | | | The non-opaque part can be structurally uniqued. To keep this to just a hash lookup, we don't try to unique cyclic types. Also change the type mapping algorithm to be optimistic about a type not being recursive and only create a new type when proven to be wrong. This is not as strong as trying to speculate that we can keep the source type, but is simpler (no speculation to revert) and more powerfull than what we had before (we don't copy non-recursive types at least). I initially wrote this to try to replace the name based type merging. It is not strong enough to replace it, but is is a useful addition. With this patch the number of named struct types is a clang lto bootstrap goes from 49674 to 15986. llvm-svn: 223278
* fix typos, grammar, formatting; NFCSanjay Patel2014-12-031-22/+19
| | | | llvm-svn: 223276
* Strength Verifier checks around the types involved in a statepointPhilip Reames2014-12-031-6/+23
| | | | | | Add checks that the types in a gc.statepoint sequence match the wrapper callee and that relocating a pointer doesn't change it's type. llvm-svn: 223275
* correct spelling, NFCMatthias Braun2014-12-031-3/+3
| | | | llvm-svn: 223274
* [SimplifyLibCalls] Improve double->float shrinking to consider constantsMatthias Braun2014-12-031-14/+33
| | | | | | | | | | This allows cases like float x; fmin(1.0, x); to be optimized to fminf(1.0f, x); rdar://19049359 Differential Revision: http://reviews.llvm.org/D6496 llvm-svn: 223270
* [SimplifyLibCalls] Enable double to float shrinking for copysignMatthias Braun2014-12-031-0/+1
| | | | | | | | rdar://19049359 Differential Revision: http://reviews.llvm.org/D6495 llvm-svn: 223269
* [Hexagon] Converting member InstrDesc to static variable.Colin LeMahieu2014-12-034-22/+28
| | | | llvm-svn: 223268
* [Hexagon] Converting subclass members to an implicit operand.Colin LeMahieu2014-12-033-24/+68
| | | | llvm-svn: 223264
* Make the Verifier more strict about gc.statepointsPhilip Reames2014-12-031-28/+60
| | | | | | The recently added documentation for statepoints claimed that we checked the parameters of the various intrinsics for validity. This patch adds the code to actually do so. I also removed a couple of redundant checks for conditions which are checked elsewhere in the Verifier and simplified the logic using the helper functions from Statepoint.h. llvm-svn: 223259
* Add TableGen info for Power8.Will Schmidt2014-12-032-0/+395
| | | | | | | | This is based on the Power7 version, with units added and renamed to match P8. Differential Revision: http://reviews.llvm.org/D6358 llvm-svn: 223257
* Change the name to be in style.Roman Divacky2014-12-031-1/+1
| | | | llvm-svn: 223255
* R600/SI: Move SIInsertWaits into AMDGPUPassConfig::addPreSched2()Tom Stellard2014-12-031-1/+3
| | | | | | | This pass needs to be run after PrologEpilogInserter, because that pass may inserter spill code which reads or writes memory. llvm-svn: 223253
* R600/SI: Don't run SI passes on R600 subtargetsTom Stellard2014-12-031-1/+1
| | | | llvm-svn: 223252
* AArch64: fix wrong-endian parameter passing.Tim Northover2014-12-031-2/+4
| | | | | | | The blocked arguments code didn't take account of the hacks needed to support it. llvm-svn: 223247
* [NFC] Fixing pendantic warning extra semicolons.Colin LeMahieu2014-12-031-7/+7
| | | | llvm-svn: 223246
* [Hexagon] [NFC] Moving function implementations out of header. ↵Colin LeMahieu2014-12-032-79/+88
| | | | | | Clang-formatting files. llvm-svn: 223245
* [Hexagon] [NFC] Renaming *packetStart to *packetBeginColin LeMahieu2014-12-033-11/+11
| | | | llvm-svn: 223243
* Silencing a 32-bit implicit conversion warning in MSVC; NFC.Aaron Ballman2014-12-031-1/+1
| | | | llvm-svn: 223237
* msan] Add compile-time checks for missing origins.Evgeniy Stepanov2014-12-031-10/+13
| | | | | | | | | | | | This change makes MemorySanitizer instrumentation a bit more strict about instructions that have no origin id assigned to them. This would have caught the bug that was fixed in r222918. This is re-commit of r222997, reverted in r223211, with 3 more missing origins added. llvm-svn: 223236
* InstCombine: simplify signed range checksErik Eckstein2014-12-032-0/+74
| | | | | | | | | Try to convert two compares of a signed range check into a single unsigned compare. Examples: (icmp sge x, 0) & (icmp slt x, n) --> icmp ult x, n (icmp slt x, 0) | (icmp sgt x, n) --> icmp ugt x, n llvm-svn: 223224
* [PowerPC] Print all inline-asm consts as signed numbersHal Finkel2014-12-031-13/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | Almost all immediates in PowerPC assembly (both 32-bit and 64-bit) are signed numbers, and it is important that we print them as such. To make sure that happens, we change PPCTargetLowering::LowerAsmOperandForConstraint so that it does all intermediate checks on a signed-extended int64_t value, and then creates the resulting target constant using MVT::i64. This will ensure that all negative values are printed as negative values (mirroring what is done in other backends to achieve the same sign-extension effect). This came up in the context of inline assembly like this: "add%I2 %0,%0,%2", ..., "Ir"(-1ll) where we used to print: addi 3,3,4294967295 and gcc would print: addi 3,3,-1 and gas accepts both forms, but our builtin assembler (correctly) does not. Now we print -1 like gcc does. While here, I replaced a bunch of custom integer checks with isInt<16> and friends from MathExtras.h. Thanks to Paul Hargrove for the bug report. llvm-svn: 223220
* Emit ABI_FP_rounding attribute.Charlie Turner2014-12-031-0/+6
| | | | | | | | | | | | LLVM understands a -enable-sign-dependent-rounding-fp-math codegen option. When the user has specified this option, the Tag_ABI_FP_rounding attribute should be emitted with value 1. This option currently does not appear to disable transformations and optimizations that assume default floating point rounding behavior, AFAICT, but the intention should be recorded in the build attributes, regardless of what the compiler actually does with the intention. Change-Id: If838578df3dc652b6f2796b8d152545674bcb30e llvm-svn: 223218
* Ask the module for its the identified types.Rafael Espindola2014-12-034-7/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When lazy reading a module, the types used in a function will not be visible to a TypeFinder until the body is read. This patch fixes that by asking the module for its identified struct types. If a materializer is present, the module asks it. If not, it uses a TypeFinder. This fixes pr21374. I will be the first to say that this is ugly, but it was the best I could find. Some of the options I looked at: * Asking the LLVMContext. This could be made to work for gold, but not currently for ld64. ld64 will load multiple modules into a single context before merging them. This causes us to see types from future merges. Unfortunately, MappedTypes is not just a cache when it comes to opaque types. Once the mapping has been made, we have to remember it for as long as the key may be used. This would mean moving MappedTypes to the Linker class and having to drop the Linker::LinkModules static methods, which are visible from C. * Adding an option to ignore function bodies in the TypeFinder. This would fix the PR by picking the worst result. It would work, but unfortunately we are currently quite dependent on the upfront type merging. I will try to reduce our dependency, but it is not clear that we will be able to get rid of it for now. The only clean solution I could think of is making the Module own the types. This would have other advantages, but it is a much bigger change. I will propose it, but it is nice to have this fixed while that is discussed. With the gold plugin, this patch takes the number of types in the LTO clang binary from 52817 to 49669. llvm-svn: 223215
* Revert r222997. The newly added compile-time checks are finding missing ↵Nick Lewycky2014-12-031-10/+9
| | | | | | origins, testcase is being reduced and a PR will be posted shortly. llvm-svn: 223211
* LoopVectorize: Remove unnecessary RAUWDuncan P. N. Exon Smith2014-12-031-2/+0
| | | | | | | | | | Remove an unnecessary `MDNode::replaceAllUsesWith()`. In the preceding line, `TheLoop->setLoopID()` visits all backedges and sets the new loop ID. This sufficiently updates the loop metadata. Metadata RAUW is going away as part of PR21532. llvm-svn: 223210
* R600/SI: Fix SIFixSGPRCopies for copies to physical registersMatt Arsenault2014-12-031-1/+6
| | | | | | | This shows up when operands required to be passed in VCC are copied to. llvm-svn: 223208
* R600/SI: Remove incorrect assertionMatt Arsenault2014-12-031-5/+5
| | | | | | This can be a COPY to a physical register, such as VCC llvm-svn: 223207
* R600/SI: Remove i1 pseudo VALU opsMatt Arsenault2014-12-033-63/+70
| | | | | | | | | | | | | | Select i1 logical ops directly to 64-bit SALU instructions. Vector i1 values are always really in SGPRs, with each bit for each item in the wave. This saves about 4 instructions when and/or/xoring any condition, and also helps write conditions that need to be passed in vcc. This should work correctly now that the SGPR live range fixing pass works. More work is needed to eliminate the VReg_1 pseudo regclass and possibly the entire SILowerI1Copies pass. llvm-svn: 223206
* R600/SI: Fix suspicious indexingMatt Arsenault2014-12-031-5/+7
| | | | | | | | The loop is over the operands of an instruction, and checks the register with the sub reg index of the dest register. This probably meant to be checking the sub reg index of the same operand. llvm-svn: 223205
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