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* [MemorySSA] Remove redundant walker assignment [NFC].Alina Sbirlea2019-03-141-3/+1
| | | | | Subscribers: llvm-commits llvm-svn: 356189
* [GlobalISel][AArch64] Add partial selection support for G_INSERT_VECTOR_ELTJessica Paquette2019-03-143-0/+59
| | | | | | | | | | | This adds support for inserting elements into packed vectors. It also adds two tests: one for selection, and one for regbank select. Unpacked vectors will come in a follow-up. Differential Revision: https://reviews.llvm.org/D59325 llvm-svn: 356182
* [ARC] Better classify add/sub immediate instructions in frame lowering.Pete Couperus2019-03-141-10/+40
| | | | | | | | | | | | | | | | | | | Summary: Some operations have multiple ARC instructions that are applicable. For instance, "add r0, r0, 123" can be encoded as a "LImm" instruction with a 32-bit immediate (8-bytes), or as a signed 12-bit immediate instruction for the case where the source and destination register are the same (4-bytes). The ARC assembler will choose the shortest encoding, but we should track the correct instruction in the compiler. This patch fixes the instruction used in some cases from ARCFrameLowering. Subscribers: hiraditya, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59326 llvm-svn: 356179
* Allow code motion (and thus folding) for atomic (but unordered) memory operandsPhilip Reames2019-03-141-3/+1
| | | | | | | | | | Building on the work done in D57601, now that we can distinguish between atomic and volatile memory accesses, go ahead and allow code motion of unordered atomics. As seen in the diffs, this allows much better folding of memory operations into using instructions. (Mostly done by the PeepholeOpt pass.) Note: I have not reviewed all callers of hasOrderedMemoryRef since one of them - isSafeToMove - is very widely used. I'm relying on the documented semantics of each method to judge correctness. Differential Revision: https://reviews.llvm.org/D59345 llvm-svn: 356170
* [X86] Fix the pattern changes from r356121 so that the ROR*r1/ROR*m1 pattern ↵Craig Topper2019-03-141-8/+8
| | | | | | | | | | | | use the rotr opcode. These instructions used to use rotl with a bitwidth-1 immediate. I changed the immediate to 1, but failed to change the opcode. Thankfully this seems to have not caused a functional issue because we now had two rotl by 1 patterns, but the correct ones were earlier and took priority. So we just missed some optimization. llvm-svn: 356164
* Add IR debug info support for Elemental, Pure, and Recursive Procedures.Adrian Prantl2019-03-141-0/+6
| | | | | | | | Patch by Eric Schweitz! Differential Revision: https://reviews.llvm.org/D54043 llvm-svn: 356163
* [x86] prevent infinite looping from vselect commutation (PR41066)Sanjay Patel2019-03-141-6/+8
| | | | | | | | | This is an immediate fix for: https://bugs.llvm.org/show_bug.cgi?id=41066 ...but as noted there and the code comments, we should do better by stubbing this out sooner. llvm-svn: 356158
* AMDGPU: Scavenge register instead of findUnusedRegMatt Arsenault2019-03-141-1/+1
| | | | llvm-svn: 356149
* GlobalISel: Use multiple returns for intrinsic structsMatt Arsenault2019-03-142-16/+9
| | | | | | | | | | | This is consistent with what SelectionDAG does and is much easier to work with than the extract sequence with an artificial wide register. For the AMDGPU control flow intrinsics, this was producing an s128 for the i64, i1 tuple return. Any legalization that should apply to a real s128 value would badly obscure the direct values that need to be seen. llvm-svn: 356147
* [SampleFDO] add suffix elision control for fcn namesThan McIntosh2019-03-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add hooks for determining the policy used to decide whether/how to chop off symbol 'suffixes' when locating a given function in a sample profile. Prior to this change, any function symbols of the form "X.Y" were elided/truncated into just "X" when looking up things in a sample profile data file. With this change, the policy on suffixes can be changed by adding a new attribute "sample-profile-suffix-elision-policy" to the function: this attribute can have the value "all" (the default), "selected", or "none". A value of "all" preserves the previous behavior (chop off everything after the first "." character, then treat that as the symbol name). A value of "selected" chops off only the rightmost ".llvm.XXXX" suffix (where "XXX" is any string not containing a "." char). A value of "none" indicates that names should be left as is. Subscribers: jdoerfert, wmi, mtrofin, danielcdh, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58832 llvm-svn: 356146
* AMDGPU: Don't add unnecessary convergent attributesMatt Arsenault2019-03-141-19/+2
| | | | | | These are redundant with the intrinsic declaration. llvm-svn: 356143
* Fix for buildbotsSam Parker2019-03-141-11/+9
| | | | | | Remove unused private field. llvm-svn: 356135
* [ARM][ParallelDSP] Enable multiple uses of loadsSam Parker2019-03-141-84/+115
| | | | | | | | | | | | | | | | When choosing whether a pair of loads can be combined into a single wide load, we check that the load only has a sext user and that sext also only has one user. But this can prevent the transformation in the cases when parallel macs use the same loaded data multiple times. To enable this, we need to fix up any other uses after creating the wide load: generating a trunc and a shift + trunc pair to recreate the narrow values. We also need to keep a record of which loads have already been widened. Differential Revision: https://reviews.llvm.org/D59215 llvm-svn: 356132
* [NFC][LSR] Cleanup Cost APISam Parker2019-03-141-63/+54
| | | | | | | | | Create members for Loop, ScalarEvolution, DominatorTree, TargetTransformInfo and Formula. Differential Revision: https://reviews.llvm.org/D58389 llvm-svn: 356131
* [ARM] Run ARMParallelDSP in the IRPasses phaseSam Parker2019-03-141-3/+6
| | | | | | | | | Run EarlyCSE before ParallelDSP and do this in the backend IR opt phase. Differential Revision: https://reviews.llvm.org/D59257 llvm-svn: 356130
* [RISCV] Fix rL356123Alex Bradbury2019-03-141-2/+2
| | | | | | The wrong version of the patch was committed. This fixes typos that broke the build. llvm-svn: 356124
* [RISCV][NFC] Rename callee saved regs 'CSR' to CSR_ILP32_LP64 and minor ↵Alex Bradbury2019-03-142-7/+10
| | | | | | | | | | | | | RISCVRegisterInfo refactoring The CSR renaming further prepares the way for an upcoming patch adding support for more RISC-V ABIs. Modify RISCVRegisterInfo::getCalleeSavedRegs and RISCVRegisterInfo::getReservedRegs to do MF->getSubtarget<RISCVSubtarget>() once rather than multiple times. llvm-svn: 356123
* [X86] Add patterns for rotr by immediate to fix PR41057.Craig Topper2019-03-141-9/+52
| | | | | | | | | | | | | | | | | | Prior to the introduction of funnel shift intrinsics we could count on rotate by immediates prefering to use rotl since that's what MatchRotate would check first. The or+shift pattern doesn't have a direction so one must be chosen arbitrarily. With funnel shift, there is a direction and fshr will try to use rotr first. While fshl will try to use rotl first. This patch adds the isel patterns for rotr to complement the rotl patterns. I've put the rotr by 1 patterns in the instruction patterns. And moved the rotl by bitwidth-1 patterns to separate Pat patterns. Fixes PR41057. llvm-svn: 356121
* [GlobalISel][Utils] Add a getConstantVRegVal variant that looks through instrsQuentin Colombet2019-03-142-10/+60
| | | | | | | | | | | | | | | | | | | getConstantVRegVal used to only look for G_CONSTANT when looking at unboxing the value of a vreg. However, constants are sometimes not directly used and are hidden behind trunc, s|zext or copy chain of computation. In particular this may be introduced by the legalization process that doesn't want to simplify these patterns because it can lead to infine loop when legalizing a constant. To circumvent that problem, add a new variant of getConstantVRegVal, named getConstantVRegValWithLookThrough, that allow to look through extensions. Differential Revision: https://reviews.llvm.org/D59227 llvm-svn: 356116
* [ResetMachineFunctionPass] Add visited functions statistics infoCraig Topper2019-03-141-0/+2
| | | | | | | | | | | | | Adding a "NumFunctionsVisited" for collecting the visited function number. It can be used to collect function pass rate in some tests, the pass rate = (NumberVisited - NumberReset)/NumberVisited. e.g. it can be used for caculating GlobalISel pass rate in Test-Suite. Patch by Tianyang Zhu (zhutianyang) Differential Revision: https://reviews.llvm.org/D59285 llvm-svn: 356114
* [AArch64][GlobalISel] Gardening: Simplify subregister copy in selectBuildVectorJessica Paquette2019-03-131-20/+16
| | | | | | | | | | NFC. Some more preliminary factoring for G_INSERT_VECTOR_ELT. Also better code-reuse, etc., etc. Differential Revision: https://reviews.llvm.org/D59323 llvm-svn: 356107
* [GlobalISel][AArch64] Gardening: Factor out vector insertsJessica Paquette2019-03-131-33/+47
| | | | | | | | | | | Factor out the vector insert code in `selectBuildVector`. Replace part of it with `emitScalarToVector`, since it was pretty much equivalent. This will make implementing G_INSERT_VECTOR_ELT easier. Differential Revision: https://reviews.llvm.org/D59322 llvm-svn: 356106
* [WebAssembly] Improve support for "needed" list in dylink sectionSam Clegg2019-03-131-0/+1
| | | | | | | | | | | This change adds basic support for shared library dependencies via the dylink section. See https://github.com/WebAssembly/tool-conventions/pull/77 Differential Revision: https://reviews.llvm.org/D59237 llvm-svn: 356102
* [GlobalISel][AArch64] Gardening: Factor out code to find lane indicesJessica Paquette2019-03-131-22/+37
| | | | | | | | | | | | | Some more refactoring for G_INSERT_VECTOR_ELT. Factor out the code used to find a lane index from `selectExtractElt`. Put it into a more general-purpose `getConstantValueForReg` function. This will be shared with the code for G_INSERT_VECTOR_ELT. Differential Revision: https://reviews.llvm.org/D59324 llvm-svn: 356101
* [AMDGPU] Silence gcc 7 warningsStanislav Mekhanoshin2019-03-135-38/+9
| | | | | | Differential Revision: https://reviews.llvm.org/D59330 llvm-svn: 356100
* Verifier: Make sure masked load/store alignment is a power of 2Matt Arsenault2019-03-131-2/+6
| | | | | | | The same should also be done for scatter/gather, but the verifier doesn't check those at all now. llvm-svn: 356094
* [MsgPack] Removed MsgPackTypesTim Renouf2019-03-132-303/+0
| | | | | | | | | | Summary: MsgPackTypes has been replaced by the lighter-weight MsgPackDocument. Differential Revision: https://reviews.llvm.org/D57025 Change-Id: Ia7069880ef29f55490abbe5d8ae15f25cc1490a4 llvm-svn: 356082
* [AMDGPU] Switched HSA metadata to use MsgPackDocumentTim Renouf2019-03-135-212/+188
| | | | | | | | | | | | Summary: MsgPackDocument is the lighter-weight replacement for MsgPackTypes. This commit switches AMDGPU HSA metadata processing to use MsgPackDocument instead of MsgPackTypes. Differential Revision: https://reviews.llvm.org/D57024 Change-Id: I0751668013abe8c87db01db1170831a76079b3a6 llvm-svn: 356081
* [MsgPack] New MsgPackDocument classTim Renouf2019-03-133-0/+496
| | | | | | | | | | | | | | | | | | | Summary: A class that exposes a simple in-memory representation of a document of MsgPack objects, that can be read from and written to MsgPack, read from and written to YAML, and inspected and modified in memory. This is intended to be a lighter-weight (in terms of memory allocations) replacement for MsgPackTypes. Two subsequent changes will: 1. switch AMDGPU HSA metadata to using MsgPackDocument instead of MsgPackTypes; 2. add MsgPack AMDGPU PAL metadata via MsgPackDocument. Differential Revision: https://reviews.llvm.org/D57023 Change-Id: Ie15a054831d5a6467c5867c064c8f8f6b80270e1 llvm-svn: 356080
* [X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b()Craig Topper2019-03-133-2/+4
| | | | | | | | | | | | The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well. We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass. I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue. Differential Revision: https://reviews.llvm.org/D59308 llvm-svn: 356078
* [DAGCombiner] Fix Comment. NFC.Nirav Dave2019-03-131-1/+1
| | | | llvm-svn: 356069
* [DAGCombiner] If a TokenFactor would be merged into its user, consider the ↵Nirav Dave2019-03-131-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | user later. Summary: A number of optimizations are inhibited by single-use TokenFactors not being merged into the TokenFactor using it. This makes we consider if we can do the merge immediately. Most tests changes here are due to the change in visitation causing minor reorderings and associated reassociation of paired memory operations. CodeGen tests with non-reordering changes: X86/aligned-variadic.ll -- memory-based add folded into stored leaq value. X86/constant-combiners.ll -- Optimizes out overlap between stores. X86/pr40631_deadstore_elision -- folds constant byte store into preceding quad word constant store. Reviewers: RKSimon, craig.topper, spatel, efriedma, courbet Reviewed By: courbet Subscribers: dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, eraman, hiraditya, kbarton, jrtc27, atanasyan, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59260 llvm-svn: 356068
* [X86][AVX] Add X86ISD::VTRUNC handling to ↵Simon Pilgrim2019-03-131-0/+14
| | | | | | SimplifyDemandedVectorEltsForTargetNode llvm-svn: 356067
* [X86][AVX] Add combineConcatVectors support to improve subvector handlingSimon Pilgrim2019-03-131-0/+39
| | | | | | | | | | Attempt to combine CONCAT_VECTORS nodes, which we only really have pre-legalization. This encourages a lot of X86ISD::SUBV_BROADCAST generation, so I've added SimplifyDemandedVectorEltsForTargetNode handling for this at the same time. The X86ISD::VTRUNC regression in shuffle-vs-trunc-256-widen.ll will be handled in a future commit. llvm-svn: 356064
* [RISCV] Only mark fp as reserved if the function has a dedicated frame pointerAlex Bradbury2019-03-131-1/+3
| | | | | | | | This follows similar logic in the ARM and Mips backends, and allows the free use of s0 in functions without a dedicated frame pointer. The changes in callee-saved-gprs.ll most clearly show the effect of this patch. llvm-svn: 356063
* [mips] Join some adjacent `let DecoderNamespace` blocks. NFCSimon Atanasyan2019-03-131-13/+7
| | | | llvm-svn: 356059
* [x86] limit extractelement of setcc to pre-legalizationSanjay Patel2019-03-131-1/+1
| | | | | | | | | | | | | | A fuzzer found the crasher: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=13700 The bug was introduced recently here: rL355741 This is the quick fix. If we need to do this transform later, then we'd have to extend/truncate the vector setcc element type to the scalar setcc type (i8). llvm-svn: 356053
* [mips] Fix encoding of the `mov.d` command for microMIPS R6Simon Atanasyan2019-03-133-3/+7
| | | | | | | | | Before this change LLVM emits non-microMIPS variant of the `mov.d` command for microMIPS code. Differential Revision: http://reviews.llvm.org/D59045 llvm-svn: 356052
* [mips] Define `mov.d` instructions using `ABSS_M` multiclass. NFCSimon Atanasyan2019-03-131-6/+1
| | | | llvm-svn: 356051
* Re-land r354244 "[DAGCombiner] Eliminate dead stores to stack."Clement Courbet2019-03-131-0/+89
| | | | | | Always check candidates for hasOtherUses(), not only stores. llvm-svn: 356050
* Fix signed/unsigned mismatch warning. NFCI.Simon Pilgrim2019-03-131-1/+1
| | | | llvm-svn: 356046
* [mips] Map SW instruction to its microMIPS R6 variantSimon Atanasyan2019-03-133-3/+6
| | | | | | | | | | | | | | | | To provide mapping between standard and microMIPS R6 variants of the `sw` command we have to rename SWSP_xxx commands from "sw" to "swsp". Otherwise `tablegen` starts to show the error `Multiple matches found for `SW'`. After that to restore printing SWSP command as `sw`, I add an appropriate `MipsInstAlias` instance. We also need to implement "size reduction" for microMIPS R6. But this task is for separate patch. After that the `micromips-lwsp-swsp.ll` test case will be extended. Differential Revision: http://reviews.llvm.org/D59046 llvm-svn: 356045
* [X86][AVX] lowerShuffleAsBroadcast - improve load folding by avoiding bitcastsSimon Pilgrim2019-03-131-70/+47
| | | | | | | | | | AVX1 broadcasts were failing as we were adding bitcasts that caused MayFoldLoad's hasOneUse to return false. This patch stops introducing bitcasts so early and also replaces the broadcast index scaling through bitcasts (which can't succeed in some cases) to instead just keep track of the bitoffset which can be converted back to the broadcast index later on. Differential Revision: https://reviews.llvm.org/D58888 llvm-svn: 356043
* [DAG] Move integer setcc %x, %x folding into FoldSetCCSimon Pilgrim2019-03-132-5/+6
| | | | | | | | | | First step towards PR40800 - I intend to move the float case in a separate future patch. I had to tweak the (overly reduced) thumb2 test and the x86 widening test change is annoying (no longer rematerializable) but we should address this separately. Differential Revision: https://reviews.llvm.org/D59244 llvm-svn: 356040
* [MIPS][microMIPS] Fix PseudoMTLOHI_MM matching and expansionSimon Atanasyan2019-03-132-1/+6
| | | | | | | | | | | | | | On micromips MipsMTLOHI is always matched to PseudoMTLOHI_DSP regardless of +dsp argument. This patch checks is HasDSP predicate is present for PseudoMTLOHI_DSP so PseudoMTLOHI_MM can be matched when appropriate. Add expansion of PseudoMTLOHI_MM instruction into a mtlo/mthi pair. Patch by Mirko Brkusanin. Differential Revision: http://reviews.llvm.org/D59203 llvm-svn: 356039
* [ELF] Fix GCC8 warnings about "fall through", NFCIJonas Hahnfeld2019-03-132-0/+10
| | | | | | | | | | | | | | | Add break statements in Object/ELF.cpp since the code should consider the generic tags for Hexagon, MIPS, and PPC. Add a test (copied from llvm-readobj) to show that this works correctly (earlier versions of this patch would have asserted). The warnings in X86ELFObjectWriter.cpp are actually false-positives since the nested switch() handles all possible values and returns in all cases. Make this explicit by adding llvm_unreachable's. Differential Revision: https://reviews.llvm.org/D58837 llvm-svn: 356037
* [Support] Treat truncation of fullpath as errorJonas Hahnfeld2019-03-131-1/+5
| | | | | | | | | | | | If the concatenation of arguments dir and bin has at least PATH_MAX characters the call to snprintf will truncate. The result will usually not exist, but if it does it's actually incorrect to return that the path exists. (Motivated by GCC compiler warning about format truncation.) Differential Revision: https://reviews.llvm.org/D58835 llvm-svn: 356036
* [RISCV] Replace incorrect use of sizeof with array_lengthofAlex Bradbury2019-03-131-3/+3
| | | | | | | RISCVDisassembler was incorrectly using sizeof(Arr) when it should have used sizeof(Arr)/sizeof(Arr[0]). Update to use array_lengthof instead. llvm-svn: 356035
* [ImplicitNullChecks] Support unordered atomic accessesPhilip Reames2019-03-131-5/+2
| | | | | | Update the INC pass to allow folding unordered atomics. This is the first optimization unblocked by the changes landed from D57601. llvm-svn: 356006
* Revert "[llvm] Skip over empty line table entries."Evgeniy Stepanov2019-03-131-7/+0
| | | | | | | This reverts commit r355972. See the discussion at https://reviews.llvm.org/D58952. llvm-svn: 356001
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