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* IPO: Add missing build dep.Peter Collingbourne2017-05-011-1/+1
| | | | llvm-svn: 301835
* [X86][AVX] Rename LowerVectorBroadcast to lowerBuildVectorAsBroadcast. NFCI.Simon Pilgrim2017-05-011-11/+8
| | | | | | Since the shuffle refactor, this is only used during BUILD_VECTOR lowering. llvm-svn: 301834
* Object: Remove ModuleSummaryIndexObjectFile class.Peter Collingbourne2017-05-016-142/+26
| | | | | | Differential Revision: https://reviews.llvm.org/D32195 llvm-svn: 301832
* [Hexagon] Replace CVI_VM_CUR_LD type with CVI_VM_LDKrzysztof Parzyszek2017-05-0110-114/+187
| | | | | | | | A .cur instruction can be identified by checking isCVINew() && mayLoad(). Patch by Colin LeMahieu. llvm-svn: 301829
* [Hexagon] Improving error reporting for writing to read only registersKrzysztof Parzyszek2017-05-013-8/+23
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301828
* [Hexagon] Give better error messages for solo instruction errorsKrzysztof Parzyszek2017-05-012-7/+11
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301827
* [Hexagon] Improve shuffle error reportingKrzysztof Parzyszek2017-05-0111-482/+276
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301823
* X86: initialize a few subtarget variables.Tim Northover2017-05-011-0/+3
| | | | | | Otherwise an indeterminate value gets read, causing a bunch of UBSan failures. llvm-svn: 301819
* Take indirect branch into account as well when folding.Xin Tong2017-05-011-6/+10
| | | | | | | | We may not be able to rewrite indirect branch target, but we also want to take it into account when folding, i.e. if it and all its successor's predecessors go to the same destination, we can fold, i.e. no need to thread. llvm-svn: 301816
* Add a new WeakVH value handle; NFCSanjoy Das2017-05-011-2/+5
| | | | | | This relands r301425. llvm-svn: 301813
* Rename WeakVH to WeakTrackingVH; NFCSanjoy Das2017-05-0126-142/+136
| | | | | | This relands r301424. llvm-svn: 301812
* [WebAssembly] Fix use of SDNodeFlags after API change in r301803Derek Schuff2017-05-011-2/+2
| | | | llvm-svn: 301811
* [PDB/CodeView] Rename some classes.Zachary Turner2017-05-015-20/+22
| | | | | | | | | | | | In preparation for introducing writing capabilities for each of these classes, I would like to adopt a Foo / FooRef naming convention, where Foo indicates that the class can manipulate and serialize Foos, and FooRef indicates that it is an immutable view of an existing Foo. In other words, Foo is a writer and FooRef is a reader. This patch names some existing readers to conform to the FooRef convention, while offering no functional change. llvm-svn: 301810
* Emulate TrackingVH using WeakVHSanjoy Das2017-05-011-16/+3
| | | | | | | | | | | | | | | | Summary: This frees up one slot in the HandleBaseKind enum, which I will use later to add a new kind of value handle. The size of the HandleBaseKind enum is important because we store a HandleBaseKind in the low two bits of a (in the worst case) 4 byte aligned pointer. Reviewers: davide, chandlerc Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D32634 llvm-svn: 301809
* [JumpThread] Add some assertions for expected ConstantInt/BlockAddressXin Tong2017-05-011-2/+5
| | | | llvm-svn: 301808
* Remove unnecessary conditions as suggested by clang-tidy. NFCGabor Horvath2017-05-013-8/+4
| | | | | | | | Patch by: Gergely Angeli! Differential Revision: https://reviews.llvm.org/D31936 llvm-svn: 301807
* [SelectionDAG] Use known ones to provide a better bound for the known zeros ↵Craig Topper2017-05-011-2/+16
| | | | | | | | | | | | | | for CTTZ/CTLZ operations. This is the SelectionDAG version of D32521. If know where at least one 1 is located in the input to these intrinsics we can place an upper bound on the number of bits needed to represent the count and thus increase the number of known zeros in the output. I think we can also refine this further for CTTZ_UNDEF/CTLZ_UNDEF by assuming that the answer will never be BitWidth. I've left this out for now because it caused other test failures across multiple targets. Usually because of turning ADD into OR based on this new information. I'll fix CTPOP in a future patch. Differential Revision: https://reviews.llvm.org/D32692 llvm-svn: 301806
* [JumpThread] Do RAUW in case Cond folds to a constant in the CFGXin Tong2017-05-011-8/+24
| | | | | | | | | | | | | | Summary: [JumpThread] Do RAUW in case Cond folds to a constant in the CFG Reviewers: sanjoy Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32407 llvm-svn: 301804
* Generalize the specialized flag-carrying SDNodes by moving flags into SDNode.Amara Emerson2017-05-0112-160/+125
| | | | | | | | This removes BinaryWithFlagsSDNode, and flags are now all passed by value. Differential Revision: https://reviews.llvm.org/D32527 llvm-svn: 301803
* [LLVM][inline-asm] Altmacro absolute expression '%' featureMichael Zuckerman2017-05-012-7/+51
| | | | | | | | | | | | | | | | | | | | | In this patch, I introduce a new alt macro feature. This feature adds meaning for the % when using it as a prefix to the calling macro arguments. In the altmacro mode, the percent sign '%' before an absolute expression convert the expression first to a string. As described in the https://sourceware.org/binutils/docs-2.27/as/Altmacro.html "Expression results as strings You can write `%expr' to evaluate the expression expr and use the result as a string." expression assumptions: 1. '%' can only evaluate an absolute expression. 2. Altmacro '%' must be the first character of the evaluated expression. 3. If no '%' is located before the expression, a regular module operation is expected. 4. The result of Absolute Expressions can be only integer. Differential Revision: https://reviews.llvm.org/D32526 llvm-svn: 301797
* [AVR] Implement non-constant bit rotationsDylan McKay2017-05-013-1/+63
| | | | | | This lets us do bit rotations of variable amount. llvm-svn: 301794
* [GlobalISel][X86] Prioritize Tablegen-erated instruction selection. NFCIgor Breger2017-05-011-50/+8
| | | | | | | | | | | | | | | | Summary: Prioritizes Tablegen-erated instruction selection over C++ instruction selection. Remove G_ADD/G_SUB C++ selection - implemented by Tablegen. Reviewers: dsanders, zvi, guyblank Reviewed By: guyblank Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32677 llvm-svn: 301792
* [GlobalISel][X86] G_SEXT/G_ZEXT support.Igor Breger2017-05-011-0/+20
| | | | | | | | | | | | Reviewers: zvi, guyblank Reviewed By: zvi Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32591 llvm-svn: 301790
* [GlobalISel][X86] G_LOAD/G_STORE pointer selection support.Igor Breger2017-05-011-2/+2
| | | | | | | | | | | | | | Summary: [GlobalISel][X86] G_LOAD/G_STORE pointer selection support. Reviewers: zvi, guyblank Reviewed By: zvi, guyblank Subscribers: dberris, rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D32217 llvm-svn: 301788
* [AVR] Fix a bug so that we now emit R_AVR_16 fixups with the correct offsetDylan McKay2017-04-303-8/+9
| | | | | | | Before this, the LDS/STS instructions would have their opcodes overwritten while linking. llvm-svn: 301782
* [DAGCombiner] shrink/widen a vselect to match its condition operand size ↵Sanjay Patel2017-04-301-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | (PR14657) We discussed shrinking/widening of selects in IR in D26556, and I'll try to get back to that patch eventually. But I'm hoping that this transform is less iffy in the DAG where we can check legality of the select that we want to produce. A few things to note: 1. We can't wait until after legalization and do this generically because (at least in the x86 tests from PR14657), we'll have PACKSS and bitcasts in the pattern. 2. This might benefit more of the SSE codegen if we lifted the legal-or-custom requirement, but that requires a closer look to make sure we don't end up worse. 3. There's a 'vblendv' opportunity that we're missing that results in andn/and/or in some cases. That should be fixed next. 4. I'm assuming that AVX1 offers the worst of all worlds wrt uneven ISA support with multiple legal vector sizes, but if there are other targets like that, we should add more tests. 5. There's a codegen miracle in the multi-BB tests from PR14657 (the gcc auto-vectorization tests): despite IR that is terrible for the target, this patch allows us to generate the optimal loop code because something post-ISEL is hoisting the splat extends above the vector loops. Differential Revision: https://reviews.llvm.org/D32620 llvm-svn: 301781
* Rename isKnownNotFullPoison to programUndefinedIfPoison; NFCSanjoy Das2017-04-303-3/+4
| | | | | | | | | | | | | | | | | Summary: programUndefinedIfPoison makes more sense, given what the function does; and I'm about to add a function with a name similar to isKnownNotFullPoison (so do the rename to avoid confusion). Reviewers: broune, majnemer, bjarke.roune Reviewed By: broune Subscribers: mcrosier, llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D30444 llvm-svn: 301776
* Do not legalize large add with addc/adde, introduce addcarry and do it with ↵Amaury Sechet2017-04-308-37/+254
| | | | | | | | | | | | | | uaddo/addcarry Summary: As per discution on how to get better codegen an large int legalization, it became clear that using a glue for the carry was preventing several desirable optimizations. Passing the carry down as a value allow for more flexibility. Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer Subscribers: igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D29872 llvm-svn: 301775
* [APInt] Replace calls to setBits with more specific calls to setBitsFrom and ↵Craig Topper2017-04-302-4/+4
| | | | | | setLowBits where possible. llvm-svn: 301768
* [X86] Clear KnownBits instead of reconstructing it. NFCCraig Topper2017-04-301-1/+1
| | | | llvm-svn: 301767
* InstructionSimplify: Canonicalize shuffle operands. NFC-ish.Zvi Rackover2017-04-301-20/+29
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Apply canonicalization rules: 1. Input vectors with no elements selected from can be replaced with undef. 2. If only one input vector is constant it shall be the second one. This allows constant-folding to cover more ad-hoc simplifications that were in place and avoid duplication for RHS and LHS checks. There are more rules we may want to add in the future when we see a justification. e.g. mask elements that select undef elements can be replaced with undef. Reviewers: spatel, RKSimon, andreadb, davide Reviewed By: spatel, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32338 llvm-svn: 301766
* InstructionSimplify: One getShuffleMask() replacing multiple getMaskValue(). ↵Zvi Rackover2017-04-301-6/+9
| | | | | | | | | | | | | | | | NFC. Summary: This is a preparatory step for D32338. Reviewers: RKSimon, spatel Reviewed By: RKSimon, spatel Subscribers: spatel, llvm-commits Differential Revision: https://reviews.llvm.org/D32388 llvm-svn: 301765
* InstructionSimplify: Simplify a shuffle with a undef mask to undefZvi Rackover2017-04-301-0/+3
| | | | | | | | | | | | | | | | Summary: Following the discussion in pr32486, adding the simplification: shuffle %x, %y, undef -> undef Reviewers: spatel, RKSimon, andreadb, davide Reviewed By: spatel Subscribers: jroelofs, davide, llvm-commits Differential Revision: https://reviews.llvm.org/D32293 llvm-svn: 301764
* [mips] Emit R_MICROMIPS_TLS_GOTTPREL relocation for %gottprel in case of ↵Simon Atanasyan2017-04-304-1/+9
| | | | | | | | | | | microMIPS In case of microMIPS mode %gottprel operator should emit microMIPS relocation R_MICROMIPS_TLS_GOTTPREL, not R_MIPS_TLS_GOTTPREL. Differential Revision: http://reviews.llvm.org/D32617 llvm-svn: 301763
* [ConstantRange] Fix a couple cases where we were possibly throwing away an ↵Craig Topper2017-04-301-2/+2
| | | | | | | | APInt allocation we could reuse. NFC This uses setAllBits to replace getMaxValue and operator=(uint64_t) instead of constructing an APInt from uint64_t. llvm-svn: 301761
* Include <cstdio> in PrettyStackTrace.cpp, since it uses vsnprintf(3).Dimitry Andric2017-04-291-0/+1
| | | | llvm-svn: 301760
* [ConstantRange] Use APInt::getOneBitSet to shorten some code. NFCCraig Topper2017-04-291-5/+2
| | | | llvm-svn: 301753
* [ConstantRange] Replace getMaxValue+zext with getLowBitsSet. Replace ↵Craig Topper2017-04-291-3/+2
| | | | | | zero-init+setBit with getOneBitSet. NFC llvm-svn: 301752
* [ConstantRange] Use APInt::operator-= to remove temporary APInts.Craig Topper2017-04-291-4/+4
| | | | llvm-svn: 301751
* [globalisel][tablegen] Compute available feature bits correctly.Daniel Sanders2017-04-2911-46/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Predicate<> now has a field to indicate how often it must be recomputed. Currently, there are two frequencies, per-module (RecomputePerFunction==0) and per-function (RecomputePerFunction==1). Per-function predicates are currently recomputed more frequently than necessary since the only predicate in this category is cheap to test. Per-module predicates are now computed in getSubtargetImpl() while per-function predicates are computed in selectImpl(). Tablegen now manages the PredicateBitset internally. It should only be necessary to add the required includes. Also fixed a problem revealed by the test case where constrainSelectedInstRegOperands() would attempt to tie operands that BuildMI had already tied. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32491 llvm-svn: 301750
* [KnownBits] Add methods for determining if the known bits represent a ↵Craig Topper2017-04-293-54/+54
| | | | | | | | | | | | | | | | negative/nonnegative number and add methods for changing the negative/nonnegative state Summary: This patch adds isNegative, isNonNegative for querying whether the sign bit is known. It also adds makeNegative and makeNonNegative for controlling the sign bit. Reviewers: RKSimon, spatel, davide Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32651 llvm-svn: 301747
* [mips][FastISel] Fix a nullptr deference.Simon Dardis2017-04-291-1/+2
| | | | | | | r301392 introduced a potential nullptr deference causing compilation failures. llvm-svn: 301746
* [ConstantRange] Use ternary operator instead of 'if' to avoid copying an ↵Craig Topper2017-04-291-10/+4
| | | | | | APInt and then possibly copying over it. llvm-svn: 301741
* [ConstantRange] Add std::move to a bunch of places that pass local APInts to ↵Craig Topper2017-04-291-24/+25
| | | | | | | | ConstantRange constructor. The ConstantRange constructor takes APInt by value so without these moves we are making copies. llvm-svn: 301740
* [ConstantRange] Remove a temporary APInt I meant to delete in r300621. NFCCraig Topper2017-04-291-1/+0
| | | | llvm-svn: 301737
* [ConstantRange] Improve the efficiency of one of the ConstantRange constructors.Craig Topper2017-04-291-6/+3
| | | | | | | | | | We were default constructing the Lower/Upper APInts. Then creating min or max value, then doing a move assignment to Lower and copy assignment to upper. The copy assignment operator in particular has an out of line function call that has to examine whether or not a previous allocation exists that can be reused which of course it can't in this case. The new code creates the min/max value first, move constructs Lower from it then copy constructs Upper from Lower. This also seems to have convinced a self host build that this constructor can be inlined more readily into other methods in ConstantRange. llvm-svn: 301736
* AMDGPU: Fix copies from physical registers in SIFixSGPRCopiesMatt Arsenault2017-04-291-4/+9
| | | | | | | | | This would assert when there were multiple defs of a physical register. We just need to move all of the users of it. llvm-svn: 301730
* [llvm-pdbdump] Abstract some of the YAML/Raw printing code.Zachary Turner2017-04-296-9/+14
| | | | | | | | | There is a lot of duplicate code for printing line info between YAML and the raw output printer. This introduces a base class that can be shared between the two, and makes some minor cleanups in the process. llvm-svn: 301728
* [ObjCARC] Do not move a release between a call and aAkira Hatanaka2017-04-292-16/+33
| | | | | | | | | | | | | | | | | | | retainAutoreleasedReturnValue that retains the returned value. This commit fixes a bug in ARC optimizer where it moves a release between a call and a retainAutoreleasedReturnValue, causing the returned object to be released before the retainAutoreleasedReturnValue can retain it. This commit accomplishes that by doing a lookahead and checking whether the call prevents the release from moving upwards. In the long term, we should treat the region between the retainAutoreleasedReturnValue and the call as a critical section and disallow moving anything there (possibly using operand bundles). rdar://problem/20449878 llvm-svn: 301724
* [LoopUnswitch] Make DEBUG output more readable (part 2).Davide Italiano2017-04-291-1/+1
| | | | | | | | | I fixed my miscompile in r301722 and I hope I don't have to take a look at this code again now that Chandler has a new LoopUnswitch pass, but maybe this could be of use for somebody else in the meanwhile. llvm-svn: 301723
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