| Commit message (Collapse) | Author | Age | Files | Lines |
| |
|
|
| |
llvm-svn: 54315
|
| |
|
|
| |
llvm-svn: 54314
|
| |
|
|
| |
llvm-svn: 54313
|
| |
|
|
| |
llvm-svn: 54312
|
| |
|
|
|
|
|
|
| |
Added hi,lo registers to be used,def implicitly. This provides better handle of
instructions which use hi/lo.
Fixes a small BranchAnalysis bug
llvm-svn: 54274
|
| |
|
|
| |
llvm-svn: 54273
|
| |
|
|
| |
llvm-svn: 54266
|
| |
|
|
| |
llvm-svn: 54250
|
| |
|
|
|
|
|
|
| |
work with
the default legalizer.
llvm-svn: 54249
|
| |
|
|
|
|
|
|
| |
switches use the binary search algorithm) for
environments that don't support it. PPC64 JIT
is such an environment; turn the flag on for that.
llvm-svn: 54248
|
| |
|
|
| |
llvm-svn: 54239
|
| |
|
|
|
|
|
|
| |
access).
Added pattern to match bitconvert node.
Fixed MTC1 asm string bug.
llvm-svn: 54229
|
| |
|
|
|
|
| |
it isn't always visible to gdb.
llvm-svn: 54228
|
| |
|
|
|
|
| |
empty structs. This fixes PR2612.
llvm-svn: 54226
|
| |
|
|
|
|
| |
to Evan for pointing these out.
llvm-svn: 54225
|
| |
|
|
|
|
|
|
|
|
|
| |
subreg form on x86-64, to avoid the problem with x86-32
having GPRs that don't have 8-bit subregs.
Also, change several 16-bit instructions to use
equivalent 32-bit instructions. These have a smaller
encoding and avoid partial-register updates.
llvm-svn: 54223
|
| |
|
|
|
|
| |
remapped.
llvm-svn: 54218
|
| |
|
|
| |
llvm-svn: 54215
|
| |
|
|
| |
llvm-svn: 54214
|
| |
|
|
| |
llvm-svn: 54213
|
| |
|
|
| |
llvm-svn: 54212
|
| |
|
|
|
|
|
| |
to different address spaces. This alters the naming scheme for those
intrinsics, e.g., atomic.load.add.i32 => atomic.load.add.i32.p0i32
llvm-svn: 54195
|
| |
|
|
|
|
|
|
|
|
|
| |
time applying to the implicit comparison in smin expressions. The
correct way to transform an inequality into the opposite
inequality, either signed or unsigned, is with a not expression.
I looked through the SCEV code, and I don't think there are any more
occurrences of this issue.
llvm-svn: 54194
|
| |
|
|
| |
llvm-svn: 54186
|
| |
|
|
|
|
|
|
| |
are inputs to two-address instructions
that themselves define a range we already care about.
llvm-svn: 54185
|
| |
|
|
|
|
|
|
|
|
|
|
| |
SGT exit condition. Essentially, the correct way to flip an inequality
in 2's complement is the not operator, not the negation operator.
That said, the difference only affects cases involving INT_MIN.
Also, enhance the pre-test search logic to be a bit smarter about
inequalities flipped with a not operator, so it can eliminate the smax
from the iteration count for simple loops.
llvm-svn: 54184
|
| |
|
|
|
|
|
|
| |
need to merge over all liveranges in
the operand's interval that share the relevant value number, not just the range that immediately precedes the PHI.
llvm-svn: 54174
|
| |
|
|
| |
llvm-svn: 54173
|
| |
|
|
|
|
|
|
| |
to be marked invalid regardless of whether it is
a debug, an exception handling or (hopefully) a
GC label.
llvm-svn: 54172
|
| |
|
|
| |
llvm-svn: 54169
|
| |
|
|
| |
llvm-svn: 54168
|
| |
|
|
| |
llvm-svn: 54167
|
| |
|
|
|
|
|
| |
The CellSPU codegen is broken, but needs to be fixed before we can
put this back in.
llvm-svn: 54164
|
| |
|
|
|
|
| |
CodeGen & Clang work coming next.
llvm-svn: 54161
|
| |
|
|
|
|
|
|
| |
partially unroll a loop when fully unrolling would not fit under the threshold.
Patch by Mikael Lepistö.
llvm-svn: 54160
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
that says "unconditional loads from this argument are safe", we now keep track
of the safety per set of indices from which loads happen. This prevents
ArgPromotion from promoting loads that aren't really valid. As an added effect,
this will now disregard the the type of the indices passed to a GEP, so
"load GEP %A, i32 1" and "load GEP %A, i64 1" will result in a single argument,
not two.
This fixes PR2598, for which a testcase has been added as well.
llvm-svn: 54159
|
| |
|
|
|
|
| |
just Value*'s.
llvm-svn: 54157
|
| |
|
|
|
|
| |
FreeRangeHeader::getMinBlockSize(). Patch by Damien.
llvm-svn: 54152
|
| |
|
|
| |
llvm-svn: 54148
|
| |
|
|
|
|
|
|
| |
which is represented in codegen as an 'and' operation. This matches them
with movz instructions, instead of leaving them to be matched by and
instructions with an immediate field.
llvm-svn: 54147
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
a new ilist_node class, and remove them. Unlike alist_node,
ilist_node doesn't attempt to manage storage itself, so it avoids
the associated problems, including being opaque in gdb.
Adjust the Recycler class so that it doesn't depend on alist_node.
Also, change it to use explicit Size and Align parameters, allowing
it to work when the largest-sized node doesn't have the greatest
alignment requirement.
Change MachineInstr's MachineMemOperand list from a pool-backed
alist to a std::list for now.
llvm-svn: 54146
|
| |
|
|
| |
llvm-svn: 54144
|
| |
|
|
| |
llvm-svn: 54142
|
| |
|
|
|
|
| |
of operands should be -1 not 0.
llvm-svn: 54141
|
| |
|
|
|
|
|
| |
Fixed COMM asm directive usage.
ConstantPool using custom FourByteConstantSection.
llvm-svn: 54139
|
| |
|
|
| |
llvm-svn: 54136
|
| |
|
|
|
|
|
|
| |
loaded.
This fixes PR2599.
llvm-svn: 54133
|
| |
|
|
|
|
|
|
| |
circumstances we could end up remapping a dependee to the same instruction
that we're trying to remove. Handle this properly by just falling back to
a conservative solution.
llvm-svn: 54132
|
| |
|
|
| |
llvm-svn: 54131
|
| |
|
|
|
|
| |
the SelectionDAG's.
llvm-svn: 54129
|