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* [IRCE] Recognize loops with ne/eq latch conditionsMax Kazantsev2017-07-181-4/+54
| | | | | | | | | | In some particular cases eq/ne conditions can be turned into equivalent slt/sgt conditions. This patch teaches parseLoopStructure to handle some of these cases. Differential Revision: https://reviews.llvm.org/D35010 llvm-svn: 308264
* [Analysis] RemoveTotalMemInst counting in InstCount to avoid reading back ↵Craig Topper2017-07-181-8/+0
| | | | | | | | | | | | | | | | | | | | | other Statistic variables Summary: Previously, we counted TotalMemInst by reading certain instruction counters before and after calling visit and then finding the difference. But that wouldn't be thread safe if this same pass was being ran on multiple threads. This list of "memory instructions" doesn't make sense to me as it includes call/invoke and is missing atomics. This patch removes the counter all together. Reviewers: hfinkel, chandlerc, davide Reviewed By: davide Subscribers: davide, llvm-commits Differential Revision: https://reviews.llvm.org/D33608 llvm-svn: 308260
* [libFuzzer] improve -reduce_inputs=1: now only consider the unique features ↵Kostya Serebryany2017-07-184-26/+23
| | | | | | of very input (seems to work much better) llvm-svn: 308253
* [libFuzzer] disable fuzzer-flags.test on windows to fix the botsKostya Serebryany2017-07-181-0/+3
| | | | llvm-svn: 308246
* [DWARF] Modification of code for the verification of .debug_info section.Spyridoula Gravani2017-07-182-45/+85
| | | | | | | | | | | | | | | Summary: This patch modifies the handleDebugInfo() function so that we verify the contents of each unit in the .debug_info section only if its header has been successfully verified. This change will allow for more/different verification checks depending on the type of the unit since from dwarf5, the .debug_info section may consist of different types of units. Subscribers: aprantl Differential Revision: https://reviews.llvm.org/D35521 llvm-svn: 308245
* [PDB] Finish and simplify TPI hashingReid Kleckner2017-07-181-75/+53
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This removes the CVTypeVisitor updater and verifier classes. They were made dead by the minimal type dumping refactoring. Replace them with a single function that takes a type record and produces a hash. Call this from the minimal type dumper and compare the hash. I also noticed that the microsoft-pdb reference repository uses a basic CRC32 for records that aren't special. We already have an implementation of that CRC ready to use, because it's used in COFF for ICF. I'll make LLD call this hashing utility in a follow-up change. We might also consider using this same hash in type stream merging, so that we don't have to hash our records twice. Reviewers: inglorion, ruiu Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D35515 llvm-svn: 308240
* [codeview] Fix YAML for LF_TYPESERVER2 by hoisting PDB_UniqueIdReid Kleckner2017-07-1710-24/+51
| | | | | | | | | | | | | | | | | | Summary: We were treating the GUIDs in TypeServer2Record as strings, and the non-ASCII bytes in the GUID would not round-trip through YAML. We already had the PDB_UniqueId type portably represent a Windows GUID, but we need to hoist that up to the DebugInfo/CodeView library so that we can use it in the TypeServer2Record as well as in PDB parsing code. Reviewers: inglorion, amccarth Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D35495 llvm-svn: 308234
* AMDGPU: Annotate features from x work item/group IDs.Matt Arsenault2017-07-173-19/+48
| | | | | | | | This wasn't necessary before since they are always enabled for kernels, but this is necessary if they need to be forwarded to a callable function. llvm-svn: 308226
* [COFF, ARM64] Correct the data layout string for COFF ARM64 targetMandeep Singh Grang2017-07-171-1/+1
| | | | llvm-svn: 308223
* [codeview] Don't use the type visitor to merge typesReid Kleckner2017-07-171-71/+58
| | | | | | | | | | | | | | | Summary: This didn't do much to speed things up, but it implements a FIXME, and I think it's a nice simplification. We don't need the record kind switch. We're doing that ourselves. Reviewers: ruiu, inglorion Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D35496 llvm-svn: 308213
* [codeview] Remove TypeServerHandler and PDBTypeServerHandlerReid Kleckner2017-07-175-217/+19
| | | | | | | | | | | | | | | | | Summary: Instead of wiring these through the CVTypeVisitor interface, clients should inspect the CVTypeArray before visiting it and potentially load up the type server's TPI stream if they need it. No tests relied on this functionality because LLD was the only client. Reviewers: ruiu Subscribers: mgorny, hiraditya, zturner, llvm-commits Differential Revision: https://reviews.llvm.org/D35394 llvm-svn: 308212
* [AArch64][Falkor] Address some stylistic review comments. NFC.Geoff Berry2017-07-171-15/+15
| | | | llvm-svn: 308211
* [AArch64] Extend CallingConv::X86_64_Win64 to AArch64 as wellMartin Storsjo2017-07-1713-22/+40
| | | | | | | | | | | | Rename the enum value from X86_64_Win64 to plain Win64. The symbol exposed in the textual IR is changed from 'x86_64_win64cc' to 'win64cc', but the numeric value is kept, keeping support for old bitcode. Differential Revision: https://reviews.llvm.org/D34474 llvm-svn: 308208
* Revert "Restore with fix "[ThinLTO] Ensure we always select the same ↵Teresa Johnson2017-07-171-14/+4
| | | | | | | | | | | | | | | function copy to import"" This reverts commit r308114 (and follow on fixes to test). There is a linking failure in a ThinLTO bot: http://green.lab.llvm.org/green/job/clang-stage2-configure-Rthinlto_build/3663/ (and undefined reference). It seems like it must be a second order effect of the heuristic change I made, and may take some time to try to reproduce locally and track down. Therefore, reverting for now. llvm-svn: 308206
* Revert "[libFuzzer] Add a dependency on symbolizer from libFuzzer tests"George Karpenkov2017-07-171-1/+1
| | | | | | | | This reverts commit 546e006a023cccd0fd32afd442ab992d3515d4b8. Reverting until I can figure out llvm-symbolizer breakages on mac os. llvm-svn: 308202
* [SystemZ] Add support for IBM z14 processor (3/3)Ulrich Weigand2017-07-179-43/+211
| | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the new 128-bit vector float instructions of z14. Note that these instructions actually only operate on the f128 type, since only each 128-bit vector register can hold only one 128-bit float value. However, this is still preferable to the legacy 128-bit float instructions, since those operate on pairs of floating-point registers (so we can hold at most 8 values in registers), while the new instructions use single vector registers (so we hold up to 32 value in registers). Adding support includes: - Enabling the instructions for the assembler/disassembler. - CodeGen for the instructions. This includes allocating the f128 type now to the VR128BitRegClass instead of FP128BitRegClass. - Scheduler description support for the instructions. Note that for a small number of operations, we have no new vector instructions (like integer <-> 128-bit float conversions), and so we use the legacy instruction and then reformat the operand (i.e. copy between a pair of floating-point registers and a vector register). llvm-svn: 308196
* [SystemZ] Add support for IBM z14 processor (2/3)Ulrich Weigand2017-07-177-19/+247
| | | | | | | | | | | | | | This adds support for the new 32-bit vector float instructions of z14. This includes: - Enabling the instructions for the assembler/disassembler. - CodeGen for the instructions, including new LLVM intrinsics. - Scheduler description support for the instructions. - Update to the vector cost function calculations. In general, CodeGen support for the new v4f32 instructions closely matches support for the existing v2f64 instructions. llvm-svn: 308195
* [SystemZ] Add support for IBM z14 processor (1/3)Ulrich Weigand2017-07-1716-15/+2265
| | | | | | | | | | | | | | This patch series adds support for the IBM z14 processor. This part includes: - Basic support for the new processor and its features. - Support for new instructions (except vector 32-bit float and 128-bit float). - CodeGen for new instructions, including new LLVM intrinsics. - Scheduler description for the new processor. - Detection of z14 as host processor. Support for the new 32-bit vector float and 128-bit vector float instructions is provided by separate patches. llvm-svn: 308194
* [Hexagon] Remove custom lowering of loads of v4i16Krzysztof Parzyszek2017-07-173-83/+7
| | | | | | | The target-independent lowering works fine, except concatenating 32-bit words. Add a pattern to generate A2_combinew instead of 64-bit asl/or. llvm-svn: 308186
* Avoid store merge to f128 in context of noimpiccitfloat NFCI.Nirav Dave2017-07-171-0/+13
| | | | | | | | | Prevent store merge from merging stores into an invalid 128-bit store (realized as a f128 value in the context of the noimplicitfloat attribute). Previously, such stores are immediately split back into valid stores. llvm-svn: 308184
* [AMDGPU] CodeGen: check dst operand type to determine if omod is supported ↵Sam Kolton2017-07-176-17/+34
| | | | | | | | | | | | | | | | for VOP3 instructions Summary: Previously, CodeGen checked first src operand type to determine if omod is supported by instruction. This isn't correct for some instructions: e.g. V_CMP_EQ_F32 has floating-point src operands but desn't support omod. Changed .td files to check if dst operand instead of src operand. Reviewers: arsenm, vpykhtin Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D35350 llvm-svn: 308179
* [X86][AVX512] Add lowering of vXi32/vXi64 ISD::ROTL/ISD::ROTRSimon Pilgrim2017-07-172-3/+135
| | | | | | | | Add support for lowering to ISD::ROTL/ISD::ROTR, including rotate by immediate Differential Revision: https://reviews.llvm.org/D35463 llvm-svn: 308177
* [CodeGen] Add begin-end iterators to MachineInstrJaved Absar2017-07-171-3/+1
| | | | | | | | | Convert iteration over operands to range-loop. Reviewed by: @rovka, @echristo Differential Revision: https://reviews.llvm.org/D35419 llvm-svn: 308173
* [YAMLTraits] Add filename support to yaml::InputAlex Bradbury2017-07-171-0/+8
| | | | | | | | | | | | | | | | | | | Summary: The current yaml::Input constructor takes a StringRef of data as its first parameter, discarding any filename information that may have been present when a YAML file was opened. Add an alterate yaml::Input constructor that takes a MemoryBufferRef, which can have a filename associated with it. This leads to clearer diagnostic messages. Sponsored By: DARPA, AFRL Reviewed By: arphaman Differential Revision: https://reviews.llvm.org/D35398 Patch by: Jonathan Anderson (trombonehero) llvm-svn: 308172
* Remove unnecessary cast. NFCI.Simon Pilgrim2017-07-171-1/+1
| | | | llvm-svn: 308166
* [X86] Use MSVC's __cpuidex intrinsic instead of inline assembly in ↵Craig Topper2017-07-171-29/+10
| | | | | | | | | | getHostCPUName/getHostCPUFeatures for 32-bit builds too. We're already using it in 64-bit builds because 64-bit MSVC doesn't support inline assembly. As far as I know we were using inline assembly because at the time the code was added we had to support MSVC 2008 pre-SP1 while the intrinsic was added to MSVC in SP1. Now that we don't have to support that we should be able to just use the intrinsic. llvm-svn: 308163
* Analysis/MemorySSA.cpp: Prune unused "llvm/Transforms/Scalar.h".NAKAMURA Takumi2017-07-171-1/+0
| | | | llvm-svn: 308162
* IR/Core.cpp: Prune unused "llvm/Bitcode/BitcodeReader.h".NAKAMURA Takumi2017-07-171-1/+0
| | | | llvm-svn: 308161
* Support/Path.cpp: Prune unused "llvm/BinaryFormat".NAKAMURA Takumi2017-07-171-2/+0
| | | | llvm-svn: 308160
* [COFF, ARM64] Add initial relocation typesMandeep Singh Grang2017-07-172-12/+55
| | | | | | | | | | | | Reviewers: compnerd, ruiu, rnk Reviewed By: compnerd Subscribers: mstorsjo, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34857 llvm-svn: 308154
* [DAGCombiner] Recognise vector rotations with non-splat constantsAndrew Zhogin2017-07-161-13/+21
| | | | | | | | Fixes PR33691. Differential revision: https://reviews.llvm.org/D35381 llvm-svn: 308150
* AMDGPU: Fix amdgpu-flat-work-group-size/amdgpu-waves-per-eu checkKonstantin Zhuravlyov2017-07-161-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D35433 llvm-svn: 308147
* AMDGPU: Remove duplicate print outs from .AMDGPU.csdataKonstantin Zhuravlyov2017-07-161-9/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D35428 llvm-svn: 308145
* [InstCombine] Don't violate dominance when replacing instructions.Davide Italiano2017-07-161-7/+11
| | | | | | Differential Revision: https://reviews.llvm.org/D35376 llvm-svn: 308144
* Strip trailing whitespace. NFCISimon Pilgrim2017-07-161-64/+64
| | | | llvm-svn: 308143
* [X86] X86::CMOV to Branch heuristic based optimization.Amjad Aboud2017-07-164-0/+616
| | | | | | | | | | | | | | LLVM compiler recognizes opportunities to transform a branch into IR select instruction(s) - later it will be lowered into X86::CMOV instruction, assuming no other optimization eliminated the SelectInst. However, it is not always profitable to emit X86::CMOV instruction. For example, branch is preferable over an X86::CMOV instruction when: 1. Branch is well predicted 2. Condition operand is expensive, compared to True-value and the False-value operands In CodeGenPrepare pass there is a shallow optimization that tries to convert SelectInst into branch, but it is not enough. This commit, implements machine optimization pass that converts X86::CMOV instruction(s) into branch, based on a conservative heuristic. Differential Revision: https://reviews.llvm.org/D34769 llvm-svn: 308142
* [X86][SSE4A] Add EXTRQ/INSERTQ values to BTVER2 scheduling modelSimon Pilgrim2017-07-161-0/+16
| | | | llvm-svn: 308132
* fix typos in comments; NFCHiroshi Inoue2017-07-163-3/+3
| | | | llvm-svn: 308127
* fix typos in comments; NFCHiroshi Inoue2017-07-163-4/+4
| | | | llvm-svn: 308126
* [InstSimplify] Use commutable matchers to simplify some code. NFCCraig Topper2017-07-161-14/+7
| | | | llvm-svn: 308125
* [InstCombine] Move (0 - x) & 1 --> x & 1 to SimplifyDemandedUseBits.Craig Topper2017-07-162-7/+5
| | | | | | This removes a dedicated matcher and allows us to support more than just an AND masking the lower bit. llvm-svn: 308124
* Restore with fix "[ThinLTO] Ensure we always select the same function copy ↵Teresa Johnson2017-07-151-4/+14
| | | | | | | | | | to import" This restores r308078/r308079 with a fix for bot non-determinisim (make sure we run llvm-lto in single threaded mode so the debug output doesn't get interleaved). llvm-svn: 308114
* [IR] Implement ↵Craig Topper2017-07-151-19/+67
| | | | | | | | | | | | | | | | | | | Constant::isNegativeZeroValue/isZeroValue/isAllOnesValue/isOneValue/isMinSignedValue for ConstantDataVector without going through getElementAsConstant Summary: Currently these methods call ConstantDataVector::getSplatValue which uses getElementsAsConstant to create a Constant object representing the element value. This method incurs a map lookup to see if we already have created such a Constant before and if not allocates a new Constant object. This patch changes these methods to use getElementAsAPFloat and getElementAsInteger so we can just examine the data values directly. Reviewers: spatel, pcc, dexonsmith, bogner, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35040 llvm-svn: 308112
* [InstCombine] Improve the expansion in SimplifyUsingDistributiveLaws to ↵Craig Topper2017-07-152-38/+56
| | | | | | | | | | | | | | | | | | | handle cases where one side doesn't simplify, but the other side resolves to an identity value Summary: If one side simplifies to the identity value for inner opcode, we can replace the value with just the operation that can't be simplified. I've removed a couple now unneeded special cases in visitAnd and visitOr. There are probably other cases I missed. Reviewers: spatel, majnemer, hfinkel, dberlin Reviewed By: spatel Subscribers: grandinj, llvm-commits, spatel Differential Revision: https://reviews.llvm.org/D35451 llvm-svn: 308111
* Strip trailing whitespace. NFCISimon Pilgrim2017-07-151-1/+1
| | | | llvm-svn: 308108
* [CodeView] Dump BuildInfoSym and ProcSym type indicesReid Kleckner2017-07-151-1/+1
| | | | | | | I need to print the type index in hex so that I can match it in FileCheck for a test I'm writing. llvm-svn: 308107
* [InstCombine] improve (1 << x) & 1 --> zext(x == 0) foldingSanjay Patel2017-07-151-15/+13
| | | | | | | 1. Add a one-use check to prevent increasing instruction count. 2. Generalize the pattern matching to include vector types. llvm-svn: 308105
* [InstCombine] allow (0 - x) & 1 --> x & 1 for vectorsSanjay Patel2017-07-151-6/+5
| | | | llvm-svn: 308098
* [InstCombine] remove dead code/tests; NFCISanjay Patel2017-07-151-11/+0
| | | | | | | These patterns and tests were added to InstSimplify with: https://reviews.llvm.org/rL303004 llvm-svn: 308096
* Revert r308078 (and subsequent tweak in r308079) which introduces a testChandler Carruth2017-07-151-14/+4
| | | | | | | | | that appears to exhibit non-determinism and is flaking on the bots pretty consistently. r308078: [ThinLTO] Ensure we always select the same function copy to import r308079: Require asserts in new test that uses debug flag llvm-svn: 308095
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