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* [mips] Handle missing CondCodesStefan Maksimovic2018-08-221-0/+29
| | | | | | | | | | | | | | | | | | | | Add patterns for unhandled CondCode enumerables: SETEQ, SETGE, SETGT, SETLE, SETLT, SETNE. Stated at the ISD::CondCode enum declaration: `All of these (except for the 'always folded ops') should be handled for floating point.` Add patterns which use these nodes, same as corresponding 'ordered' CondCode nodes. Referring to 'Ordered means that neither operand is a QNAN' we assume it is safe to match ex. SETLT node to the same instruction as SETOLT. Differential Revision: https://reviews.llvm.org/D50757 llvm-svn: 340392
* [XRay] Refactor file header reading (NFC)Dean Michael Berris2018-08-223-64/+86
| | | | | | | | | | | | | | | | Summary: This patch moves out the definition of the XRay log file header from binary logs into its own header and implementation file. This is one part of the refactoring being done in D50441. Reviewers: eizan Subscribers: mgorny, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D51086 llvm-svn: 340389
* [AST] Fix a whitespace typo [NFC]Philip Reames2018-08-221-1/+1
| | | | llvm-svn: 340384
* [AST] Reorder code to reduce a future patch diff [NFC]Philip Reames2018-08-221-3/+3
| | | | llvm-svn: 340383
* [AST] Move a function definition into the cpp [NFC]Philip Reames2018-08-221-0/+12
| | | | llvm-svn: 340382
* [GuardWidening] Ignore guards with trivial conditionsMax Kazantsev2018-08-221-0/+6
| | | | | | | | | | | | Guard widening should not spend efforts on dealing with guards with trivial true/false conditions. Such guards can easily be eliminated by any further cleanup pass like instcombine. However we should not unconditionally delete them because it may be profitable to widen other conditions into such guards. Differential Revision: https://reviews.llvm.org/D50247 Reviewed By: fedor.sergeev llvm-svn: 340381
* [CodeGenPrepare] Set debug loc when widening a switch conditionVedant Kumar2018-08-221-0/+1
| | | | | | | Set a debug location on the cast instruction used to widen a switch condition. llvm-svn: 340379
* [Support][CachePruning] prune least recently accessed files firstBob Haarman2018-08-221-12/+35
| | | | | | | | | | | | | | | | | Summary: Before this change, pruning order was based on size. This changes it to be based on time of last use instead, preferring to keep recently used files and prune older ones. Reviewers: pcc, rnk, espindola Reviewed By: rnk Subscribers: emaste, arichardson, hiraditya, steven_wu, dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D51062 llvm-svn: 340374
* [WebAssembly] Fix typos in mem.grow/memory.grow opcodesHeejin Ahn2018-08-221-2/+2
| | | | | | This should be not 0x3f but 0x40. llvm-svn: 340373
* [WebAssembly] Change comments on SP writing back (NFC)Heejin Ahn2018-08-222-3/+5
| | | | | | | | | | | | Summary: We now write back not to memory but to __stack_pointer global. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51074 llvm-svn: 340372
* [CodeGenPrepare] Set debug locations when splitting selectsVedant Kumar2018-08-221-1/+5
| | | | | | | When splitting a select into a diamond, set debug locations on newly-created branch instructions and phi nodes. llvm-svn: 340371
* [CodeGenPrepare] Clean up dbg.value use-before-def as late as possibleVedant Kumar2018-08-211-5/+4
| | | | | | | | | | | CodeGenPrepare has a strategy for moving dbg.values so that a value's definition always dominates its debug users. This cleanup was happening too early (before certain CGP transforms were run), resulting in some dbg.value use-before-def errors. Perform this cleanup as late as possible to avoid use-before-def. llvm-svn: 340370
* [CodeGenPrepare] Scan past debug intrinsics to find select candidates (NFC)Vedant Kumar2018-08-211-3/+4
| | | | | | | | | | In optimizeSelectInst, when scanning for candidate selects to rewrite into branches, scan past debug intrinsics. This makes the debug-enabled and non-debug paths through optimizeSelectInst more congruent. NFC because every select is eventually visited either way. llvm-svn: 340368
* [CodeGenPrepare] Exit earlier when optimizing selects (NFC)Vedant Kumar2018-08-211-2/+5
| | | | | | | When optimizing for size, this allows optimizeSelectInst to skip a linear scan and exit early. llvm-svn: 340367
* Update MemorySSA in BasicBlockUtils.Alina Sbirlea2018-08-219-27/+50
| | | | | | | | | | | Summary: Extend BasicBlocksUtils to update MemorySSA. Subscribers: sanjoy, arsenm, nhaehnle, jlebar, Prazek, llvm-commits Differential Revision: https://reviews.llvm.org/D45300 llvm-svn: 340365
* [MS Demangler] Print template constructor args.Zachary Turner2018-08-211-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously if you had something like this: template<typename T> struct Foo { template<typename U> Foo(U); }; Foo F(3.7); this would mangle as ??$?0N@?$Foo@H@@QEAA@N@Z and this would be demangled as: undname: __cdecl Foo<int>::Foo<int><double>(double) llvm-undname: __cdecl Foo<int>::Foo<int>(double) Note the lack of the constructor template parameter in our demangling. This patch makes it so we print the constructor argument list. llvm-svn: 340356
* MachineScheduler: Refactor setPolicy() to limit computing remaining latencyTom Stellard2018-08-211-28/+60
| | | | | | | | | | | | | | | | | | | | | Summary: Computing the remaining latency can be very expensive especially on graphs of N nodes where the number of edges approaches N^2. This reduces the compile time of a pathological case with the AMDGPU backend from ~7.5 seconds to ~3 seconds. This test case has a basic block with 2655 stores, each with somewhere between 500 and 1500 successors and predecessors. Reviewers: atrick, MatzeB, airlied, mareko Reviewed By: mareko Subscribers: tpr, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D50486 llvm-svn: 340346
* [AMDGPU] Consider loads from flat addrspace to be potentially divergentScott Linder2018-08-211-4/+6
| | | | | | | | | In general we can't assume flat loads are uniform, and cases where we can prove they are should be handled through infer-address-spaces. Differential Revision: https://reviews.llvm.org/D50991 llvm-svn: 340343
* [MS Demangler] Fix a few more edge cases.Zachary Turner2018-08-211-18/+69
| | | | | | | | | | | | | | | | I found these by running llvm-undname over a couple hundred megabytes of object files generated as part of building chromium. The issues fixed in this patch are: 1) decltype-auto return types. 2) Indirect vtables (e.g. const A::`vftable'{for `B'}) 3) Pointers, references, and rvalue-references to member pointers. I have exactly one remaining symbol out of a few hundred MB of object files that produces a name we can't demangle, and it's related to back-referencing. llvm-svn: 340341
* [WebAssembly] Restore __stack_pointer after catch instructionsHeejin Ahn2018-08-216-6/+109
| | | | | | | | | | | | | | | Summary: After the stack is unwound due to a thrown exception, the `__stack_pointer` global can point to an invalid address. This inserts instructions that restore `__stack_pointer` global. Reviewers: jgravelle-google, dschuff Subscribers: mgorny, sbc100, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50980 llvm-svn: 340339
* [WebAssembly] v128.constThomas Lively2018-08-216-17/+141
| | | | | | | | | | | | | | | | Summary: This CL implements v128.const for each vector type. New operand types are added to ensure the vector contents can be serialized without LEB encoding. Tests are added for instruction selection, encoding, assembly and disassembly. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50873 llvm-svn: 340336
* [LICM] Refactor some AliasSetTracker code to get rid of new/deletes. NFCMarcello Maggioni2018-08-211-43/+33
| | | | | | Differential Revision: https://reviews.llvm.org/D51024 llvm-svn: 340333
* [CodeExtractor] Use 'normal destination' BB as insert point to store invoke ↵Florian Hahn2018-08-211-1/+9
| | | | | | | | | | | | | | | | | | | results. Currently CodeExtractor tries to use the next node after an invoke to place the store for the result of the invoke, if it is an out parameter of the region. This fails, as the invoke terminates the current BB. In that case, we can place the store in the 'normal destination' BB, as the result will only be available in that case. Reviewers: davidxl, davide, efriedma Reviewed By: davidxl Differential Revision: https://reviews.llvm.org/D51037 llvm-svn: 340331
* [WebAssembly] Don't make wasm cleanuppads into funclet entriesHeejin Ahn2018-08-211-3/+8
| | | | | | | | | | | | | | | Summary: Catchpads and cleanuppads are not funclet entries; they are only EH scope entries. We already dont't set `isEHFuncletEntry` for catchpads. This patch does the same thing for cleanuppads. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50654 llvm-svn: 340330
* [WebAssembly] Change writeSPToMemory to writeSPToGlobal (NFC)Heejin Ahn2018-08-211-4/+4
| | | | | | | | | | | | Summary: SP is now a __stack_pointer global and not a memory address anymore. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51046 llvm-svn: 340328
* [RegisterCoalescer] Use substPhysReg in reMaterializeTrivialDefBjorn Pettersson2018-08-211-1/+4
| | | | | | | | | | | | | | | | | | | Summary: When RegisterCoalescer::reMaterializeTrivialDef is substituting a register use in a DBG_VALUE instruction, and the old register is a subreg, and the new register is a physical register, then we need to use substPhysReg in order to extract the correct subreg. Reviewers: wmi, aprantl Reviewed By: wmi Subscribers: hiraditya, MatzeB, qcolombet, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D50844 llvm-svn: 340326
* [WebAssembly] Add isEHScopeReturn instruction propertyHeejin Ahn2018-08-213-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | Summary: So far, `isReturn` property is used to mean both a return instruction from a functon and the end of an EH scope, a scope that starts with a EH scope entry BB and ends with a catchret or a cleanupret instruction. Because WinEH uses funclets, all EH-scope-ending instructions are also real return instruction from a function. But for wasm, they only serve as the end marker of an EH scope but not a return instruction that exits a function. This mismatch caused incorrect prolog and epilog generation in wasm EH scopes. This patch fixes this. This patch is in the same vein with rL333045, which splits `MachineBasicBlock::isEHFuncletEntry` into `isEHFuncletEntry` and `isEHScopeEntry`. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50653 llvm-svn: 340325
* [InstCombine] Pull simple checks above a more complicated one. NFCICraig Topper2018-08-211-4/+2
| | | | | | I'm assuming its easier to make sure the RHS of an XOR is all ones than it is to check for the many select patterns we have. So lets check that first. Same with the one use check. llvm-svn: 340321
* [GVN] Assign new value number to calls reading memory, if there is no MemDep ↵Florian Hahn2018-08-211-13/+9
| | | | | | | | | | | | | | | | | | | | | | info. Currently we assign the same value number to two calls reading the same memory location if we do not have MemoryDependence info. Without MemDep Info we cannot guarantee that there is no store between the two calls, so we have to assign a new number to the second call. It also adds a new option EnableMemDep to enable/disable running MemoryDependenceAnalysis and also renamed NoLoads to NoMemDepAnalysis to be more explicit what it does. As it also impacts calls that read memory, NoLoads is a bit confusing. Reviewers: efriedma, sebpop, john.brawn, wmi Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D50893 llvm-svn: 340319
* [RegisterCoalscer] Manually remove leftover segments when commuting defKrzysztof Parzyszek2018-08-211-0/+12
| | | | | | | | | | | | | In removeCopyByCommutingDef, segments from the source live range are copied into (and merged with) the segments of the target live range. This is performed for all subranges of the source interval. It can happen that there will be subranges of the target interval that had no corresponding subranges in the source interval, and in such cases these subrages will not be updated. Since the copy being coalesced is about to be removed, these ranges need to be updated by removing the segments that are started by the copy. llvm-svn: 340318
* [NVPTX] Remove ftz variants of cvt with rounding modeBenjamin Kramer2018-08-211-36/+6
| | | | | | | | These do not exist in ptxas, it refuses to compile them. Differential Revision: https://reviews.llvm.org/D51042 llvm-svn: 340317
* Temporarily Revert "[PowerPC] Generate Power9 extswsli extend sign and shift ↵Eric Christopher2018-08-214-38/+3
| | | | | | | | immediate instruction" due to it causing a compiler crash on valid. This reverts commit r340016, testcase forthcoming. llvm-svn: 340315
* [AST] Remove notion of volatile from alias sets [NFCI]Philip Reames2018-08-212-27/+9
| | | | | | | | | | Volatility is not an aliasing property. We used to model volatile as if it had extremely conservative aliasing implications, but that hasn't been true for several years now. So, it doesn't make sense to be in AliasSet. It also turns out the code is entirely a noop. Outside of the AST code to update it, there was only one user: load store promotion in LICM. L/S promotion doesn't need the check since it walks all the users of the address anyway. It already checks each load or store via !isUnordered which causes us to bail for volatile accesses. (Look at the lines immediately following the two remove asserts.) There is the possibility of some small compile time impact here, but the only case which will get noticeably slower is a loop with a large number of loads and stores to the same address where only the last one we inspect is volatile. This is sufficiently rare it's not worth optimizing for.. llvm-svn: 340312
* Update DBG_VALUE register operand during LiveInterval operationsYury Delendik2018-08-211-11/+11
| | | | | | | | | | | | | | | | | | | Summary: Handling of DBG_VALUE in ConnectedVNInfoEqClasses::Distribute() was fixed in PR16110. However DBG_VALUE register operands are not getting updated. This patch properly resolves the value location. Reviewers: MatzeB, vsk Reviewed By: MatzeB Subscribers: kparzysz, thegameg, vsk, MatzeB, dschuff, sbc100, jgravelle-google, aheejin, sunfish, llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D48994 llvm-svn: 340310
* Revert "Revert rr340111 "[GISel]: Add Legalization/lowering code for bit ↵Aditya Nandakumar2018-08-211-1/+122
| | | | | | | | | | | | | | | counting operations"" This reverts commit d1341152d91398e9a882ba2ee924147ea2f9b589. This patch originally made use of Nested MachineIRBuilder buildInstr calls, and since order of argument processing is not well defined, the instructions were built slightly in a different order (still correct). I've removed the nested buildInstr calls to have a defined order now. Patch was tested by Mikael. llvm-svn: 340309
* [X86][SSE] Lower vXi8 general shifts to SSE shifts directly. NFCI.Simon Pilgrim2018-08-211-26/+17
| | | | | | Most of these shifts are extended to vXi16 so we don't gain anything from forcing another round of generic shift lowering - we know these extended cases are legal constant splat shifts. llvm-svn: 340307
* [BypassSlowDivision] Teach bypass slow division not to interfere with div by ↵Craig Topper2018-08-211-0/+9
| | | | | | | | | | | | | | constant where constants have been constant hoisted, but not moved from their basic block DAGCombiner doesn't pay attention to whether constants are opaque before doing the div by constant optimization. So BypassSlowDivision shouldn't introduce control flow that would make DAGCombiner unable to see an opaque constant. This can occur when a div and rem of the same constant are used in the same basic block. it will be hoisted, but not leave the block. Longer term we probably need to look into the X86 immediate cost model used by constant hoisting and maybe not mark div/rem immediates for hoisting at all. This fixes the case from PR38649. Differential Revision: https://reviews.llvm.org/D51000 llvm-svn: 340303
* [X86][SSE] Lower v8i16 general shifts to SSE shifts directly. NFCI.Simon Pilgrim2018-08-211-9/+9
| | | | | | We don't gain anything from forcing another round of generic shift lowering - we know these are legal constant splat shifts. llvm-svn: 340302
* [X86][SSE] Lower directly to SSE shifts in the BLEND(SHIFT, SHIFT) combine. ↵Simon Pilgrim2018-08-211-9/+13
| | | | | | | | NFCI. We don't gain anything from forcing another round of generic shift lowering - we know these are legal constant splat shifts. llvm-svn: 340300
* Try to fix bot build failureMatt Arsenault2018-08-211-1/+1
| | | | llvm-svn: 340296
* [AMDGPU] Support idot2 pattern.Farhana Aleen2018-08-212-0/+23
| | | | | | | | | | | | | | | | Summary: Transform add (mul ((i32)S0.x, (i32)S1.x), add( mul ((i32)S0.y, (i32)S1.y), (i32)S3) => i/udot2((v2i16)S0, (v2i16)S1, (i32)S3) Author: FarhanaAleen Reviewed By: arsenm Subscribers: llvm-commits, AMDGPU Differential Revision: https://reviews.llvm.org/D50024 llvm-svn: 340295
* AMDGPU: Partially move target handling code from clang to TargetParserMatt Arsenault2018-08-211-0/+147
| | | | | | | | | | | | | | | | | | | | A future change in clang necessitates access of this information from the driver, so move this into a common place. Try to mimic something resembling the API the other targets are using here. One thing I'm uncertain about is how to split amdgcn and r600 handling. Here I've mostly duplicated the functions for each, while keeping the same enums. I think this is a bit awkward for the features which don't matter for amdgcn. It's also a bit messy that this isn't a complete set of subtarget features. This is just the minimum set needed for the driver code. For example building the list of subtarget feature names is still in clang. llvm-svn: 340291
* [X86][SSE] Add helper function to convert to/between the SSE vector shift ↵Simon Pilgrim2018-08-211-36/+33
| | | | | | | | opcodes. NFCI. Also remove some more getOpcode calls from LowerShift when we already have Opc. llvm-svn: 340290
* [aarch64][mc] Don't lookup symbols when there is no symbol lookup callbackDaniel Sanders2018-08-211-0/+2
| | | | | | | | | | | | | | Summary: When run under llvm-mc-disassemble-fuzzer, there is no symbol lookup callback so tryAddingSymbolicOperand() must fail gracefully instead of crashing Reviewers: aemerson, javed.absar Reviewed By: aemerson Subscribers: lhames, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D51005 llvm-svn: 340287
* [InstSimplify] use isKnownNeverNaN to fold more fcmp ord/unoSanjay Patel2018-08-211-7/+5
| | | | | | | | | | | Remove duplicate tests from InstCombine that were added with D50582. I left negative tests there to verify that nothing in InstCombine tries to go overboard. If isKnownNeverNaN is improved to handle the FP binops or other cases, we should have coverage under InstSimplify, so we could remove more duplicate tests from InstCombine at that time. llvm-svn: 340279
* [LV] Vectorize loops where non-phi instructions used outside loopAnna Thomas2018-08-212-7/+36
| | | | | | | | | | | | | | | | | | | Summary: Follow up change to rL339703, where we now vectorize loops with non-phi instructions used outside the loop. Note that the cyclic dependency identification occurs when identifying reduction/induction vars. We also need to identify that we do not allow users where the PSCEV information within and outside the loop are different. This was the fix added in rL307837 for PR33706. Reviewers: Ayal, mkuper, fhahn Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D50778 llvm-svn: 340278
* [AMDGPU] Allow int types for MUBUF vdataTim Renouf2018-08-211-0/+20
| | | | | | | | | | | | | | | | | Summary: Previously the new llvm.amdgcn.raw/struct.buffer.load/store intrinsics only allowed float types for the data to be loaded or stored, which sometimes meant the frontend needed to generate a bitcast. In this, the new intrinsics copied the old buffer intrinsics. This commit extends the new intrinsics to allow int types as well. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D50315 Change-Id: I8202af2d036455553681dcbb3d7d32ae273f8f85 llvm-svn: 340270
* [AMDGPU] New buffer intrinsicsTim Renouf2018-08-217-179/+502
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This commit adds new intrinsics llvm.amdgcn.raw.buffer.load llvm.amdgcn.raw.buffer.load.format llvm.amdgcn.raw.buffer.load.format.d16 llvm.amdgcn.struct.buffer.load llvm.amdgcn.struct.buffer.load.format llvm.amdgcn.struct.buffer.load.format.d16 llvm.amdgcn.raw.buffer.store llvm.amdgcn.raw.buffer.store.format llvm.amdgcn.raw.buffer.store.format.d16 llvm.amdgcn.struct.buffer.store llvm.amdgcn.struct.buffer.store.format llvm.amdgcn.struct.buffer.store.format.d16 llvm.amdgcn.raw.buffer.atomic.* llvm.amdgcn.struct.buffer.atomic.* with the following changes from the llvm.amdgcn.buffer.* intrinsics: * there are separate raw and struct versions: raw does not have an index arg and sets idxen=0 in the instruction, and struct always sets idxen=1 in the instruction even if the index is 0, to allow for the fact that gfx9 does bounds checking differently depending on whether idxen is set; * there is a combined cachepolicy arg (glc+slc) * there are now only two offset args: one for the offset that is included in bounds checking and swizzling, to be split between the instruction's voffset and immoffset fields, and one for the offset that is excluded from bounds checking and swizzling, to go into the instruction's soffset field. The AMDISD::BUFFER_* SD nodes always have an index operand, all three offset operands, combined cachepolicy operand, and an extra idxen operand. The obsolescent llvm.amdgcn.buffer.* intrinsics continue to work. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D50306 Change-Id: If897ea7dc34fcbf4d5496e98cc99a934f62fc205 llvm-svn: 340269
* [AMDGPU] New tbuffer intrinsicsTim Renouf2018-08-217-104/+309
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This commit adds new intrinsics llvm.amdgcn.raw.tbuffer.load llvm.amdgcn.struct.tbuffer.load llvm.amdgcn.raw.tbuffer.store llvm.amdgcn.struct.tbuffer.store with the following changes from the llvm.amdgcn.tbuffer.* intrinsics: * there are separate raw and struct versions: raw does not have an index arg and sets idxen=0 in the instruction, and struct always sets idxen=1 in the instruction even if the index is 0, to allow for the fact that gfx9 does bounds checking differently depending on whether idxen is set; * there is a combined format arg (dfmt+nfmt) * there is a combined cachepolicy arg (glc+slc) * there are now only two offset args: one for the offset that is included in bounds checking and swizzling, to be split between the instruction's voffset and immoffset fields, and one for the offset that is excluded from bounds checking and swizzling, to go into the instruction's soffset field. The AMDISD::TBUFFER_* SD nodes always have an index operand, all three offset operands, combined format operand, combined cachepolicy operand, and an extra idxen operand. The tbuffer pseudo- and real instructions now also have a combined format operand. The obsolescent llvm.amdgcn.tbuffer.* and llvm.SI.tbuffer.store intrinsics continue to work. V2: Separate raw and struct intrinsics. V3: Moved extract_glc and extract_slc defs to a more sensible place. V4: Rebased on D49995. V5: Only two separate offset args instead of three. V6: Pseudo- and real instructions have joint format operand. V7: Restored optionality of dfmt and nfmt in assembler. V8: Addressed minor review comments. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D49026 Change-Id: If22ad77e349fac3a5d2f72dda53c010377d470d4 llvm-svn: 340268
* Change how finalizeBundle selects debug location for the BUNDLE instructionBjorn Pettersson2018-08-211-1/+11
| | | | | | | | | | | | | | | | | | | | | | Summary: Previously a BUNDLE instruction inherited the DebugLoc from the first instruction in the bundle, even if that DebugLoc had no DILocation. With this commit this is changed into selecting the first DebugLoc that has a DILocation, by searching among the bundled instructions. The idea is to reduce amount of bundles that are lacking debug locations. Reviewers: #debug-info, JDevlieghere Reviewed By: JDevlieghere Subscribers: JDevlieghere, mattd, llvm-commits Differential Revision: https://reviews.llvm.org/D50639 llvm-svn: 340267
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