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* Verifier: Change Assert to AssertDI.Adrian Prantl2017-03-061-3/+3
| | | | | | | This error can be recovered from by stripping debug info. This is NFC for +asserts builds. llvm-svn: 297072
* [ObjectYAML] NFC. Refactor DWARFYAML CompileUnit dump codeChris Bieneman2017-03-064-122/+324
| | | | | | | | | | | | Summary: This patch refactors the DWARFYAML code for dumping compile units to use a visitor pattern. Using this design will, in the future, enable the DWARF YAML code to perform analysis and mutations of the DWARF DIEs. An example of such mutations would be calculating the length of a compile unit and updating the CU's Length field before writing the DIE. This support will make it easier to craft or modify DWARF tests by hand. Reviewers: lhames Subscribers: mgorny, fhahn, jgosnell, aprantl, llvm-commits Differential Revision: https://reviews.llvm.org/D30357 llvm-svn: 297067
* AMDGPU/R600: Fix ALU clause markers use detectionJan Vesely2017-03-061-2/+5
| | | | | | | | also exit early on kill instead of redefinition. Differential Revision: https://reviews.llvm.org/D30230 llvm-svn: 297060
* [IfConversion] Only renormalize probabilities if branches are analyzableKrzysztof Parzyszek2017-03-061-2/+4
| | | | | | | | | | | If a block has non-analyzable branches, the listed successors don't need to add up to one. For example, if a block has a conditional tail call, that tail call will not have a corresponding successor in the successor list, but will still be a possible branch. Differential Revision: https://reviews.llvm.org/D30556 llvm-svn: 297054
* [InstSimplify] refactor related div/rem folds; NFCISanjay Patel2017-03-061-47/+37
| | | | llvm-svn: 297052
* GlobalISel: don't emit degenerate G_INSERT instructions.Tim Northover2017-03-061-0/+25
| | | | | | | | | | | Before, we were producing G_INSERT instructions that were actually closer to a cast or even a COPY when both input and output sizes are the same. This doesn't really make sense and means that everything interpreting a G_INSERT also has to handle all these kinds of casts. So now we detect these degenerate cases and emit real casts instead. llvm-svn: 297051
* NewGVN: Remove DebugUnknownExprs, just mark the instructions as unusedDaniel Berlin2017-03-061-7/+3
| | | | llvm-svn: 297047
* NewGVN: Only call isInstructionTrivially dead once per instruction.Daniel Berlin2017-03-061-9/+10
| | | | llvm-svn: 297046
* [X86] Fix arg copy elision for illegal typesReid Kleckner2017-03-061-37/+33
| | | | | | | | | | | Use the store size of the argument type, which will be a byte-sized quantity, rather than dividing the size in bits by 8. Fixes PR32136 and re-enables copy elision from i64 arguments. Reverts the workaround in from r296950. llvm-svn: 297045
* GlobalISel: add buildUndef method to MachineIRBuilder. NFC.Tim Northover2017-03-062-1/+5
| | | | llvm-svn: 297044
* GlobalISel: refactor legalization of G_INSERT.Tim Northover2017-03-061-37/+23
| | | | | | | | Now that G_INSERT instructions can only insert one register, this code was overly general. In another direction it didn't handle registers that crossed split boundaries properly, which needed to be fixed. llvm-svn: 297042
* Remove the sample pgo annotation heuristic that uses call count to annotate ↵Dehao Chen2017-03-061-5/+3
| | | | | | | | | | | | | | | | basic block count. Summary: We do not need that special handling because the debug info is more accurate now. Performance testing shows no regression on google internal benchmarks. Reviewers: davidxl, aprantl Reviewed By: aprantl Subscribers: llvm-commits, aprantl Differential Revision: https://reviews.llvm.org/D30658 llvm-svn: 297038
* [Hexagon] Early-if-convert branches that may exit the loopKrzysztof Parzyszek2017-03-061-63/+106
| | | | | | | | | | | | | | | | Merge the tail block into the loop in cases where the main loop body exits early, subject to profitability constraints. This will coalesce the loop body into fewer blocks. For example: loop: loop: // loop body // loop body if (...) jump exit --> // more body more: if (...) jump exit // more body jump loop jump loop llvm-svn: 297033
* [Hexagon] Mark dead defs as <dead> in expand-condsetsKrzysztof Parzyszek2017-03-061-12/+28
| | | | | | | | | The code in updateDeadFlags removed unnecessary <dead> flags, but there can be cases where such a flag is not set, and yet a register has become dead. For example, if a mux with identical inputs is replaced with a COPY, the predicate register may no longer be used after that. llvm-svn: 297032
* [Hexagon] Pick a dot-old instruction that matches the architectureKrzysztof Parzyszek2017-03-063-4/+25
| | | | llvm-svn: 297031
* [InstSimplify] remove misleading comments; NFCSanjay Patel2017-03-061-2/+2
| | | | | | Div/rem-of-0 does not cause faults/undef (not the same as div/rem-by-0). llvm-svn: 297029
* [DAGCombiner] simplify div/rem-by-0Sanjay Patel2017-03-061-1/+10
| | | | | | | | | | | | | | | | | Refactoring of duplicated code and more fixes to follow. This is motivated by the post-commit comments for r296699: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20170306/435182.html Ie, we can crash if we're missing obvious simplifications like this that exist in the IR simplifier or if these occur later than expected. The x86 change for non-splat division shows a potential opportunity to improve vector codegen: we assumed that since only one lane had meaningful results, we should do the math in scalar. But that means moving back and forth from vector registers. llvm-svn: 297026
* Silence a warning "hiding virtual function".Vassil Vassilev2017-03-061-0/+1
| | | | llvm-svn: 297018
* [BasicBlockUtils] Check for nullptr before updating LoopInfo.Michael Kruse2017-03-061-3/+4
| | | | | | | | | | | | | | | | LoopInfo::getLoopFor returns nullptr if a BB is not in a loop and only then can the loop be updated to contain the newly created BBs. Add the missing nullptr check to SplitBlockAndInsertIfThen. Within LLVM, the only user of this function that also passes a LoopInfo to be updated is InnerLoopVectorizer::predicateInstructions(). As the method's name implies, the BB operataten on will always be within a loop, but out-of-tree users may also use it differently (here: Polly). All other uses of LoopInfo::getLoopFor in the file properly check its return value for nullptr. llvm-svn: 297016
* [DAG] fix formatting; NFCSanjay Patel2017-03-061-2/+1
| | | | llvm-svn: 297015
* [DAG] fix typo in comment; NFCSanjay Patel2017-03-061-1/+1
| | | | llvm-svn: 297011
* [PowerPC] Fix failure with STBRX when store is narrower than the bswapNemanja Ivanovic2017-03-061-2/+5
| | | | | | | | | | | Fixes a crash caused by r296811 by truncating the input of the STBRX node when the bswap is wider than i32. Fixes https://bugs.llvm.org/show_bug.cgi?id=32140 Differential Revision: https://reviews.llvm.org/D30615 llvm-svn: 297001
* [XRay] Allow logging the first argument of a function call.Dean Michael Berris2017-03-061-0/+3
| | | | | | | | | | | | | | | | | | | Summary: Functions with the "xray-log-args" attribute will have a special XRay sled kind emitted, for compiler-rt to copy any call arguments to your logging handler. For practical and performance reasons, only the first argument is supported, and only up to 64 bits. Reviewers: dberris Reviewed By: dberris Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29702 llvm-svn: 296998
* [SCEV] Decrease the recursion threshold for CompareValueComplexitySanjoy Das2017-03-051-6/+11
| | | | | | | | | | Fixes PR32142. r287232 accidentally increased the recursion threshold for CompareValueComplexity from 2 to 32. This change reverses that change by introducing a separate flag for CompareValueComplexity's threshold. llvm-svn: 296992
* [SelectionDAG] Fix vector splitting for *_EXTEND_VECTOR_INREG instructionsSimon Pilgrim2017-03-051-1/+6
| | | | | | Found by fuzz testing after rL296985 landed llvm-svn: 296989
* [X86] Silence GCC enum compare warning.Benjamin Kramer2017-03-051-2/+2
| | | | | | | | X86ISelLowering.cpp:26506:36: error: enumeral mismatch in conditional expression: 'llvm::X86ISD::NodeType' vs 'llvm::ISD::NodeType' [-Werror=enum-compare] llvm-svn: 296986
* [X86][SSE] Lower 128-bit vectors to SIGN/ZERO_EXTEND_VECTOR_IN_REG opsSimon Pilgrim2017-03-054-93/+136
| | | | | | | | | | | | As described on PR31712, we miss a variety of legalization combines because we lower these to X86ISD::VSEXT/VZEXT despite them having the same functionality. This patch makes 128-bit (SSE41) SIGN/ZERO_EXTEND_VECTOR_IN_REG ops legal, adds the necessary tablegen plumbing and uses a helper 'getExtendInVec' to decide when to use SIGN/ZERO_EXTEND_VECTOR_IN_REG or VSEXT/VZEXT. We're missing a couple of shuffle combines that will be added in a future patch for review. Later patches can then support the AVX2 cases as a mixture of SIGN/ZERO_EXTEND and SIGN/ZERO_EXTEND_VECTOR_IN_REG, and then finally deal with the AVX512 cases. Differential Revision: https://reviews.llvm.org/D30549 llvm-svn: 296985
* [SimplifyCFG] Use APInt::operator| instead of APInt::Or. NFCCraig Topper2017-03-051-1/+1
| | | | | | I'm looking to improve operator| to support rvalue references and may remove APInt::Or. llvm-svn: 296982
* [DAGCombine] Use APInt::operator|(uint64_t) instead of creating a temporary ↵Craig Topper2017-03-051-6/+6
| | | | | | | | APInt and calling APInt::Or. NFC This is more efficient by itself. But this is prep for a future patch that may remove APInt::Or while making operator| support rvalue references similar to add/sub. llvm-svn: 296981
* [x86] don't require a zext when forming ADC/SBBSanjay Patel2017-03-041-24/+29
| | | | | | | | | | | | | The larger goal is to move the ADC/SBB transforms currently in combineX86SetCC() to combineAddOrSubToADCOrSBB() because we're creating ADC/SBB in lots of places where we shouldn't. This was intended to be an NFC change, but avx-512 has something strange going on. It doesn't seem like any of the affected tests should really be using SET+TEST or ADC; a simple ADD could replace several instructions. But that's another bug... llvm-svn: 296978
* [DAGCombiner] allow transforming (select Cond, C +/- 1, C) to (add(ext Cond), C)Sanjay Patel2017-03-043-2/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | select Cond, C +/- 1, C --> add(ext Cond), C -- with a target hook. This is part of the ongoing process to obsolete D24480. The motivation is to canonicalize to select IR in InstCombine whenever possible, so we need to have a way to undo that easily in codegen. PowerPC is an obvious winner for this kind of transform because it has fast and complete bit-twiddling abilities but generally lousy conditional execution perf (although this might have changed in recent implementations). x86 also sees some wins, but the effect is limited because these transforms already mostly exist in its target-specific combineSelectOfTwoConstants(). The fact that we see any x86 changes just shows that that code is a mess of special-case holes. We may be able to remove some of that logic now. My guess is that other targets will want to enable this hook for most cases. The likely follow-ups would be to add value type and/or the constants themselves as parameters for the hook. As the tests in select_const.ll show, we can transform any select-of-constants to math/logic, but the general transform for any 2 constants needs one more instruction (multiply or 'and'). ARM is one target that I think may not want this for most cases. I see infinite loops there because it wants to use selects to enable conditionally executed instructions. Differential Revision: https://reviews.llvm.org/D30537 llvm-svn: 296977
* Try to fix thread name truncation on non-Windows.Zachary Turner2017-03-043-7/+16
| | | | llvm-svn: 296976
* Improve the Threading code on NetBSDKamil Rytarowski2017-03-041-5/+2
| | | | | | | | Do not include <sys/user.h> on NetBSD. It's dead file and will be removed. No need to include <sys/sysctl.h> in this code context on NetBSD. llvm-svn: 296973
* Truncate thread names if they're too long.Zachary Turner2017-03-042-3/+29
| | | | llvm-svn: 296972
* DebugCounter: Initialize skip to 0, not -1Daniel Berlin2017-03-041-2/+2
| | | | llvm-svn: 296971
* [X86][SSE] Enable post-legalize vXi64 shuffle combining on 32-bit targetsSimon Pilgrim2017-03-041-5/+0
| | | | | | | | Long ago (2010 according to svn blame), combineShuffle probably needed to prevent the accidental creation of illegal i64 types but there doesn't appear to be any combines that can cause this any more as they all have their own legality checks. Differential Revision: https://reviews.llvm.org/D30213 llvm-svn: 296966
* [legalize-types] Remove stale entries from SoftenedFloats.Florian Hahn2017-03-041-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Summary: When replacing a SDValue, we should remove the replaced value from SoftenedFloats (and possibly the other maps as well?). When we revisit a Node because it needs analyzing again, we have to remove all result values from SoftenedFloats (and possibly other maps?). This fixes the fp128 test failures with expensive checks for X86. I think we probably should also remove the values from the other maps (PromotedIntegers and so on), let me know what you think. Reviewers: baldrick, bogner, davidxl, ab, arsenm, pirama, chh, RKSimon Reviewed By: chh Subscribers: danalbert, wdng, srhines, hfinkel, sepavloff, llvm-commits Differential Revision: https://reviews.llvm.org/D29265 llvm-svn: 296964
* Set option enabling LSR alternative way to resolve complex solution to false.Evgeny Stupachenko2017-03-041-1/+1
| | | | | | | Differential Revision: http://reviews.llvm.org/D29862 From: Evgeny Stupachenko <evstupac@gmail.com> llvm-svn: 296959
* X86ISelLowering: Only perform copy elision on legal types.Matthias Braun2017-03-041-33/+37
| | | | | | | | | This fixes cases where i1 types were not properly legalized yet and lead to the creating of 0-sized stack slots. This fixes http://llvm.org/PR32136 llvm-svn: 296950
* Fix build.Peter Collingbourne2017-03-041-1/+1
| | | | llvm-svn: 296949
* WholeProgramDevirt: Implement exporting for uniform ret val opt.Peter Collingbourne2017-03-041-6/+19
| | | | | | Differential Revision: https://reviews.llvm.org/D29846 llvm-svn: 296948
* WholeProgramDevirt: Implement exporting for single-impl devirtualization.Peter Collingbourne2017-03-041-6/+54
| | | | | | Differential Revision: https://reviews.llvm.org/D29811 llvm-svn: 296945
* WholeProgramDevirt: Add any unsuccessful llvm.type.checked.load ↵Peter Collingbourne2017-03-041-12/+88
| | | | | | | | | | | | | devirtualizations to the list of llvm.type.test users. Any unsuccessful llvm.type.checked.load devirtualizations will be translated into uses of llvm.type.test, so we need to add the resulting llvm.type.test intrinsics to the function summaries so that the LowerTypeTests pass will export them. Differential Revision: https://reviews.llvm.org/D29808 llvm-svn: 296939
* NewGVN: Be consistent in what order we compare operands for swapping.Daniel Berlin2017-03-041-2/+2
| | | | | | NFC. llvm-svn: 296935
* [MISched] Remove unused arguments. NFC.Eli Friedman2017-03-041-4/+2
| | | | llvm-svn: 296934
* [x86] check for commuted add pattern to find ADC/SBBSanjay Patel2017-03-041-4/+11
| | | | llvm-svn: 296933
* RegAllocGreedy: Follow-up to r296722Matthias Braun2017-03-031-1/+5
| | | | | | | | | We can now end up in situations where we initiate LiveIntervalUnion queries with different SubRanges against the same register unit, so the assert() no longer holds in all cases. Just recalculate now when we know the cache is out of date. llvm-svn: 296928
* GlobalISel: constrain G_INSERT to inserting just one value per instruction.Tim Northover2017-03-032-3/+11
| | | | | | | It's much easier to reason about single-value inserts and no-one was actually using the variadic variants before. llvm-svn: 296923
* GlobalISel: add merge/unmerge nodes for legalization.Tim Northover2017-03-034-19/+80
| | | | | | | | | | | | | | These are simplified variants of the current G_SEQUENCE and G_EXTRACT, which assume the individual parts will be contiguous, homogeneous, and occupy the entirity of the larger register. This makes reasoning about them much easer since you only have to look at the first register being merged and the result to know what the instruction is doing. I intend to gradually replace all uses of the more complicated sequence/extract with these (or single-element insert/extracts), and then remove the older variants. For now we start with legalization. llvm-svn: 296921
* [x86] refactor combineAddOrSubToADCOrSBB(); NFCISanjay Patel2017-03-031-21/+25
| | | | | | | | | | | | The comments were wrong, and this is not an obvious transform. This hopefully makes it clearer that we're missing the commuted patterns for adds. It's less clear that this is actually a good transform for all micro-arch. This is prep work for trying to clean up the current adc/sbb codegen because it's definitely not happening optimally. llvm-svn: 296918
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