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* Clarify HowFarToZero computation when the step is a positive power of two. ↵Mark Heffernan2014-12-151-8/+13
| | | | | | Functionally this should be identical to the existing code except for the case where Step is maximally negative (eg, INT_MIN). We now punt in that one corner case to make reasoning about the code easier. llvm-svn: 224274
* [Hexagon] Adding misc multiply encodings and tests.Colin LeMahieu2014-12-151-0/+48
| | | | llvm-svn: 224273
* LiveRangeCalc: Rewrite subrange calculationMatthias Braun2014-12-153-242/+152
| | | | | | | | | This changes subrange calculation to calculate subranges sequentially instead of in parallel. The code is easier to understand that way and addresses the code review issues raised about LiveOutData being hard to understand/needing more comments by removing them :) llvm-svn: 224272
* [Hexagon] Adding doubleworld accumulating multiplies of halfwords.Colin LeMahieu2014-12-151-0/+74
| | | | llvm-svn: 224267
* [Hexagon] Adding accumulating half word multiplies.Colin LeMahieu2014-12-151-0/+105
| | | | llvm-svn: 224266
* [Hexagon] Adding multiply with rnd/sat/rndsatColin LeMahieu2014-12-151-0/+46
| | | | llvm-svn: 224265
* LiveRangeCalc: use more range based for loops; NFCMatthias Braun2014-12-151-20/+18
| | | | llvm-svn: 224263
* [Hexagon] Adding encoding bits for halfword multiplies.Colin LeMahieu2014-12-151-0/+39
| | | | llvm-svn: 224261
* [X86] Also pretty-print shuffle mask for INSERTPS rm variants.Ahmed Bougacha2014-12-151-3/+7
| | | | llvm-svn: 224260
* IR: Make metadata typeless in assemblyDuncan P. N. Exon Smith2014-12-153-80/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that `Metadata` is typeless, reflect that in the assembly. These are the matching assembly changes for the metadata/value split in r223802. - Only use the `metadata` type when referencing metadata from a call intrinsic -- i.e., only when it's used as a `Value`. - Stop pretending that `ValueAsMetadata` is wrapped in an `MDNode` when referencing it from call intrinsics. So, assembly like this: define @foo(i32 %v) { call void @llvm.foo(metadata !{i32 %v}, metadata !0) call void @llvm.foo(metadata !{i32 7}, metadata !0) call void @llvm.foo(metadata !1, metadata !0) call void @llvm.foo(metadata !3, metadata !0) call void @llvm.foo(metadata !{metadata !3}, metadata !0) ret void, !bar !2 } !0 = metadata !{metadata !2} !1 = metadata !{i32* @global} !2 = metadata !{metadata !3} !3 = metadata !{} turns into this: define @foo(i32 %v) { call void @llvm.foo(metadata i32 %v, metadata !0) call void @llvm.foo(metadata i32 7, metadata !0) call void @llvm.foo(metadata i32* @global, metadata !0) call void @llvm.foo(metadata !3, metadata !0) call void @llvm.foo(metadata !{!3}, metadata !0) ret void, !bar !2 } !0 = !{!2} !1 = !{i32* @global} !2 = !{!3} !3 = !{} I wrote an upgrade script that handled almost all of the tests in llvm and many of the tests in cfe (even handling many `CHECK` lines). I've attached it (or will attach it in a moment if you're speedy) to PR21532 to help everyone update their out-of-tree testcases. This is part of PR21532. llvm-svn: 224257
* Silence more static analyzer warnings.Michael Ilseman2014-12-1510-10/+32
| | | | | | | | Add in definedness checks for shift operators, null checks when pointers are assumed by the code to be non-null, and explicit unreachables. llvm-svn: 224255
* Add disassembler tests for mips3 platform. There are no functional changes.Vladimir Medic2014-12-151-1/+2
| | | | llvm-svn: 224253
* Changing a cast from unsigned to uint64_t, should be NFC in practice.Aaron Ballman2014-12-151-1/+1
| | | | llvm-svn: 224249
* Sink store based on alias analysisElena Demikhovsky2014-12-153-51/+48
| | | | | | | | | | | | - by Ella Bolshinsky The alias analysis is used define whether the given instruction is a barrier for store sinking. For 2 identical stores, following instructions are checked in the both basic blocks, to determine whether they are sinking barriers. http://reviews.llvm.org/D6420 llvm-svn: 224247
* [X86] Break false dependencies before partial register updates when the ↵Michael Kuperstein2014-12-151-0/+20
| | | | | | | | | | source operand is in memory Adds the various "rm" instruction variants into the list of instructions that have a partial register update. Also adds all variants of SQRTSD that were missing in the original list. Differential Revision: http://reviews.llvm.org/D6620 llvm-svn: 224246
* AVX-512: Added EXPAND instructions and intrinsics.Elena Demikhovsky2014-12-154-15/+150
| | | | llvm-svn: 224241
* Fix line mapping information in LLVM JIT profiling with VtuneAlexey Bataev2014-12-151-0/+12
| | | | | | | | The line mapping information for dynamic code is reported incorrectly. It causes VTune to map LLVM generated code to source lines incorrectly. This patch fix this issue. Patch by Denis Pravdin. Differential Revision: http://reviews.llvm.org/D6603 llvm-svn: 224229
* ThreadLocal: Move Unix-specific code out of Support/ThreadLocal.cppDavid Majnemer2014-12-152-45/+43
| | | | | | Just a cleanup, no functionality change is intended. llvm-svn: 224227
* ThreadLocal: Return a mutable pointer if templated with a non-const typeDavid Majnemer2014-12-153-4/+4
| | | | | | | It makes more sense for ThreadLocal<const T>::get to return a const T* and ThreadLocal<T>::get to return a T*. llvm-svn: 224225
* Loop Vectorizer minor changes in the code - Elena Demikhovsky2014-12-143-12/+12
| | | | | | | | some comments, function names, identation. Reviewed here: http://reviews.llvm.org/D6527 llvm-svn: 224218
* APInt: udivrem should use machine instructions for single-word APIntsDavid Majnemer2014-12-141-0/+12
| | | | | | | | This mirrors the behavior of APInt::udiv and APInt::urem. Some architectures, like X86, have a single instruction which can compute both division and remainder. llvm-svn: 224217
* ScalarEvolution: Remove SCEVUDivision, it's unusedDavid Majnemer2014-12-141-93/+26
| | | | | | This is just a code simplification, no functionality change is intended. llvm-svn: 224216
* [PowerPC] Handle cmp op promotion for SELECT[_CC] nodes in ↵Hal Finkel2014-12-141-18/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PPCTL::DAGCombineExtBoolTrunc PPCTargetLowering::DAGCombineExtBoolTrunc contains logic to remove unwanted truncations and extensions when dealing with nodes of the form: zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...) There was a FIXME in the implementation (now removed) regarding the fact that the function would abort the transformations if any of the non-output operands of a SELECT or SELECT_CC node would need to be promoted (because they were also output operands, for example). As a result, we continued to generate unnecessary zero-extends for code such as this: unsigned foo(unsigned a, unsigned b) { return (a <= b) ? a : b; } which would produce: cmplw 0, 3, 4 isel 3, 4, 3, 1 rldicl 3, 3, 0, 32 blr and now we produce: cmplw 0, 3, 4 isel 3, 4, 3, 1 blr which is better in the obvious way. llvm-svn: 224213
* Reapply "[ARM] Combine base-updating/post-incrementing vector load/stores."Ahmed Bougacha2014-12-131-6/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | r223862 tried to also combine base-updating load/stores. r224198 reverted it, as "it created a regression on the test-suite on test MultiSource/Benchmarks/Ptrdist/anagram by scrambling the order in which the words are shown." Reapply, with a fix to ignore non-normal load/stores. Truncstores are handled elsewhere (you can actually write a pattern for those, whereas for postinc loads you can't, since they return two values), but it should be possible to also combine extloads base updates, by checking that the memory (rather than result) type is of the same size as the addend. Original commit message: We used to only combine intrinsics, and turn them into VLD1_UPD/VST1_UPD when the base pointer is incremented after the load/store. We can do the same thing for generic load/stores. Note that we can only combine the first load/store+adds pair in a sequence (as might be generated for a v16f32 load for instance), because other combines turn the base pointer addition chain (each computing the address of the next load, from the address of the last load) into independent additions (common base pointer + this load's offset). Differential Revision: http://reviews.llvm.org/D6585 llvm-svn: 224203
* Revert "[ARM] Combine base-updating/post-incrementing vector load/stores."Renato Golin2014-12-131-38/+6
| | | | | | | | | This reverts commit r223862, as it created a regression on the test-suite on test MultiSource/Benchmarks/Ptrdist/anagram by scrambling the order in which the words are shown. We'll investigate the issue and re-apply when safe. llvm-svn: 224198
* Silencing a -Wsign-compare warning; NFC.Aaron Ballman2014-12-131-1/+2
| | | | llvm-svn: 224195
* Rename argument strings of codegen passes to avoid collisions with command lineAkira Hatanaka2014-12-133-4/+4
| | | | | | | | | | | | | | | | | | | | options. This commit changes the command line arguments (PassInfo::PassArgument) of two passes, MachineFunctionPrinter and MachineScheduler, to avoid collisions with command line options that have the same argument strings. This bug manifests when the PassList construct (defined in opt.cpp) is used in a tool that links with codegen passes. To reproduce the bug, paste the following lines into llc.cpp and run llc. #include "llvm/IR/LegacyPassNameParser.h" static llvm::cl::list<const llvm::PassInfo*, bool, llvm::PassNameParser> PassList(llvm::cl::desc("Optimizations available:")); rdar://problem/19212448 llvm-svn: 224186
* [PowerPC] Add a DAGToDAG peephole to remove unnecessary zero-extsHal Finkel2014-12-123-5/+310
| | | | | | | | | | | | | | | | | | | | On PPC64, we end up with lots of i32 -> i64 zero extensions, not only from all of the usual places, but also from the ABI, which specifies that values passed are zero extended. Almost all 32-bit PPC instructions in PPC64 mode are defined to do *something* to the higher-order bits, and for some instructions, that action clears those bits (thus providing a zero-extended result). This is especially common after rotate-and-mask instructions. Adding an additional instruction to zero-extend the results of these instructions is unnecessary. This PPCISelDAGToDAG peephole optimization examines these zero-extensions, and looks back through their operands to see if all instructions will implicitly zero extend their results. If so, we convert these instructions to their 64-bit variants (which is an internal change only, the actual encoding of these instructions is the same as the original 32-bit ones) and remove the unnecessary zero-extension (changing where the INSERT_SUBREG instructions are to make everything internally consistent). llvm-svn: 224169
* ValueTracking: Don't recurse too deeply in computeKnownBitsFromAssumeDavid Majnemer2014-12-121-0/+4
| | | | | | | | | Respect the MaxDepth recursion limit, doing otherwise will trigger an assert in computeKnownBits. This fixes PR21891. llvm-svn: 224168
* [ARMConstantIsland] Insert tbb/tbh optimization where previous jump table ↵Chad Rosier2014-12-121-1/+3
| | | | | | resided. llvm-svn: 224165
* Pass EC by reference to MemoryBufferMMapFile to return error code.Yaron Keren2014-12-121-1/+1
| | | | | | Patch by Kim Grasman! llvm-svn: 224159
* Clean up static analyzer warnings.Michael Ilseman2014-12-126-9/+14
| | | | | | | | | Clang's static analyzer found several potential cases of undefined behavior, use of un-initialized values, and potentially null pointer dereferences in tablegen, Support, MC, and ADT. This cleans them up with specific assertions on the assumptions of the code. llvm-svn: 224154
* [Hexagon] Adding double word add/min/minu/max/maxu instructions and tests.Colin LeMahieu2014-12-121-21/+63
| | | | llvm-svn: 224153
* [Hexagon] Adding J class call instructions.Colin LeMahieu2014-12-122-9/+48
| | | | llvm-svn: 224150
* IR: Don't track nullptr on metadata RAUWDuncan P. N. Exon Smith2014-12-121-1/+2
| | | | | | | | | | | | | | | | | The RAUW support in `Metadata` supports going to `nullptr` specifically to handle values being deleted, causing `ValueAsMetadata` to be deleted. Fix the case where the reference is from a `TrackingMDRef` (as opposed to an `MDOperand` or a `MetadataAsValue`). This is surprisingly rare -- metadata tracked by `TrackingMDRef` going to null -- but it came up in an openSUSE bootstrap during inlining. The tracking ref was held by the `ValueMap` because it was referencing a local, the basic block containing the local became dead after it had been merged in, and when the local was deleted, the tracking ref asserted in an `isa`. llvm-svn: 224146
* MAP_FILE is the default. We don't need to add it.Rafael Espindola2014-12-121-3/+0
| | | | llvm-svn: 224144
* More code format fix from r224133, NFCSteven Wu2014-12-121-2/+1
| | | | llvm-svn: 224140
* Remove silly left over from the Windows resize_file implementation.Rafael Espindola2014-12-121-1/+0
| | | | | | | I didn't notice the problem first because on a non debug build the CRT was just exiting the process without any message. llvm-svn: 224139
* Move the resize file feature from mapped_file_region to the only user.Rafael Espindola2014-12-122-13/+5
| | | | | | This removes a duplicated stat on every file that llvm-ar looks at. llvm-svn: 224138
* Pass a FD to resise_file and add a testcase.Rafael Espindola2014-12-122-17/+6
| | | | | | I will add a real use in another commit. llvm-svn: 224136
* Remove unused feature. NFC.Rafael Espindola2014-12-121-7/+1
| | | | llvm-svn: 224135
* Restructure code from r224097. NFCSteven Wu2014-12-121-12/+12
| | | | llvm-svn: 224133
* [AVX512] Enabling bit logic loweringRobert Khasanov2014-12-122-0/+9
| | | | | | Added lowering tests. llvm-svn: 224132
* [mips] Enable code generation for MIPS-III.Vasileios Kalintiris2014-12-123-9/+17
| | | | | | | | | | | | | | | | | | Summary: This commit enables the MIPS-III target and adds support for code generation of SELECT nodes. We have to use pseudo-instructions with custom inserters for these nodes as MIPS-III CPUs do not have conditional-move instructions. Depends on D6212 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6464 llvm-svn: 224128
* [AVX512] Enabling MIN/MAX lowering.Robert Khasanov2014-12-122-4/+19
| | | | | | Added lowering tests. llvm-svn: 224127
* Reapply "[MachineScheduler] Fix for PR21807: minor code difference building ↵Andrea Di Biagio2014-12-121-1/+3
| | | | | | | | | | | with/without -g." This reapplies r224118 with a fix for test 'misched-code-difference-with-debug.ll'. That test was failing on some buildbots because it was x86 specific but it was missing a target triple. Added an explicit triple to test misched-code-difference-with-debug.ll. llvm-svn: 224126
* [Reassociate] Use dbgs() instead of errs().Chad Rosier2014-12-121-2/+2
| | | | llvm-svn: 224125
* [mips] Support SELECT nodes for targets that don't have conditional-move ↵Vasileios Kalintiris2014-12-124-0/+129
| | | | | | | | | | | | | | | | | | | | | | | | instructions. Summary: For Mips targets that do not have conditional-move instructions, ie. targets before MIPS32 and MIPS-IV, we have to insert a diamond control-flow pattern in order to support SELECT nodes. In order to do that, we add pseudo-instructions with a custom inserter that emits the necessary control-flow that selects the correct value. With this patch we add complete support for code generation of Mips-II targets based on the LLVM test-suite. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6212 llvm-svn: 224124
* [AVX512] Minor fix in lowering pattern for broadcast intrustions.Robert Khasanov2014-12-121-6/+5
| | | | | | No functional change. llvm-svn: 224122
* Revert: [MachineScheduler] Fix for PR21807: minor code difference building ↵Andrea Di Biagio2014-12-121-3/+1
| | | | | | | | with/without -g. Test 'misched-code-difference-with-debug.ll' was failing on some buildbots. llvm-svn: 224121
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