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* When determining the new index for an insertelement, we may not assume that anNick Lewycky2013-06-011-7/+9
| | | | | | | | | | index greater than the size of the vector is invalid. The shuffle may be shrinking the size of the vector. Fixes a crash! Also drop the maximum recursion depth of the safety check for this optimization to five. llvm-svn: 183080
* Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics ↵Venkatraman Govindaraju2013-06-011-0/+6
| | | | | | as non-leaf functions. llvm-svn: 183079
* SimplifyCFG: Fix typo in comment for ComputeSpeculationCostDavid Majnemer2013-06-011-1/+1
| | | | llvm-svn: 183078
* Move getRealLinkageName to a common place and remove all the duplicates of it.Benjamin Kramer2013-06-014-65/+25
| | | | | | Also simplify code a bit while there. No functionality change. llvm-svn: 183076
* Move object construction into [] so the temporary can be moved.Benjamin Kramer2013-06-011-5/+3
| | | | | | No functionality change. llvm-svn: 183075
* APInt: Simplify code. No functionality change.Benjamin Kramer2013-06-011-36/+2
| | | | llvm-svn: 183073
* APFloat: Use isDenormal instead of hand-rolled code to check for denormals.Benjamin Kramer2013-06-011-1/+1
| | | | llvm-svn: 183072
* Revert r183069: "TMP: LEA64_32r fixing"Tim Northover2013-06-014-155/+54
| | | | | | Very sorry, it was committed from the wrong branch by mistake. llvm-svn: 183070
* TMP: LEA64_32r fixingTim Northover2013-06-014-54/+155
| | | | llvm-svn: 183069
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-06-014-32/+45
| | | | | | | | | | | | | | The MOV64ri64i32 instruction required hacky MCInst lowering because it was allocated as setting a GR64, but the eventual instruction ("movl") only set a GR32. This converts it into a so-called "MOV32ri64" which still accepts a (appropriate) 64-bit immediate but defines a GR32. This is then converted to the full GR64 by a SUBREG_TO_REG operation, thus keeping everyone happy. This fixes a typo in the opcode field of the original patch, which should make the legact JIT work again (& adds test for that problem). llvm-svn: 183068
* [Sparc] Generate correct code for leaf functions with stack objects Venkatraman Govindaraju2013-06-014-30/+79
| | | | llvm-svn: 183067
* Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha2013-05-319-39/+40
| | | | | | | This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. llvm-svn: 183061
* Prevent loop-unroll from making assumptions about undefined behavior.Andrew Trick2013-05-311-5/+14
| | | | | | | | | | | | | | Fixes rdar:14036816, PR16130. There is an opportunity to compute precise trip counts for 'or' expressions and multi-exit loops. rdar:14038809: Optimize trip count computation for multi-exit loops. To do this we need to record the fact that ExitLimit assumes NSW. When it does not we can safely assume that the loop trip count is the minimum ExitLimt across all subexpressions and loop exits. llvm-svn: 183060
* Temporarily Revert "X86: change MOV64ri64i32 into MOV32ri64" as itEric Christopher2013-05-314-45/+32
| | | | | | seems to have caused PR16192 and other JIT related failures. llvm-svn: 183059
* Const-ify some printing and dumping code for DIEValues.Eric Christopher2013-05-312-13/+13
| | | | llvm-svn: 183057
* Add support for adding the contents of a StringRef to the MD5 hash.Eric Christopher2013-05-311-0/+8
| | | | llvm-svn: 183054
* Convert more unsigned char -> uint8_t.Eric Christopher2013-05-311-1/+1
| | | | llvm-svn: 183053
* Fix comment.Eric Christopher2013-05-311-1/+1
| | | | llvm-svn: 183052
* Move "unsigned char" -> "uint8_t".Eric Christopher2013-05-311-8/+8
| | | | llvm-svn: 183051
* LoopVectorize: Change API call to get the backedge taken countArnold Schwaighofer2013-05-311-3/+3
| | | | | | | | | | Use ScalarEvolution's getBackedgeTakenCount API instead of getExitCount since that is really what we want to know. Using the more specific getExitCount was safe because we made sure that there is only one exiting block. No functionality change. llvm-svn: 183047
* Loop Strength Reduce: Scaling factor cost.Quentin Colombet2013-05-313-3/+74
| | | | | | | | | | | | Account for the cost of scaling factor in Loop Strength Reduce when rating the formulae. This uses a target hook. The default implementation of the hook is: if the addressing mode is legal, the scaling factor is free. <rdar://problem/13806271> llvm-svn: 183045
* Rename COFFYaml.h to COFFYAML.h for consistency.Rafael Espindola2013-05-311-1/+1
| | | | llvm-svn: 183042
* Don't allocate temporary string for section data.Rafael Espindola2013-05-311-0/+17
| | | | llvm-svn: 183040
* LoopVectorize: PHIs with only outside users should prevent vectorizationArnold Schwaighofer2013-05-311-13/+30
| | | | | | | | | | We check that instructions in the loop don't have outside users (except if they are reduction values). Unfortunately, we skipped this check for if-convertable PHIs. Fixes PR16184. llvm-svn: 183035
* NVPTX: Don't even create a regalloc if we're not going to use it.Benjamin Kramer2013-05-311-2/+7
| | | | | | Fixes a leak found by valgrind. llvm-svn: 183031
* Modify how the formulae are rated in Loop Strength Reduce.Quentin Colombet2013-05-311-6/+45
| | | | | | | | | | | | | | Namely, check if the target allows to fold more that one register in the addressing mode and if yes, adjust the cost accordingly. Prior to this commit, reg1 + scale * reg2 accesses were artificially preferred to reg1 + reg2 accesses. Indeed, the cost model wrongly assumed that reg1 + reg2 needs a temporary register for the computation, whereas it was correctly estimated for reg1 + scale * reg2. <rdar://problem/13973908> llvm-svn: 183021
* Add a way to define the bit range covered by a SubRegIndex.Ahmed Bougacha2013-05-314-29/+42
| | | | | | | | | | | | | NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change the instances of SubRegIndex that have a comps template arg to use the ComposedSubRegIndex class instead. In TableGen land, this adds Size and Offset attributes to SubRegIndex, and the ComposedSubRegIndex class, for which the Size and Offset are computed by TableGen. This also adds an accessor in MCRegisterInfo, and Size/Offsets for the X86 and ARM subreg indices. llvm-svn: 183020
* Remove useless code from transitioning to new EH schemeKai Nacke2013-05-311-4/+1
| | | | | | | Removes all uses of the variable UsesNewEH. Simply return false in case that no resume instructions were found. llvm-svn: 183016
* ARM: permit upper-case BE/LE on setend instructionTim Northover2013-05-311-1/+1
| | | | | | Patch by Amaury de la Vieuville. llvm-svn: 183012
* ARM: add fstmx and fldmx instructions for assemblyTim Northover2013-05-313-8/+70
| | | | | | | | | These instructions are deprecated oddities, but we still need to be able to disassemble (and reassemble) them if and when they're encountered. Patch by Amaury de la Vieuville. llvm-svn: 183011
* Simplify multiplications by vectors whose elements are powers of 2.Rafael Espindola2013-05-311-16/+48
| | | | | | Patch by Andrea Di Biagio. llvm-svn: 183005
* ARM: fix VEXT encoding corner caseTim Northover2013-05-311-5/+6
| | | | | | | | | | The disassembly of VEXT instructions was too lax in the bits checked. This fixes the case where the instruction affects Q-registers but a misaligned lane was specified (should be UNDEFINED). Patch by Amaury de la Vieuville llvm-svn: 183003
* [SystemZ] Don't use LOAD and STORE REVERSED for volatile accessesRichard Sandiford2013-05-312-9/+27
| | | | | | | | | | | | | | | | | | Unlike most -- hopefully "all other", but I'm still checking -- memory instructions we support, LOAD REVERSED and STORE REVERSED may access the memory location several times. This means that they are not suitable for volatile loads and stores. This patch is a prerequisite for better atomic load and store support. The same principle applies there: almost all memory instructions we support are inherently atomic ("block concurrent"), but LOAD REVERSED and STORE REVERSED are exceptions. Other instructions continue to allow volatile operands. I will add positive "allows volatile" tests at the same time as the "allows atomic load or store" tests. llvm-svn: 183002
* [NVPTX] Re-enable support for virtual registers in the final outputJustin Holewinski2013-05-318-66/+307
| | | | | | | | | | | | Now that 3.3 is branched, we are re-enabling virtual registers to help iron out bugs before the next release. Some of the post-RA passes do not play well with virtual registers, so we disable them for now. The needed functionality of the PrologEpilogInserter pass is copied to a new backend-specific NVPTXPrologEpilog pass. The test for this commit is not breaking the existing tests. llvm-svn: 182998
* [msan] Handle mixed track-origins and keep-going settings (llvm part).Evgeniy Stepanov2013-05-311-4/+6
| | | | | | | | | | | | | Before this change, each module defined a weak_odr global __msan_track_origins with a value of 1 if origin tracking is enabled, 0 if disabled. If there are modules with different values, any of them may win. If 0 wins, and there is at least one module with 1, the program will most likely crash. With this change, __msan_track_origins is only emitted if origin tracking is on. Then runtime library detects if there is at least one module with origin tracking, and enables runtime support for it. llvm-svn: 182997
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-05-314-32/+45
| | | | | | | | | | The MOV64ri64i32 instruction required hacky MCInst lowering because it was allocated as setting a GR64, but the eventual instruction ("movl") only set a GR32. This converts it into a so-called "MOV32ri64" which still accepts a (appropriate) 64-bit immediate but defines a GR32. This is then converted to the full GR64 by a SUBREG_TO_REG operation, thus keeping everyone happy. llvm-svn: 182991
* Fix ScalarEvolution::ComputeExitLimitFromCond for 'or' conditions.Andrew Trick2013-05-311-32/+54
| | | | | | | | | | | | | | | | Fixes PR16130 - clang produces incorrect code with loop/expression at -O2. This is a 2+ year old bug that's now holding up the release. It's a case where we knowingly made aggressive assumptions about undefined behavior. These assumptions are wrong when SCEV is computing a subexpression that does not directly control the branch. With this fix, we avoid making assumptions in those cases but still optimize the common case. SCEV's trip count computation for exits controlled by 'or' expressions is now analagous to the trip count computation for loops with multiple exits. I had already fixed the multiple exit case to be conservative. llvm-svn: 182989
* [mips] Big-endian code generation for atomic instructions.Akira Hatanaka2013-05-311-2/+16
| | | | | | Patch by Jyun-Yan You. llvm-svn: 182984
* Reapply with r182909 with a fix to the calculation of the new indices forNick Lewycky2013-05-312-2/+257
| | | | | | insertelement instructions. llvm-svn: 182976
* Remove debug print added in r182949.Ahmed Bougacha2013-05-301-1/+0
| | | | llvm-svn: 182973
* Revert r182937 and r182877.Rafael Espindola2013-05-301-17/+3
| | | | | | | | | r182877 broke MCJIT tests on ARM and r182937 was working around another failure by r182877. This should make the ARM bots green. llvm-svn: 182960
* Use the const_cast only where necessary.Bill Wendling2013-05-301-4/+4
| | | | llvm-svn: 182950
* MCObjectSymbolizer: Switch from IntervalMap to sorted vector, following r182625.Ahmed Bougacha2013-05-301-10/+46
| | | | | | | This removes the need for the missing SectionRef operator< workaround, and fixes an IntervalMap assert about alignment on MSVC. llvm-svn: 182949
* Implement IEEE-754R 2008 nextUp/nextDown functions in the guise of the ↵Michael Gottesman2013-05-301-20/+228
| | | | | | | | function APFloat::next(bool nextDown). rdar://13852078 llvm-svn: 182945
* X86: use sub-register sequences for MOV*r0 operationsTim Northover2013-05-305-100/+74
| | | | | | | | | | | | Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. llvm-svn: 182928
* Fix rematerialization into physical registers.Tim Northover2013-05-301-2/+3
| | | | | | | | | | | | | | | | | r182872 introduced a bug in how the register-coalescer's rematerialization handled defining a physical register. It relied on the output of the coalescer's setRegisters method to determine whether the replacement instruction needed an implicit-def. However, this value isn't necessarily the same as the CopyMI's actual destination register which is what the rest of the basic-block expects us to be defining. The commit changes the rematerializer to use the actual register attached to CopyMI in its decision. This will be tested soon by an X86 patch which moves everything to using MOV32r0 instead of other sizes. llvm-svn: 182925
* [NVPTX] Fix case where a sext load of an i1 type may produce anJustin Holewinski2013-05-301-2/+4
| | | | | | ld.u1 instead of an ld.u8. llvm-svn: 182924
* X86: change zext moves to use sub-register infrastructure.Tim Northover2013-05-305-71/+74
| | | | | | | | | | | | 32-bit writes on amd64 zero out the high bits of the corresponding 64-bit register. LLVM makes use of this for zero-extension, but until now relied on custom MCLowering and other code to fixup instructions. Now we have proper handling of sub-registers, this can be done by creating SUBREG_TO_REG instructions at selection-time. Should be no change in functionality. llvm-svn: 182921
* [SystemZ] Enable unaligned accessesRichard Sandiford2013-05-302-0/+11
| | | | | | | The code to distinguish between unaligned and aligned addresses was already there, so this is mostly just a switch-on-and-test process. llvm-svn: 182920
* Revert r182909.Evgeniy Stepanov2013-05-302-246/+0
| | | | | | PR/16177 llvm-svn: 182919
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