| Commit message (Collapse) | Author | Age | Files | Lines |
| ... | |
| |
|
|
|
|
|
|
|
|
|
|
| |
Summary: This adds the ELF32 writer for AVR.
Reviewers: kparzysz
Subscribers: beanz, mgorny
Differential Revision: https://reviews.llvm.org/D25031
llvm-svn: 282856
|
| |
|
|
|
|
| |
It was accidentally committed.
llvm-svn: 282855
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Summary:
This change adds the AVR assembly instruction printer.
No tests are included in this patch. I have left them downstream so we can
add them once `llc` successfully runs (there's very few components left
to upstream until this).
Reviewers: arsenm, kparzysz
Subscribers: wdng, beanz, mgorny
Differential Revision: https://reviews.llvm.org/D25028
llvm-svn: 282854
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Summary:
Previously, when allocating unspillable live ranges, we would never
attempt to split. We would always bail out and try last ditch graph
recoloring.
This patch changes this by attempting to split all live intervals before
performing recoloring.
This fixes LLVM bug PR14879.
I can't add test cases for any backends other than AVR because none of
them have small enough register classes to trigger the bug.
Reviewers: qcolombet
Subscribers: MatzeB
Differential Revision: https://reviews.llvm.org/D25070
llvm-svn: 282852
|
| |
|
|
|
|
| |
stack spilling pseudos for XMM16-31 and YMM16-31 without VLX.
llvm-svn: 282843
|
| |
|
|
|
|
| |
without VLX to teh isFrameLoadOpcode and isFrameStoreOpcode.
llvm-svn: 282842
|
| |
|
|
|
|
|
|
| |
addRegisterClass regardless of whether AVX512/VLX is enabled or not."
Turns out this doesn't pass verify-machineinstrs.
llvm-svn: 282841
|
| |
|
|
| |
llvm-svn: 282839
|
| |
|
|
| |
llvm-svn: 282838
|
| |
|
|
|
|
|
|
| |
also missing. Change register class to include the extra 16 AVX512 registers.
I'm not completely sure what this method does or why all the 256-bit VTs returned VR128RegClass when the comments on the method definiton say it should return the largest super register class. I just figured AVX-512 should be similar.
llvm-svn: 282836
|
| |
|
|
|
|
|
|
|
|
| |
addRegisterClass regardless of whether AVX512/VLX is enabled or not.
If AVX512 is disabled, the registers should already be marked reserved. Pattern predicates and register classes on instructions should take care of most of the rest. Loads/stores and physical register copies for XMM16-31 and YMM16-31 without VLX have already been taken care of.
I'm a little unclear why this changed the register allocation of the SSE2 run of the sad.ll test, but the registers selected appear to be valid after this change.
llvm-svn: 282835
|
| |
|
|
| |
llvm-svn: 282834
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Summary:
We don't want to decay hot callsites to import chains of hot
callsites. The same mechanism is used in LIPO.
Reviewers: tejohnson, eraman, mehdi_amini
Subscribers: llvm-commits, mehdi_amini
Differential Revision: https://reviews.llvm.org/D24976
llvm-svn: 282833
|
| |
|
|
|
|
|
|
|
|
| |
For some reason there are both of these available, except
for scalar 64-bit compares which only has u64. I'm not sure
why there are both (I'm guessing it's for the one bit inputs we
don't use), but for consistency always using the
unsigned one.
llvm-svn: 282832
|
| |
|
|
|
|
| |
works with the new one (trace-pc-guard)
llvm-svn: 282831
|
| |
|
|
|
|
| |
the feature counter of the old best input
llvm-svn: 282829
|
| |
|
|
| |
llvm-svn: 282826
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Summary:
This lets people link against LLVM and their own version of the UTF
library.
I determined this only affects llvm, clang, lld, and lldb by running
$ git grep -wl 'UTF[0-9]\+\|\bConvertUTF\bisLegalUTF\|getNumBytesFor' | cut -f 1 -d '/' | sort | uniq
clang
lld
lldb
llvm
Tested with
ninja lldb
ninja check-clang check-llvm check-lld
(ninja check-lldb doesn't complete for me with or without this patch.)
Reviewers: rnk
Subscribers: klimek, beanz, mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D24996
llvm-svn: 282822
|
| |
|
|
|
|
| |
This completes LV.
llvm-svn: 282821
|
| |
|
|
| |
llvm-svn: 282820
|
| |
|
|
|
|
|
|
|
| |
Code that doesn't use floating point and doesn't use SSE (kernel code)
shouldn't save and restore SSE registers.
Fixes PR30503
llvm-svn: 282819
|
| |
|
|
|
|
|
|
| |
This uses a TableGen'ed like structure for all 3-operands instrs.
The output of the RegBankSelect pass should be identical but the
RegisterBankInfo will do less dynamic allocations.
llvm-svn: 282817
|
| |
|
|
|
|
|
| |
This is the kind of input TableGen should generate at some point.
NFC.
llvm-svn: 282816
|
| |
|
|
|
|
|
|
|
| |
Make sure that the ValueMappings contain the value we expect at the
indices we expect.
NFC.
llvm-svn: 282815
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
(Recommit after making sure IsVerbose gets properly initialized in
DiagnosticInfoOptimizationBase. See previous commit that takes care of
this.)
OptimizationRemarkAnalysis directly takes the role of the report that is
generated by LAA.
Then we need the magic to be able to turn an LAA remark into an LV
remark. This is done via a new OptimizationRemark ctor.
llvm-svn: 282813
|
| |
|
|
|
|
|
|
| |
Also, make foldSelectExtConst() a member of InstCombiner, remove
unnecessary parameters from its interface, and group visitSelectInst
helpers together in the header file.
llvm-svn: 282796
|
| |
|
|
| |
llvm-svn: 282768
|
| |
|
|
|
|
| |
Check for existance and not truth value.
llvm-svn: 282767
|
| |
|
|
|
|
|
|
|
| |
load command that uses the MachO::entry_point_command type
but not used in llvm libObject code but used in llvm tool code.
This includes just the LC_MAIN load command.
llvm-svn: 282766
|
| |
|
|
| |
llvm-svn: 282761
|
| |
|
|
|
|
|
|
| |
This reverts commit r282758.
There are some clang failures I haven't seen.
llvm-svn: 282759
|
| |
|
|
|
|
|
|
|
|
| |
OptimizationRemarkAnalysis directly takes the role of the report that is
generated by LAA.
Then we need the magic to be able to turn an LAA remark into an LV
remark. This is done via a new OptimizationRemark ctor.
llvm-svn: 282758
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Instead of producing a mapping for all the operands, we only generate a
mapping for the definition. Indeed, the other operands are not
constrained by the instruction and thus, we should leave the choice to
the actual definition to do the right thing.
In pratice this is almost NFC, but with one advantage. We will have only
one instance of OperandsMapping for each copy and phi that map to one
register bank instead of one different instance for each different
number of operands for each copy and phi.
llvm-svn: 282756
|
| |
|
|
| |
llvm-svn: 282755
|
| |
|
|
|
|
| |
OptimizationRemarkAnalysisAliasing to new streaming API for opt remarks
llvm-svn: 282742
|
| |
|
|
| |
llvm-svn: 282740
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The VS debugger doesn't appear to understand the 0x68 or 0x69 type
indices, which were probably intended for use on a platform where a C
'int' is 8 bits. So, use the character types instead. Clang was already
using the character types because '[u]int8_t' is usually defined in
terms of 'char'.
See the Rust issue for screenshots of what VS does:
https://github.com/rust-lang/rust/issues/36646
Fixes PR30552
llvm-svn: 282739
|
| |
|
|
| |
llvm-svn: 282737
|
| |
|
|
|
|
|
|
|
| |
load command that uses the Mach::source_version_command type
but not used in llvm libObject code but used in llvm tool code.
This includes just the LC_SOURCE_VERSION load command.
llvm-svn: 282736
|
| |
|
|
|
|
| |
one array of guards per function, instead of one guard per BB. reorganize the code so that trace-pc-guard does not create unneeded globals
llvm-svn: 282735
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Summary:
Not tunned up heuristic, but with this small heuristic there is about
+0.10% improvement on SPEC 2006
Reviewers: tejohnson, mehdi_amini, eraman
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D24940
llvm-svn: 282733
|
| |
|
|
| |
llvm-svn: 282732
|
| |
|
|
|
|
| |
This is an attempt to fix a windows bot.
llvm-svn: 282730
|
| |
|
|
|
|
| |
Here we can already remove the member function emitAnalysis.
llvm-svn: 282729
|
| |
|
|
|
|
| |
This will be shared between Legality and CostModel.
llvm-svn: 282728
|
| |
|
|
|
|
|
|
| |
The last one remaining after which emitAnalysis can be removed is when
we convert the LAA's report to a vectorization report. This requires
converting LAA to the new interface first.
llvm-svn: 282726
|
| |
|
|
|
|
|
| |
Also renamed the function to emitRemarkWithHints to better reflect what
the function actually does.
llvm-svn: 282723
|
| |
|
|
| |
llvm-svn: 282721
|
| |
|
|
|
|
|
|
|
|
| |
The shuffle mask decodes have a large amount of repeated code extracting/splitting mask values from Constant data.
This patch pulls all of this duplicated code into a single helper function to identify undef elements and combine/split constant integer data into the requested shuffle mask elements.
Updated PSHUFB/VPERMIL/VPERMIL2/VPPERM decoders to use it (VPERMV/VPERMV3 could be converted as well in the future).
llvm-svn: 282720
|
| |
|
|
| |
llvm-svn: 282717
|